ACEC/circuit.cpp

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2022-10-23 15:29:41 +08:00
#include "circuit.h"
Gate* Gates;
std::vector<int> circuit_inputs;
int circuit_output;
void read_verilog_from_file(const char *filename) {
using namespace std;
ifstream file(filename);
cmatch m;
string line;
// all inputs and outputs
cout << "I/O:" << endl;
getline(file, line);
while(regex_search(line.c_str(), m, regex("[x|y]\\d+"))) {
cout << m.str(0) << " ";
line = m.suffix().str();
}
cout << endl;
// skip detailed I/O
getline(file, line);
getline(file, line);
int maxvar = 0;
// all wires
cout << "wires: " << endl;
getline(file, line);
while(regex_search(line.c_str(), m, regex("n\\d+"))) {
string wire = m.str(0);
cout << wire << " ";
maxvar = max(maxvar, std::atoi(wire.substr(1).c_str()));
line = m.suffix().str();
}
cout << endl;
assert(maxvar);
cout << "maxvar: " << maxvar << endl;
// allcate for global gates table
Gates = new Gate[maxvar + 1];
while(true) {
getline(file, line);
if(line == "endmodule") break;
cout << line << endl;
std::vector<int> vars;
string copy = line;
while(regex_search(copy.c_str(), m, regex("~?[xyn]\\d+"))) {
string str = m.str(0);
int sign = 1;
if(str[0] == '~') {
sign = -1;
str = str.substr(1);
}
// remove x , y or n
str = str.substr(1);
vars.push_back(sign * atoi(str.c_str()));
copy = m.suffix().str();
}
if(regex_match(line.c_str(), m, regex(" assign ~?[xyn]\\d+ = ~?[xyn]\\d+ (& ~?[xyn]\\d+)+ ;"))) {
cout << "MATCH AND: " ;
} else if(regex_match(line.c_str(), m, regex(" assign ~?[xyn]\\d+ = ~?[xyn]\\d+ (\\^ ~?[xyn]\\d+)+ (\\^ 1\\'b0)+ ;"))) {
cout << "MATCH XOR: " ;
} else if(regex_match(line.c_str(), m, regex(" assign ~?[xyn]\\d+ = ~?[xyn]\\d+ (\\| ~?[xyn]\\d+)+ ;"))) {
cout << "MATCH OR: " ;
} else if(regex_match(line.c_str(), m, regex(" assign ~?y\\d+ = ~?[xyn]\\d+ ;"))) {
cout << "MATCH OUTPUT: " ;
} else {
cout << "MATCH MAJ: " ;
}
for(auto& var : vars) {
cout << var << " ";
}
cout << endl;
}
}