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establish circuit structure

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This commit is contained in:
YuhangQ 2022-10-23 16:14:11 +08:00
parent 01a2ea2226
commit 53916eb422
4 changed files with 239 additions and 286 deletions
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1
acec.cpp
View File

@ -175,6 +175,7 @@ int main(int argv, char* args[]) {
system(also_cmd);
read_verilog_from_file("test.v");
print_circuit_structure();
// std::map<std::string, Polynomial*> nas;
// for(int i=1; i<=S->maxvar; i++) {

111
circuit.cpp
View File

@ -1,6 +1,7 @@
#include "circuit.h"
Gate* Gates;
const char* GateName[4] = {"XOR", "MAJ", "AND", "OR"};
CircuitGate* Gates;
std::vector<int> circuit_inputs;
int circuit_output;
@ -12,43 +13,45 @@ void read_verilog_from_file(const char *filename) {
cmatch m;
string line;
// all inputs and outputs
cout << "I/O:" << endl;
// skip I/Os
getline(file, line);
//cout << "inputs: " << endl;
getline(file, line);
while(regex_search(line.c_str(), m, regex("[x|y]\\d+"))) {
cout << m.str(0) << " ";
//cout << atoi(m.str(0).substr(1).c_str()) << " ";
circuit_inputs.push_back(atoi(m.str(0).substr(1).c_str()) + 1);
line = m.suffix().str();
}
cout << endl;
//cout << endl;
// skip detailed I/O
getline(file, line);
// skip outputs;
getline(file, line);
int maxvar = 0;
// all wires
cout << "wires: " << endl;
//cout << "wires: " << endl;
getline(file, line);
while(regex_search(line.c_str(), m, regex("n\\d+"))) {
string wire = m.str(0);
cout << wire << " ";
//cout << wire << " ";
maxvar = max(maxvar, std::atoi(wire.substr(1).c_str()));
line = m.suffix().str();
}
cout << endl;
//cout << endl;
assert(maxvar);
cout << "maxvar: " << maxvar << endl;
//cout << "maxvar: " << maxvar + 1 << endl;
// allcate for global gates table
Gates = new Gate[maxvar + 1];
Gates = new CircuitGate[maxvar + 2];
while(true) {
getline(file, line);
if(line == "endmodule") break;
cout << line << endl;
//cout << line << endl;
std::vector<int> vars;
string copy = line;
@ -61,27 +64,87 @@ void read_verilog_from_file(const char *filename) {
}
// remove x , y or n
str = str.substr(1);
vars.push_back(sign * atoi(str.c_str()));
vars.push_back(sign * (atoi(str.c_str()) + 1));
copy = m.suffix().str();
}
int id = vars[0];
vars.erase(vars.begin());
CircuitGate &gate = Gates[id];
if(regex_match(line.c_str(), m, regex(" assign ~?[xyn]\\d+ = ~?[xyn]\\d+ (& ~?[xyn]\\d+)+ ;"))) {
cout << "MATCH AND: " ;
//cout << "MATCH AND: " ;
gate.type = AND;
gate.inputs.insert(gate.inputs.end(), vars.begin(), vars.end());
} else if(regex_match(line.c_str(), m, regex(" assign ~?[xyn]\\d+ = ~?[xyn]\\d+ (\\^ ~?[xyn]\\d+)+ (\\^ 1\\'b0)+ ;"))) {
cout << "MATCH XOR: " ;
//cout << "MATCH XOR: " ;
gate.type = XOR;
gate.inputs.insert(gate.inputs.end(), vars.begin(), vars.end());
} else if(regex_match(line.c_str(), m, regex(" assign ~?[xyn]\\d+ = ~?[xyn]\\d+ (\\| ~?[xyn]\\d+)+ ;"))) {
cout << "MATCH OR: " ;
//cout << "MATCH OR: " ;
gate.type = OR;
gate.inputs.insert(gate.inputs.end(), vars.begin(), vars.end());
} else if(regex_match(line.c_str(), m, regex(" assign ~?y\\d+ = ~?[xyn]\\d+ ;"))) {
cout << "MATCH OUTPUT: " ;
//cout << "MATCH OUTPUT: " ;
circuit_output = vars[0];
} else {
cout << "MATCH MAJ: " ;
//cout << "MATCH MAJ: " ;
set<int> tmp;
for(auto& var : vars) tmp.insert(var);
assert(tmp.size() == 3);
gate.type = MAJ;
gate.inputs.insert(gate.inputs.end(), tmp.begin(), tmp.end());
}
for(auto& var : vars) {
cout << var << " ";
}
cout << endl;
// for(auto& var : vars) {
// cout << var << " ";
// }
// cout << endl;
}
recalulate_fanouts();
calulate_topo_index();
}
void calulate_topo_index() {
int topo_count[circuit_output + 1];
memset(topo_count, 0, sizeof(topo_count));
std::queue<int> q;
int cnt = 0;
for(auto& in : circuit_inputs) {
Gates[in].topo_index = ++cnt;
q.push(in);
}
while(!q.empty()) {
int u = q.front(); q.pop();
for(auto &fanout : Gates[u].fanouts) {
topo_count[fanout]++;
if(topo_count[fanout] == Gates[fanout].inputs.size()) {
Gates[fanout].topo_index = ++cnt;
q.push(fanout);
}
}
}
}
void recalulate_fanouts() {
for(int i=1; i<=circuit_output; i++) {
Gates[i].fanouts.clear();
}
for(int i=1; i<=circuit_output; i++) {
for(int in : Gates[i].inputs) {
Gates[abs(in)].fanouts.push_back(i);
}
}
}
void print_circuit_structure() {
for(int i=1; i<=circuit_output; i++) {
printf(" Gate %d = %s (", i, GateName[Gates[i].type]);
for(auto& in : Gates[i].inputs) {
printf(" %d", in);
}
printf(" ) topo: %d \n", Gates[i].topo_index);
}
}

13
circuit.h
View File

@ -6,14 +6,21 @@ enum GateType {
XOR, MAJ, AND, OR
};
struct Gate {
struct CircuitGate {
GateType type;
std::vector<int> inputs;
std::vector<int> output;
std::vector<int> fanouts;
int topo_index;
};
extern Gate* Gates;
extern const char* GateName[4];
extern CircuitGate* Gates;
extern std::vector<int> circuit_inputs;
extern int circuit_output;
void read_verilog_from_file(const char *);
void read_verilog_from_file(const char *);
void print_circuit_structure();
void recalulate_fanouts();
void calulate_topo_index();

400
result.txt
View File

@ -1,259 +1,141 @@
I/O:
x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 y0
wires:
n15 n16 n17 n18 n19 n20 n21 n22 n23 n24 n25 n26 n27 n28 n29 n30 n31 n32 n33 n34 n35 n36 n37 n38 n39 n40 n41 n42 n43 n44 n45 n46 n47 n48 n49 n50 n51 n52 n53 n54 n55 n56 n57 n58 n59 n60 n61 n62 n63 n64 n65 n66 n67 n68 n69 n70 n71 n72 n73 n74 n75 n76 n77 n78 n79 n80 n81 n82 n83 n84 n85 n86 n87 n88 n89 n90 n91 n92 n93 n94 n95 n96 n97 n98 n99 n100 n101 n102 n103 n104 n105 n106 n107 n108 n109 n110 n111 n112 n113 n114 n115 n116 n117 n118 n119 n120 n121 n122 n123 n124 n125 n126 n127 n128 n129 n130 n131 n132 n133 n134 n135 n136 n137 n138 n139 n140
maxvar: 140
assign n39 = x5 & x11 ;
MATCH AND: 39 5 11
assign n38 = x1 & x6 ;
MATCH AND: 38 1 6
assign n40 = n39 ^ n38 ^ 1'b0 ;
MATCH XOR: 40 39 38
assign n60 = x11 & x13 ;
MATCH AND: 60 11 13
assign n61 = n38 & n60 ;
MATCH AND: 61 38 60
assign n68 = x0 & x10 ;
MATCH AND: 68 0 10
assign n59 = x9 & x13 ;
MATCH AND: 59 9 13
assign n121 = n68 ^ n59 ^ 1'b0 ;
MATCH XOR: 121 68 59
assign n69 = x3 & x4 ;
MATCH AND: 69 3 4
assign n122 = n121 ^ n69 ^ 1'b0 ;
MATCH XOR: 122 121 69
assign n123 = ( n40 & n61 ) | ( n40 & n122 ) | ( n61 & n122 ) ;
MATCH MAJ: 123 40 61 40 122 61 122
assign n35 = x6 & x11 ;
MATCH AND: 35 6 11
assign n36 = x1 & x5 ;
MATCH AND: 36 1 5
assign n37 = n35 & n36 ;
MATCH AND: 37 35 36
assign n19 = x5 & x6 ;
MATCH AND: 19 5 6
assign n18 = x8 & x11 ;
MATCH AND: 18 8 11
assign n21 = n19 ^ n18 ^ 1'b0 ;
MATCH XOR: 21 19 18
assign n108 = n37 ^ n21 ^ 1'b0 ;
MATCH XOR: 108 37 21
assign n44 = x0 & x3 ;
MATCH AND: 44 0 3
assign n109 = n108 ^ n44 ^ 1'b0 ;
MATCH XOR: 109 108 44
assign n45 = x2 & x10 ;
MATCH AND: 45 2 10
assign n34 = x1 & x9 ;
MATCH AND: 34 1 9
assign n106 = n45 ^ n34 ^ 1'b0 ;
MATCH XOR: 106 45 34
assign n46 = x4 & x13 ;
MATCH AND: 46 4 13
assign n107 = n106 ^ n46 ^ 1'b0 ;
MATCH XOR: 107 106 46
assign n124 = n109 ^ n107 ^ 1'b0 ;
MATCH XOR: 124 109 107
assign n105 = ( n59 & n68 ) | ( n59 & n69 ) | ( n68 & n69 ) ;
MATCH MAJ: 105 59 68 59 69 68 69
assign n125 = n124 ^ n105 ^ 1'b0 ;
MATCH XOR: 125 124 105
assign n73 = x4 & x10 ;
MATCH AND: 73 4 10
assign n82 = x3 & x9 ;
MATCH AND: 82 3 9
assign n84 = x3 & x6 ;
MATCH AND: 84 3 6
assign n126 = x9 & x10 ;
MATCH AND: 126 9 10
assign n127 = n84 & n126 ;
MATCH AND: 127 84 126
assign n128 = ( n73 & n82 ) | ( n73 & n127 ) | ( n82 & n127 ) ;
MATCH MAJ: 128 73 82 73 127 82 127
assign n129 = n122 ^ n61 ^ 1'b0 ;
MATCH XOR: 129 122 61
assign n130 = n129 ^ n40 ^ 1'b0 ;
MATCH XOR: 130 129 40
assign n63 = x6 & x13 ;
MATCH AND: 63 6 13
assign n62 = x1 & x11 ;
MATCH AND: 62 1 11
assign n64 = n63 ^ n62 ^ 1'b0 ;
MATCH XOR: 64 63 62
assign n94 = x10 & x11 ;
MATCH AND: 94 10 11
assign n95 = n84 & n94 ;
MATCH AND: 95 84 94
assign n132 = n126 ^ n84 ^ 1'b0 ;
MATCH XOR: 132 126 84
assign n133 = ( n60 & n95 ) | ( n60 & n132 ) | ( n95 & n132 ) ;
MATCH MAJ: 133 60 95 60 132 95 132
assign n131 = n82 ^ n73 ^ 1'b0 ;
MATCH XOR: 131 82 73
assign n134 = n131 ^ n127 ^ 1'b0 ;
MATCH XOR: 134 131 127
assign n135 = ( n64 & n133 ) | ( n64 & n134 ) | ( n133 & n134 ) ;
MATCH MAJ: 135 64 133 64 134 133 134
assign n136 = ( n128 & n130 ) | ( n128 & n135 ) | ( n130 & n135 ) ;
MATCH MAJ: 136 128 130 128 135 130 135
assign n137 = ( n123 & n125 ) | ( n123 & n136 ) | ( n125 & n136 ) ;
MATCH MAJ: 137 123 125 123 136 125 136
assign n119 = ( n105 & n107 ) | ( n105 & n109 ) | ( n107 & n109 ) ;
MATCH MAJ: 119 105 107 105 109 107 109
assign n53 = x7 & x10 ;
MATCH AND: 53 7 10
assign n25 = x5 & x9 ;
MATCH AND: 25 5 9
assign n113 = n53 ^ n25 ^ 1'b0 ;
MATCH XOR: 113 53 25
assign n111 = ( n34 & n45 ) | ( n34 & n46 ) | ( n45 & n46 ) ;
MATCH MAJ: 111 34 45 34 46 45 46
assign n16 = x6 & x8 ;
MATCH AND: 16 6 8
assign n15 = x11 & x12 ;
MATCH AND: 15 11 12
assign n17 = n16 ^ n15 ^ 1'b0 ;
MATCH XOR: 17 16 15
assign n112 = n111 ^ n17 ^ 1'b0 ;
MATCH XOR: 112 111 17
assign n114 = n113 ^ n112 ^ 1'b0 ;
MATCH XOR: 114 113 112
assign n31 = x2 & x3 ;
MATCH AND: 31 2 3
assign n115 = n114 ^ n31 ^ 1'b0 ;
MATCH XOR: 115 114 31
assign n20 = n18 & n19 ;
MATCH AND: 20 18 19
assign n117 = n115 ^ n20 ^ 1'b0 ;
MATCH XOR: 117 115 20
assign n110 = ( n21 & n37 ) | ( n21 & n44 ) | ( n37 & n44 ) ;
MATCH MAJ: 110 21 37 21 44 37 44
assign n29 = x1 & x4 ;
MATCH AND: 29 1 4
assign n28 = x0 & x13 ;
MATCH AND: 28 0 13
assign n30 = n29 ^ n28 ^ 1'b0 ;
MATCH XOR: 30 29 28
assign n116 = n110 ^ n30 ^ 1'b0 ;
MATCH XOR: 116 110 30
assign n118 = n117 ^ n116 ^ 1'b0 ;
MATCH XOR: 118 117 116
assign n120 = n119 ^ n118 ^ 1'b0 ;
MATCH XOR: 120 119 118
assign n138 = n137 ^ n120 ^ 1'b0 ;
MATCH XOR: 138 137 120
assign n83 = n82 ^ n64 ^ 1'b0 ;
MATCH XOR: 83 82 64
assign n85 = n60 & n84 ;
MATCH AND: 85 60 84
assign n87 = x10 | n85 ;
MATCH OR: 87 10 85
assign n86 = n84 ^ n60 ^ 1'b0 ;
MATCH XOR: 86 84 60
assign n88 = ( x9 & ~x10 ) | ( x9 & n86 ) | ( ~x10 & n86 ) ;
MATCH MAJ: 88 9 -10 9 86 -10 86
assign n89 = ( n85 & n87 ) | ( n85 & n88 ) | ( n87 & n88 ) ;
MATCH MAJ: 89 85 87 85 88 87 88
assign n90 = ( n73 & n83 ) | ( n73 & n89 ) | ( n83 & n89 ) ;
MATCH MAJ: 90 73 83 73 89 83 89
assign n70 = n69 ^ n68 ^ 1'b0 ;
MATCH XOR: 70 69 68
assign n80 = n70 ^ n59 ^ 1'b0 ;
MATCH XOR: 80 70 59
assign n65 = x9 | n61 ;
MATCH OR: 65 9 61
assign n66 = ( x3 & ~x9 ) | ( x3 & n64 ) | ( ~x9 & n64 ) ;
MATCH MAJ: 66 3 -9 3 64 -9 64
assign n67 = ( n61 & n65 ) | ( n61 & n66 ) | ( n65 & n66 ) ;
MATCH MAJ: 67 61 65 61 66 65 66
assign n79 = n67 ^ n40 ^ 1'b0 ;
MATCH XOR: 79 67 40
assign n81 = n80 ^ n79 ^ 1'b0 ;
MATCH XOR: 81 80 79
assign n102 = n90 ^ n81 ^ 1'b0 ;
MATCH XOR: 102 90 81
assign n74 = n44 & n73 ;
MATCH AND: 74 44 73
assign n71 = n59 ^ n40 ^ 1'b0 ;
MATCH XOR: 71 59 40
assign n72 = ( n67 & n70 ) | ( n67 & n71 ) | ( n70 & n71 ) ;
MATCH MAJ: 72 67 70 67 71 70 71
assign n77 = n74 ^ n72 ^ 1'b0 ;
MATCH XOR: 77 74 72
assign n47 = n45 ^ n44 ^ 1'b0 ;
MATCH XOR: 47 45 44
assign n48 = n47 ^ n46 ^ 1'b0 ;
MATCH XOR: 48 47 46
assign n57 = n48 ^ n34 ^ 1'b0 ;
MATCH XOR: 57 48 34
assign n41 = x13 | n37 ;
MATCH OR: 41 13 37
assign n42 = ( x9 & ~x13 ) | ( x9 & n40 ) | ( ~x13 & n40 ) ;
MATCH MAJ: 42 9 -13 9 40 -13 40
assign n43 = ( n37 & n41 ) | ( n37 & n42 ) | ( n41 & n42 ) ;
MATCH MAJ: 43 37 41 37 42 41 42
assign n56 = n43 ^ n21 ^ 1'b0 ;
MATCH XOR: 56 43 21
assign n58 = n57 ^ n56 ^ 1'b0 ;
MATCH XOR: 58 57 56
assign n78 = n77 ^ n58 ^ 1'b0 ;
MATCH XOR: 78 77 58
assign n96 = ( x9 & x10 ) | ( x9 & ~n95 ) | ( x10 & ~n95 ) ;
MATCH MAJ: 96 9 10 9 -95 10 -95
assign n97 = n96 ^ n86 ^ 1'b0 ;
MATCH XOR: 97 96 86
assign n98 = n95 & n97 ;
MATCH AND: 98 95 97
assign n99 = n89 ^ n73 ^ 1'b0 ;
MATCH XOR: 99 89 73
assign n100 = n99 ^ n83 ^ 1'b0 ;
MATCH XOR: 100 99 83
assign n101 = n98 & n100 ;
MATCH AND: 101 98 100
assign n103 = n78 & n101 ;
MATCH AND: 103 78 101
assign n104 = n102 & n103 ;
MATCH AND: 104 102 103
assign n139 = n138 ^ n104 ^ 1'b0 ;
MATCH XOR: 139 138 104
assign n91 = ( ~n78 & n81 ) | ( ~n78 & n90 ) | ( n81 & n90 ) ;
MATCH MAJ: 91 -78 81 -78 90 81 90
assign n92 = n78 & n91 ;
MATCH AND: 92 78 91
assign n75 = ( n58 & n72 ) | ( n58 & n74 ) | ( n72 & n74 ) ;
MATCH MAJ: 75 58 72 58 74 72 74
assign n52 = ( n44 & n45 ) | ( n44 & n46 ) | ( n45 & n46 ) ;
MATCH MAJ: 52 44 45 44 46 45 46
assign n49 = n34 ^ n21 ^ 1'b0 ;
MATCH XOR: 49 34 21
assign n50 = ( n43 & n48 ) | ( n43 & n49 ) | ( n48 & n49 ) ;
MATCH MAJ: 50 43 48 43 49 48 49
assign n22 = x9 | n20 ;
MATCH OR: 22 9 20
assign n23 = ( x1 & ~x9 ) | ( x1 & n21 ) | ( ~x9 & n21 ) ;
MATCH MAJ: 23 1 -9 1 21 -9 21
assign n24 = ( n20 & n22 ) | ( n20 & n23 ) | ( n22 & n23 ) ;
MATCH MAJ: 24 20 22 20 23 22 23
assign n26 = n24 ^ n17 ^ 1'b0 ;
MATCH XOR: 26 24 17
assign n27 = n26 ^ n25 ^ 1'b0 ;
MATCH XOR: 27 26 25
assign n32 = n30 ^ n27 ^ 1'b0 ;
MATCH XOR: 32 30 27
assign n33 = n32 ^ n31 ^ 1'b0 ;
MATCH XOR: 33 32 31
assign n51 = n50 ^ n33 ^ 1'b0 ;
MATCH XOR: 51 50 33
assign n54 = n52 ^ n51 ^ 1'b0 ;
MATCH XOR: 54 52 51
assign n55 = n54 ^ n53 ^ 1'b0 ;
MATCH XOR: 55 54 53
assign n76 = n75 ^ n55 ^ 1'b0 ;
MATCH XOR: 76 75 55
assign n93 = n92 ^ n76 ^ 1'b0 ;
MATCH XOR: 93 92 76
assign n140 = n139 ^ n93 ^ 1'b0 ;
MATCH XOR: 140 139 93
assign y0 = n140 ;
MATCH OUTPUT: 0 140
Gate 1 = XOR ( ) topo: 1
Gate 2 = XOR ( ) topo: 2
Gate 3 = XOR ( ) topo: 3
Gate 4 = XOR ( ) topo: 4
Gate 5 = XOR ( ) topo: 5
Gate 6 = XOR ( ) topo: 6
Gate 7 = XOR ( ) topo: 7
Gate 8 = XOR ( ) topo: 8
Gate 9 = XOR ( ) topo: 9
Gate 10 = XOR ( ) topo: 10
Gate 11 = XOR ( ) topo: 11
Gate 12 = XOR ( ) topo: 12
Gate 13 = XOR ( ) topo: 13
Gate 14 = XOR ( ) topo: 14
Gate 15 = XOR ( ) topo: 0
Gate 16 = AND ( 12 13 ) topo: 37
Gate 17 = AND ( 7 9 ) topo: 23
Gate 18 = XOR ( 17 16 ) topo: 56
Gate 19 = AND ( 9 12 ) topo: 32
Gate 20 = AND ( 6 7 ) topo: 20
Gate 21 = AND ( 19 20 ) topo: 51
Gate 22 = XOR ( 20 19 ) topo: 52
Gate 23 = OR ( 10 21 ) topo: 71
Gate 24 = MAJ ( -10 2 22 ) topo: 72
Gate 25 = MAJ ( 21 23 24 ) topo: 89
Gate 26 = AND ( 6 10 ) topo: 24
Gate 27 = XOR ( 25 18 ) topo: 100
Gate 28 = XOR ( 27 26 ) topo: 112
Gate 29 = AND ( 1 14 ) topo: 38
Gate 30 = AND ( 2 5 ) topo: 17
Gate 31 = XOR ( 30 29 ) topo: 57
Gate 32 = AND ( 3 4 ) topo: 15
Gate 33 = XOR ( 31 28 ) topo: 120
Gate 34 = XOR ( 33 32 ) topo: 127
Gate 35 = AND ( 2 10 ) topo: 25
Gate 36 = AND ( 7 12 ) topo: 33
Gate 37 = AND ( 2 6 ) topo: 19
Gate 38 = AND ( 36 37 ) topo: 53
Gate 39 = AND ( 2 7 ) topo: 21
Gate 40 = AND ( 6 12 ) topo: 34
Gate 41 = XOR ( 40 39 ) topo: 54
Gate 42 = OR ( 14 38 ) topo: 74
Gate 43 = MAJ ( -14 10 41 ) topo: 77
Gate 44 = MAJ ( 38 42 43 ) topo: 92
Gate 45 = AND ( 1 4 ) topo: 16
Gate 46 = AND ( 3 11 ) topo: 27
Gate 47 = AND ( 5 14 ) topo: 39
Gate 48 = XOR ( 46 45 ) topo: 43
Gate 49 = XOR ( 48 47 ) topo: 66
Gate 50 = XOR ( 35 22 ) topo: 73
Gate 51 = MAJ ( 44 49 50 ) topo: 103
Gate 52 = XOR ( 51 34 ) topo: 131
Gate 53 = MAJ ( 45 46 47 ) topo: 58
Gate 54 = AND ( 8 11 ) topo: 28
Gate 55 = XOR ( 53 52 ) topo: 135
Gate 56 = XOR ( 55 54 ) topo: 137
Gate 57 = XOR ( 44 22 ) topo: 104
Gate 58 = XOR ( 49 35 ) topo: 88
Gate 59 = XOR ( 58 57 ) topo: 114
Gate 60 = AND ( 10 14 ) topo: 40
Gate 61 = AND ( 12 14 ) topo: 41
Gate 62 = AND ( 39 61 ) topo: 62
Gate 63 = AND ( 2 12 ) topo: 35
Gate 64 = AND ( 7 14 ) topo: 42
Gate 65 = XOR ( 64 63 ) topo: 65
Gate 66 = OR ( 10 62 ) topo: 83
Gate 67 = MAJ ( -10 4 65 ) topo: 86
Gate 68 = MAJ ( 62 66 67 ) topo: 99
Gate 69 = AND ( 1 11 ) topo: 29
Gate 70 = AND ( 4 5 ) topo: 18
Gate 71 = XOR ( 70 69 ) topo: 46
Gate 72 = XOR ( 60 41 ) topo: 78
Gate 73 = MAJ ( 68 71 72 ) topo: 110
Gate 74 = AND ( 5 11 ) topo: 30
Gate 75 = AND ( 45 74 ) topo: 47
Gate 76 = MAJ ( 59 73 75 ) topo: 121
Gate 77 = XOR ( 76 56 ) topo: 138
Gate 78 = XOR ( 75 73 ) topo: 118
Gate 79 = XOR ( 78 59 ) topo: 125
Gate 80 = XOR ( 68 41 ) topo: 111
Gate 81 = XOR ( 71 60 ) topo: 68
Gate 82 = XOR ( 81 80 ) topo: 119
Gate 83 = AND ( 4 10 ) topo: 26
Gate 84 = XOR ( 83 65 ) topo: 87
Gate 85 = AND ( 4 7 ) topo: 22
Gate 86 = AND ( 61 85 ) topo: 63
Gate 87 = XOR ( 85 61 ) topo: 64
Gate 88 = OR ( 11 86 ) topo: 84
Gate 89 = MAJ ( -11 10 87 ) topo: 85
Gate 90 = MAJ ( 86 88 89 ) topo: 98
Gate 91 = MAJ ( 74 84 90 ) topo: 108
Gate 92 = MAJ ( -79 82 91 ) topo: 129
Gate 93 = AND ( 79 92 ) topo: 133
Gate 94 = XOR ( 93 77 ) topo: 139
Gate 95 = AND ( 11 12 ) topo: 36
Gate 96 = AND ( 85 95 ) topo: 55
Gate 97 = MAJ ( -96 10 11 ) topo: 79
Gate 98 = XOR ( 97 87 ) topo: 93
Gate 99 = AND ( 96 98 ) topo: 105
Gate 100 = XOR ( 90 74 ) topo: 109
Gate 101 = XOR ( 100 84 ) topo: 117
Gate 102 = AND ( 99 101 ) topo: 124
Gate 103 = XOR ( 91 82 ) topo: 126
Gate 104 = AND ( 79 102 ) topo: 130
Gate 105 = AND ( 103 104 ) topo: 134
Gate 106 = MAJ ( 60 69 70 ) topo: 60
Gate 107 = XOR ( 46 35 ) topo: 44
Gate 108 = XOR ( 107 47 ) topo: 67
Gate 109 = XOR ( 38 22 ) topo: 75
Gate 110 = XOR ( 109 45 ) topo: 90
Gate 111 = MAJ ( 22 38 45 ) topo: 76
Gate 112 = MAJ ( 35 46 47 ) topo: 59
Gate 113 = XOR ( 112 18 ) topo: 81
Gate 114 = XOR ( 54 26 ) topo: 45
Gate 115 = XOR ( 114 113 ) topo: 95
Gate 116 = XOR ( 115 32 ) topo: 106
Gate 117 = XOR ( 111 31 ) topo: 91
Gate 118 = XOR ( 116 21 ) topo: 115
Gate 119 = XOR ( 118 117 ) topo: 122
Gate 120 = MAJ ( 106 108 110 ) topo: 101
Gate 121 = XOR ( 120 119 ) topo: 128
Gate 122 = XOR ( 69 60 ) topo: 61
Gate 123 = XOR ( 122 70 ) topo: 82
Gate 124 = MAJ ( 41 62 123 ) topo: 96
Gate 125 = XOR ( 110 108 ) topo: 102
Gate 126 = XOR ( 125 106 ) topo: 113
Gate 127 = AND ( 10 11 ) topo: 31
Gate 128 = AND ( 85 127 ) topo: 49
Gate 129 = MAJ ( 74 83 128 ) topo: 69
Gate 130 = XOR ( 123 62 ) topo: 97
Gate 131 = XOR ( 130 41 ) topo: 107
Gate 132 = XOR ( 83 74 ) topo: 48
Gate 133 = XOR ( 127 85 ) topo: 50
Gate 134 = MAJ ( 61 96 133 ) topo: 80
Gate 135 = XOR ( 132 128 ) topo: 70
Gate 136 = MAJ ( 65 134 135 ) topo: 94
Gate 137 = MAJ ( 129 131 136 ) topo: 116
Gate 138 = MAJ ( 124 126 137 ) topo: 123
Gate 139 = XOR ( 138 121 ) topo: 132
Gate 140 = XOR ( 139 105 ) topo: 136
Gate 141 = XOR ( 140 94 ) topo: 140