parser verilog
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12
acec.cpp
12
acec.cpp
@ -1,6 +1,6 @@
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#include <bits/stdc++.h>
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#include "circuit.h"
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#include "polynomial.h"
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@ -165,6 +165,16 @@ int main(int argv, char* args[]) {
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init_mpz(19260817);
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if(argv != 2) {
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printf("usage: ./acec <AIG-FILE>\n");
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return -1;
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}
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char also_cmd[1024];
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sprintf(also_cmd, "also -c \"read_aiger %s; convert --aig_to_xmg; write_verilog -x test.v\"", args[1]);
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system(also_cmd);
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read_verilog_from_file("test.v");
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// std::map<std::string, Polynomial*> nas;
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// for(int i=1; i<=S->maxvar; i++) {
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87
circuit.cpp
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87
circuit.cpp
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@ -0,0 +1,87 @@
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#include "circuit.h"
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Gate* Gates;
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std::vector<int> circuit_inputs;
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int circuit_output;
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void read_verilog_from_file(const char *filename) {
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using namespace std;
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ifstream file(filename);
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cmatch m;
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string line;
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// all inputs and outputs
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cout << "I/O:" << endl;
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getline(file, line);
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while(regex_search(line.c_str(), m, regex("[x|y]\\d+"))) {
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cout << m.str(0) << " ";
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line = m.suffix().str();
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}
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cout << endl;
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// skip detailed I/O
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getline(file, line);
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getline(file, line);
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int maxvar = 0;
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// all wires
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cout << "wires: " << endl;
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getline(file, line);
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while(regex_search(line.c_str(), m, regex("n\\d+"))) {
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string wire = m.str(0);
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cout << wire << " ";
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maxvar = max(maxvar, std::atoi(wire.substr(1).c_str()));
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line = m.suffix().str();
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}
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cout << endl;
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assert(maxvar);
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cout << "maxvar: " << maxvar << endl;
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// allcate for global gates table
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Gates = new Gate[maxvar + 1];
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while(true) {
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getline(file, line);
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if(line == "endmodule") break;
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cout << line << endl;
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std::vector<int> vars;
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string copy = line;
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while(regex_search(copy.c_str(), m, regex("~?[xyn]\\d+"))) {
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string str = m.str(0);
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int sign = 1;
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if(str[0] == '~') {
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sign = -1;
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str = str.substr(1);
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}
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// remove x , y or n
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str = str.substr(1);
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vars.push_back(sign * atoi(str.c_str()));
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copy = m.suffix().str();
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}
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if(regex_match(line.c_str(), m, regex(" assign ~?[xyn]\\d+ = ~?[xyn]\\d+ (& ~?[xyn]\\d+)+ ;"))) {
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cout << "MATCH AND: " ;
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} else if(regex_match(line.c_str(), m, regex(" assign ~?[xyn]\\d+ = ~?[xyn]\\d+ (\\^ ~?[xyn]\\d+)+ (\\^ 1\\'b0)+ ;"))) {
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cout << "MATCH XOR: " ;
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} else if(regex_match(line.c_str(), m, regex(" assign ~?[xyn]\\d+ = ~?[xyn]\\d+ (\\| ~?[xyn]\\d+)+ ;"))) {
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cout << "MATCH OR: " ;
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} else if(regex_match(line.c_str(), m, regex(" assign ~?y\\d+ = ~?[xyn]\\d+ ;"))) {
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cout << "MATCH OUTPUT: " ;
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} else {
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cout << "MATCH MAJ: " ;
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}
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for(auto& var : vars) {
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cout << var << " ";
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}
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cout << endl;
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}
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}
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19
circuit.h
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19
circuit.h
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#pragma once
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#include "bits/stdc++.h"
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enum GateType {
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XOR, MAJ, AND, OR
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};
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struct Gate {
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std::vector<int> inputs;
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std::vector<int> output;
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std::vector<int> fanouts;
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};
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extern Gate* Gates;
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extern std::vector<int> circuit_inputs;
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extern int circuit_output;
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void read_verilog_from_file(const char *);
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259
result.txt
Normal file
259
result.txt
Normal file
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I/O:
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x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 y0
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wires:
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n15 n16 n17 n18 n19 n20 n21 n22 n23 n24 n25 n26 n27 n28 n29 n30 n31 n32 n33 n34 n35 n36 n37 n38 n39 n40 n41 n42 n43 n44 n45 n46 n47 n48 n49 n50 n51 n52 n53 n54 n55 n56 n57 n58 n59 n60 n61 n62 n63 n64 n65 n66 n67 n68 n69 n70 n71 n72 n73 n74 n75 n76 n77 n78 n79 n80 n81 n82 n83 n84 n85 n86 n87 n88 n89 n90 n91 n92 n93 n94 n95 n96 n97 n98 n99 n100 n101 n102 n103 n104 n105 n106 n107 n108 n109 n110 n111 n112 n113 n114 n115 n116 n117 n118 n119 n120 n121 n122 n123 n124 n125 n126 n127 n128 n129 n130 n131 n132 n133 n134 n135 n136 n137 n138 n139 n140
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maxvar: 140
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assign n39 = x5 & x11 ;
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MATCH AND: 39 5 11
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assign n38 = x1 & x6 ;
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MATCH AND: 38 1 6
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assign n40 = n39 ^ n38 ^ 1'b0 ;
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MATCH XOR: 40 39 38
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assign n60 = x11 & x13 ;
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MATCH AND: 60 11 13
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assign n61 = n38 & n60 ;
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MATCH AND: 61 38 60
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assign n68 = x0 & x10 ;
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MATCH AND: 68 0 10
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assign n59 = x9 & x13 ;
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MATCH AND: 59 9 13
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assign n121 = n68 ^ n59 ^ 1'b0 ;
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MATCH XOR: 121 68 59
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assign n69 = x3 & x4 ;
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MATCH AND: 69 3 4
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assign n122 = n121 ^ n69 ^ 1'b0 ;
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MATCH XOR: 122 121 69
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assign n123 = ( n40 & n61 ) | ( n40 & n122 ) | ( n61 & n122 ) ;
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MATCH MAJ: 123 40 61 40 122 61 122
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assign n35 = x6 & x11 ;
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MATCH AND: 35 6 11
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assign n36 = x1 & x5 ;
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MATCH AND: 36 1 5
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assign n37 = n35 & n36 ;
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MATCH AND: 37 35 36
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assign n19 = x5 & x6 ;
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MATCH AND: 19 5 6
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assign n18 = x8 & x11 ;
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MATCH AND: 18 8 11
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assign n21 = n19 ^ n18 ^ 1'b0 ;
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MATCH XOR: 21 19 18
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assign n108 = n37 ^ n21 ^ 1'b0 ;
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MATCH XOR: 108 37 21
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assign n44 = x0 & x3 ;
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MATCH AND: 44 0 3
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assign n109 = n108 ^ n44 ^ 1'b0 ;
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MATCH XOR: 109 108 44
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assign n45 = x2 & x10 ;
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MATCH AND: 45 2 10
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assign n34 = x1 & x9 ;
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MATCH AND: 34 1 9
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assign n106 = n45 ^ n34 ^ 1'b0 ;
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MATCH XOR: 106 45 34
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assign n46 = x4 & x13 ;
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MATCH AND: 46 4 13
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assign n107 = n106 ^ n46 ^ 1'b0 ;
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MATCH XOR: 107 106 46
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assign n124 = n109 ^ n107 ^ 1'b0 ;
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MATCH XOR: 124 109 107
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assign n105 = ( n59 & n68 ) | ( n59 & n69 ) | ( n68 & n69 ) ;
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MATCH MAJ: 105 59 68 59 69 68 69
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assign n125 = n124 ^ n105 ^ 1'b0 ;
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MATCH XOR: 125 124 105
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assign n73 = x4 & x10 ;
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MATCH AND: 73 4 10
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assign n82 = x3 & x9 ;
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MATCH AND: 82 3 9
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assign n84 = x3 & x6 ;
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MATCH AND: 84 3 6
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assign n126 = x9 & x10 ;
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MATCH AND: 126 9 10
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assign n127 = n84 & n126 ;
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MATCH AND: 127 84 126
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assign n128 = ( n73 & n82 ) | ( n73 & n127 ) | ( n82 & n127 ) ;
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MATCH MAJ: 128 73 82 73 127 82 127
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assign n129 = n122 ^ n61 ^ 1'b0 ;
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MATCH XOR: 129 122 61
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assign n130 = n129 ^ n40 ^ 1'b0 ;
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MATCH XOR: 130 129 40
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assign n63 = x6 & x13 ;
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MATCH AND: 63 6 13
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assign n62 = x1 & x11 ;
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MATCH AND: 62 1 11
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assign n64 = n63 ^ n62 ^ 1'b0 ;
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MATCH XOR: 64 63 62
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assign n94 = x10 & x11 ;
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MATCH AND: 94 10 11
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assign n95 = n84 & n94 ;
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MATCH AND: 95 84 94
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assign n132 = n126 ^ n84 ^ 1'b0 ;
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MATCH XOR: 132 126 84
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assign n133 = ( n60 & n95 ) | ( n60 & n132 ) | ( n95 & n132 ) ;
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MATCH MAJ: 133 60 95 60 132 95 132
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assign n131 = n82 ^ n73 ^ 1'b0 ;
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MATCH XOR: 131 82 73
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assign n134 = n131 ^ n127 ^ 1'b0 ;
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MATCH XOR: 134 131 127
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assign n135 = ( n64 & n133 ) | ( n64 & n134 ) | ( n133 & n134 ) ;
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MATCH MAJ: 135 64 133 64 134 133 134
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assign n136 = ( n128 & n130 ) | ( n128 & n135 ) | ( n130 & n135 ) ;
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MATCH MAJ: 136 128 130 128 135 130 135
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assign n137 = ( n123 & n125 ) | ( n123 & n136 ) | ( n125 & n136 ) ;
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MATCH MAJ: 137 123 125 123 136 125 136
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assign n119 = ( n105 & n107 ) | ( n105 & n109 ) | ( n107 & n109 ) ;
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MATCH MAJ: 119 105 107 105 109 107 109
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assign n53 = x7 & x10 ;
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MATCH AND: 53 7 10
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assign n25 = x5 & x9 ;
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MATCH AND: 25 5 9
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assign n113 = n53 ^ n25 ^ 1'b0 ;
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MATCH XOR: 113 53 25
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assign n111 = ( n34 & n45 ) | ( n34 & n46 ) | ( n45 & n46 ) ;
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MATCH MAJ: 111 34 45 34 46 45 46
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assign n16 = x6 & x8 ;
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MATCH AND: 16 6 8
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assign n15 = x11 & x12 ;
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MATCH AND: 15 11 12
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assign n17 = n16 ^ n15 ^ 1'b0 ;
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MATCH XOR: 17 16 15
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assign n112 = n111 ^ n17 ^ 1'b0 ;
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MATCH XOR: 112 111 17
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assign n114 = n113 ^ n112 ^ 1'b0 ;
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MATCH XOR: 114 113 112
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assign n31 = x2 & x3 ;
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MATCH AND: 31 2 3
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assign n115 = n114 ^ n31 ^ 1'b0 ;
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MATCH XOR: 115 114 31
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assign n20 = n18 & n19 ;
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MATCH AND: 20 18 19
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assign n117 = n115 ^ n20 ^ 1'b0 ;
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MATCH XOR: 117 115 20
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assign n110 = ( n21 & n37 ) | ( n21 & n44 ) | ( n37 & n44 ) ;
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MATCH MAJ: 110 21 37 21 44 37 44
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assign n29 = x1 & x4 ;
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MATCH AND: 29 1 4
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assign n28 = x0 & x13 ;
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MATCH AND: 28 0 13
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assign n30 = n29 ^ n28 ^ 1'b0 ;
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MATCH XOR: 30 29 28
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assign n116 = n110 ^ n30 ^ 1'b0 ;
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MATCH XOR: 116 110 30
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assign n118 = n117 ^ n116 ^ 1'b0 ;
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MATCH XOR: 118 117 116
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assign n120 = n119 ^ n118 ^ 1'b0 ;
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MATCH XOR: 120 119 118
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assign n138 = n137 ^ n120 ^ 1'b0 ;
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MATCH XOR: 138 137 120
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assign n83 = n82 ^ n64 ^ 1'b0 ;
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MATCH XOR: 83 82 64
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assign n85 = n60 & n84 ;
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MATCH AND: 85 60 84
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assign n87 = x10 | n85 ;
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MATCH OR: 87 10 85
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assign n86 = n84 ^ n60 ^ 1'b0 ;
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MATCH XOR: 86 84 60
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assign n88 = ( x9 & ~x10 ) | ( x9 & n86 ) | ( ~x10 & n86 ) ;
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MATCH MAJ: 88 9 -10 9 86 -10 86
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assign n89 = ( n85 & n87 ) | ( n85 & n88 ) | ( n87 & n88 ) ;
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MATCH MAJ: 89 85 87 85 88 87 88
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assign n90 = ( n73 & n83 ) | ( n73 & n89 ) | ( n83 & n89 ) ;
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MATCH MAJ: 90 73 83 73 89 83 89
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assign n70 = n69 ^ n68 ^ 1'b0 ;
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MATCH XOR: 70 69 68
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assign n80 = n70 ^ n59 ^ 1'b0 ;
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MATCH XOR: 80 70 59
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assign n65 = x9 | n61 ;
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MATCH OR: 65 9 61
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assign n66 = ( x3 & ~x9 ) | ( x3 & n64 ) | ( ~x9 & n64 ) ;
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MATCH MAJ: 66 3 -9 3 64 -9 64
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assign n67 = ( n61 & n65 ) | ( n61 & n66 ) | ( n65 & n66 ) ;
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MATCH MAJ: 67 61 65 61 66 65 66
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assign n79 = n67 ^ n40 ^ 1'b0 ;
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MATCH XOR: 79 67 40
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assign n81 = n80 ^ n79 ^ 1'b0 ;
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MATCH XOR: 81 80 79
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assign n102 = n90 ^ n81 ^ 1'b0 ;
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MATCH XOR: 102 90 81
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assign n74 = n44 & n73 ;
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MATCH AND: 74 44 73
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assign n71 = n59 ^ n40 ^ 1'b0 ;
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MATCH XOR: 71 59 40
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assign n72 = ( n67 & n70 ) | ( n67 & n71 ) | ( n70 & n71 ) ;
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MATCH MAJ: 72 67 70 67 71 70 71
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assign n77 = n74 ^ n72 ^ 1'b0 ;
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MATCH XOR: 77 74 72
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assign n47 = n45 ^ n44 ^ 1'b0 ;
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MATCH XOR: 47 45 44
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assign n48 = n47 ^ n46 ^ 1'b0 ;
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MATCH XOR: 48 47 46
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assign n57 = n48 ^ n34 ^ 1'b0 ;
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MATCH XOR: 57 48 34
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assign n41 = x13 | n37 ;
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MATCH OR: 41 13 37
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assign n42 = ( x9 & ~x13 ) | ( x9 & n40 ) | ( ~x13 & n40 ) ;
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MATCH MAJ: 42 9 -13 9 40 -13 40
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assign n43 = ( n37 & n41 ) | ( n37 & n42 ) | ( n41 & n42 ) ;
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MATCH MAJ: 43 37 41 37 42 41 42
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assign n56 = n43 ^ n21 ^ 1'b0 ;
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MATCH XOR: 56 43 21
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assign n58 = n57 ^ n56 ^ 1'b0 ;
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MATCH XOR: 58 57 56
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assign n78 = n77 ^ n58 ^ 1'b0 ;
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MATCH XOR: 78 77 58
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assign n96 = ( x9 & x10 ) | ( x9 & ~n95 ) | ( x10 & ~n95 ) ;
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MATCH MAJ: 96 9 10 9 -95 10 -95
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assign n97 = n96 ^ n86 ^ 1'b0 ;
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MATCH XOR: 97 96 86
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assign n98 = n95 & n97 ;
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MATCH AND: 98 95 97
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assign n99 = n89 ^ n73 ^ 1'b0 ;
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MATCH XOR: 99 89 73
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assign n100 = n99 ^ n83 ^ 1'b0 ;
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MATCH XOR: 100 99 83
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assign n101 = n98 & n100 ;
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MATCH AND: 101 98 100
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assign n103 = n78 & n101 ;
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MATCH AND: 103 78 101
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assign n104 = n102 & n103 ;
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MATCH AND: 104 102 103
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assign n139 = n138 ^ n104 ^ 1'b0 ;
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MATCH XOR: 139 138 104
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assign n91 = ( ~n78 & n81 ) | ( ~n78 & n90 ) | ( n81 & n90 ) ;
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MATCH MAJ: 91 -78 81 -78 90 81 90
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assign n92 = n78 & n91 ;
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MATCH AND: 92 78 91
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assign n75 = ( n58 & n72 ) | ( n58 & n74 ) | ( n72 & n74 ) ;
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MATCH MAJ: 75 58 72 58 74 72 74
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assign n52 = ( n44 & n45 ) | ( n44 & n46 ) | ( n45 & n46 ) ;
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MATCH MAJ: 52 44 45 44 46 45 46
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assign n49 = n34 ^ n21 ^ 1'b0 ;
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MATCH XOR: 49 34 21
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assign n50 = ( n43 & n48 ) | ( n43 & n49 ) | ( n48 & n49 ) ;
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MATCH MAJ: 50 43 48 43 49 48 49
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assign n22 = x9 | n20 ;
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MATCH OR: 22 9 20
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assign n23 = ( x1 & ~x9 ) | ( x1 & n21 ) | ( ~x9 & n21 ) ;
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MATCH MAJ: 23 1 -9 1 21 -9 21
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assign n24 = ( n20 & n22 ) | ( n20 & n23 ) | ( n22 & n23 ) ;
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MATCH MAJ: 24 20 22 20 23 22 23
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assign n26 = n24 ^ n17 ^ 1'b0 ;
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MATCH XOR: 26 24 17
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assign n27 = n26 ^ n25 ^ 1'b0 ;
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MATCH XOR: 27 26 25
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assign n32 = n30 ^ n27 ^ 1'b0 ;
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MATCH XOR: 32 30 27
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assign n33 = n32 ^ n31 ^ 1'b0 ;
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MATCH XOR: 33 32 31
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assign n51 = n50 ^ n33 ^ 1'b0 ;
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MATCH XOR: 51 50 33
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assign n54 = n52 ^ n51 ^ 1'b0 ;
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MATCH XOR: 54 52 51
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assign n55 = n54 ^ n53 ^ 1'b0 ;
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MATCH XOR: 55 54 53
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assign n76 = n75 ^ n55 ^ 1'b0 ;
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MATCH XOR: 76 75 55
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assign n93 = n92 ^ n76 ^ 1'b0 ;
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MATCH XOR: 93 92 76
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assign n140 = n139 ^ n93 ^ 1'b0 ;
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MATCH XOR: 140 139 93
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assign y0 = n140 ;
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MATCH OUTPUT: 0 140
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132
test.v
Normal file
132
test.v
Normal file
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module top( x0 , x1 , x2 , x3 , x4 , x5 , x6 , x7 , x8 , x9 , x10 , x11 , x12 , x13 , y0 );
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input x0 , x1 , x2 , x3 , x4 , x5 , x6 , x7 , x8 , x9 , x10 , x11 , x12 , x13 ;
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output y0 ;
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wire n15 , n16 , n17 , n18 , n19 , n20 , n21 , n22 , n23 , n24 , n25 , n26 , n27 , n28 , n29 , n30 , n31 , n32 , n33 , n34 , n35 , n36 , n37 , n38 , n39 , n40 , n41 , n42 , n43 , n44 , n45 , n46 , n47 , n48 , n49 , n50 , n51 , n52 , n53 , n54 , n55 , n56 , n57 , n58 , n59 , n60 , n61 , n62 , n63 , n64 , n65 , n66 , n67 , n68 , n69 , n70 , n71 , n72 , n73 , n74 , n75 , n76 , n77 , n78 , n79 , n80 , n81 , n82 , n83 , n84 , n85 , n86 , n87 , n88 , n89 , n90 , n91 , n92 , n93 , n94 , n95 , n96 , n97 , n98 , n99 , n100 , n101 , n102 , n103 , n104 , n105 , n106 , n107 , n108 , n109 , n110 , n111 , n112 , n113 , n114 , n115 , n116 , n117 , n118 , n119 , n120 , n121 , n122 , n123 , n124 , n125 , n126 , n127 , n128 , n129 , n130 , n131 , n132 , n133 , n134 , n135 , n136 , n137 , n138 , n139 , n140 ;
|
||||
assign n39 = x5 & x11 ;
|
||||
assign n38 = x1 & x6 ;
|
||||
assign n40 = n39 ^ n38 ^ 1'b0 ;
|
||||
assign n60 = x11 & x13 ;
|
||||
assign n61 = n38 & n60 ;
|
||||
assign n68 = x0 & x10 ;
|
||||
assign n59 = x9 & x13 ;
|
||||
assign n121 = n68 ^ n59 ^ 1'b0 ;
|
||||
assign n69 = x3 & x4 ;
|
||||
assign n122 = n121 ^ n69 ^ 1'b0 ;
|
||||
assign n123 = ( n40 & n61 ) | ( n40 & n122 ) | ( n61 & n122 ) ;
|
||||
assign n35 = x6 & x11 ;
|
||||
assign n36 = x1 & x5 ;
|
||||
assign n37 = n35 & n36 ;
|
||||
assign n19 = x5 & x6 ;
|
||||
assign n18 = x8 & x11 ;
|
||||
assign n21 = n19 ^ n18 ^ 1'b0 ;
|
||||
assign n108 = n37 ^ n21 ^ 1'b0 ;
|
||||
assign n44 = x0 & x3 ;
|
||||
assign n109 = n108 ^ n44 ^ 1'b0 ;
|
||||
assign n45 = x2 & x10 ;
|
||||
assign n34 = x1 & x9 ;
|
||||
assign n106 = n45 ^ n34 ^ 1'b0 ;
|
||||
assign n46 = x4 & x13 ;
|
||||
assign n107 = n106 ^ n46 ^ 1'b0 ;
|
||||
assign n124 = n109 ^ n107 ^ 1'b0 ;
|
||||
assign n105 = ( n59 & n68 ) | ( n59 & n69 ) | ( n68 & n69 ) ;
|
||||
assign n125 = n124 ^ n105 ^ 1'b0 ;
|
||||
assign n73 = x4 & x10 ;
|
||||
assign n82 = x3 & x9 ;
|
||||
assign n84 = x3 & x6 ;
|
||||
assign n126 = x9 & x10 ;
|
||||
assign n127 = n84 & n126 ;
|
||||
assign n128 = ( n73 & n82 ) | ( n73 & n127 ) | ( n82 & n127 ) ;
|
||||
assign n129 = n122 ^ n61 ^ 1'b0 ;
|
||||
assign n130 = n129 ^ n40 ^ 1'b0 ;
|
||||
assign n63 = x6 & x13 ;
|
||||
assign n62 = x1 & x11 ;
|
||||
assign n64 = n63 ^ n62 ^ 1'b0 ;
|
||||
assign n94 = x10 & x11 ;
|
||||
assign n95 = n84 & n94 ;
|
||||
assign n132 = n126 ^ n84 ^ 1'b0 ;
|
||||
assign n133 = ( n60 & n95 ) | ( n60 & n132 ) | ( n95 & n132 ) ;
|
||||
assign n131 = n82 ^ n73 ^ 1'b0 ;
|
||||
assign n134 = n131 ^ n127 ^ 1'b0 ;
|
||||
assign n135 = ( n64 & n133 ) | ( n64 & n134 ) | ( n133 & n134 ) ;
|
||||
assign n136 = ( n128 & n130 ) | ( n128 & n135 ) | ( n130 & n135 ) ;
|
||||
assign n137 = ( n123 & n125 ) | ( n123 & n136 ) | ( n125 & n136 ) ;
|
||||
assign n119 = ( n105 & n107 ) | ( n105 & n109 ) | ( n107 & n109 ) ;
|
||||
assign n53 = x7 & x10 ;
|
||||
assign n25 = x5 & x9 ;
|
||||
assign n113 = n53 ^ n25 ^ 1'b0 ;
|
||||
assign n111 = ( n34 & n45 ) | ( n34 & n46 ) | ( n45 & n46 ) ;
|
||||
assign n16 = x6 & x8 ;
|
||||
assign n15 = x11 & x12 ;
|
||||
assign n17 = n16 ^ n15 ^ 1'b0 ;
|
||||
assign n112 = n111 ^ n17 ^ 1'b0 ;
|
||||
assign n114 = n113 ^ n112 ^ 1'b0 ;
|
||||
assign n31 = x2 & x3 ;
|
||||
assign n115 = n114 ^ n31 ^ 1'b0 ;
|
||||
assign n20 = n18 & n19 ;
|
||||
assign n117 = n115 ^ n20 ^ 1'b0 ;
|
||||
assign n110 = ( n21 & n37 ) | ( n21 & n44 ) | ( n37 & n44 ) ;
|
||||
assign n29 = x1 & x4 ;
|
||||
assign n28 = x0 & x13 ;
|
||||
assign n30 = n29 ^ n28 ^ 1'b0 ;
|
||||
assign n116 = n110 ^ n30 ^ 1'b0 ;
|
||||
assign n118 = n117 ^ n116 ^ 1'b0 ;
|
||||
assign n120 = n119 ^ n118 ^ 1'b0 ;
|
||||
assign n138 = n137 ^ n120 ^ 1'b0 ;
|
||||
assign n83 = n82 ^ n64 ^ 1'b0 ;
|
||||
assign n85 = n60 & n84 ;
|
||||
assign n87 = x10 | n85 ;
|
||||
assign n86 = n84 ^ n60 ^ 1'b0 ;
|
||||
assign n88 = ( x9 & ~x10 ) | ( x9 & n86 ) | ( ~x10 & n86 ) ;
|
||||
assign n89 = ( n85 & n87 ) | ( n85 & n88 ) | ( n87 & n88 ) ;
|
||||
assign n90 = ( n73 & n83 ) | ( n73 & n89 ) | ( n83 & n89 ) ;
|
||||
assign n70 = n69 ^ n68 ^ 1'b0 ;
|
||||
assign n80 = n70 ^ n59 ^ 1'b0 ;
|
||||
assign n65 = x9 | n61 ;
|
||||
assign n66 = ( x3 & ~x9 ) | ( x3 & n64 ) | ( ~x9 & n64 ) ;
|
||||
assign n67 = ( n61 & n65 ) | ( n61 & n66 ) | ( n65 & n66 ) ;
|
||||
assign n79 = n67 ^ n40 ^ 1'b0 ;
|
||||
assign n81 = n80 ^ n79 ^ 1'b0 ;
|
||||
assign n102 = n90 ^ n81 ^ 1'b0 ;
|
||||
assign n74 = n44 & n73 ;
|
||||
assign n71 = n59 ^ n40 ^ 1'b0 ;
|
||||
assign n72 = ( n67 & n70 ) | ( n67 & n71 ) | ( n70 & n71 ) ;
|
||||
assign n77 = n74 ^ n72 ^ 1'b0 ;
|
||||
assign n47 = n45 ^ n44 ^ 1'b0 ;
|
||||
assign n48 = n47 ^ n46 ^ 1'b0 ;
|
||||
assign n57 = n48 ^ n34 ^ 1'b0 ;
|
||||
assign n41 = x13 | n37 ;
|
||||
assign n42 = ( x9 & ~x13 ) | ( x9 & n40 ) | ( ~x13 & n40 ) ;
|
||||
assign n43 = ( n37 & n41 ) | ( n37 & n42 ) | ( n41 & n42 ) ;
|
||||
assign n56 = n43 ^ n21 ^ 1'b0 ;
|
||||
assign n58 = n57 ^ n56 ^ 1'b0 ;
|
||||
assign n78 = n77 ^ n58 ^ 1'b0 ;
|
||||
assign n96 = ( x9 & x10 ) | ( x9 & ~n95 ) | ( x10 & ~n95 ) ;
|
||||
assign n97 = n96 ^ n86 ^ 1'b0 ;
|
||||
assign n98 = n95 & n97 ;
|
||||
assign n99 = n89 ^ n73 ^ 1'b0 ;
|
||||
assign n100 = n99 ^ n83 ^ 1'b0 ;
|
||||
assign n101 = n98 & n100 ;
|
||||
assign n103 = n78 & n101 ;
|
||||
assign n104 = n102 & n103 ;
|
||||
assign n139 = n138 ^ n104 ^ 1'b0 ;
|
||||
assign n91 = ( ~n78 & n81 ) | ( ~n78 & n90 ) | ( n81 & n90 ) ;
|
||||
assign n92 = n78 & n91 ;
|
||||
assign n75 = ( n58 & n72 ) | ( n58 & n74 ) | ( n72 & n74 ) ;
|
||||
assign n52 = ( n44 & n45 ) | ( n44 & n46 ) | ( n45 & n46 ) ;
|
||||
assign n49 = n34 ^ n21 ^ 1'b0 ;
|
||||
assign n50 = ( n43 & n48 ) | ( n43 & n49 ) | ( n48 & n49 ) ;
|
||||
assign n22 = x9 | n20 ;
|
||||
assign n23 = ( x1 & ~x9 ) | ( x1 & n21 ) | ( ~x9 & n21 ) ;
|
||||
assign n24 = ( n20 & n22 ) | ( n20 & n23 ) | ( n22 & n23 ) ;
|
||||
assign n26 = n24 ^ n17 ^ 1'b0 ;
|
||||
assign n27 = n26 ^ n25 ^ 1'b0 ;
|
||||
assign n32 = n30 ^ n27 ^ 1'b0 ;
|
||||
assign n33 = n32 ^ n31 ^ 1'b0 ;
|
||||
assign n51 = n50 ^ n33 ^ 1'b0 ;
|
||||
assign n54 = n52 ^ n51 ^ 1'b0 ;
|
||||
assign n55 = n54 ^ n53 ^ 1'b0 ;
|
||||
assign n76 = n75 ^ n55 ^ 1'b0 ;
|
||||
assign n93 = n92 ^ n76 ^ 1'b0 ;
|
||||
assign n140 = n139 ^ n93 ^ 1'b0 ;
|
||||
assign y0 = n140 ;
|
||||
endmodule
|
||||
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Reference in New Issue
Block a user