YuhangQ/any2bench
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YuhangQ 045ca1e143 init commit
2023-01-04 21:52:32 +08:00
Mylib.lib
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README.md
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test.v
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verilog2bench.py
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README.md

Intro

一个工具可以把任意格式转换成只有基础门电路的 .bench 格式

要求

需要 yosys 处理 verilog 需要 abc 进行逻辑综合

这两个程序请加入到环境变量

Description
将任意格式转换成 bench 格式
Readme 111 KiB
Languages
Verilog 70.2%
Python 29.8%