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109
Mylib.lib
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109
Mylib.lib
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library(demo) {
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cell(NAND4) {
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area: 15;
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pin(A) { direction: input; }
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pin(B) { direction: input; }
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pin(C) { direction: input; }
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pin(D) { direction: input; }
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pin(Y) { direction: output; function: "(A*B*C*D)'"; } }
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cell(NAND3) {
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area: 12;
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pin(A) { direction: input; }
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pin(B) { direction: input; }
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pin(C) { direction: input; }
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pin(Y) { direction: output; function: "(A*B*C)'"; } }
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cell(NAND2) {
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area: 10;
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pin(A) { direction: input; }
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pin(B) { direction: input; }
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pin(Y) { direction: output; function: "(A*B)'"; } }
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cell(AND4) {
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area: 20;
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pin(A) { direction: input; }
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pin(B) { direction: input; }
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pin(C) { direction: input; }
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pin(D) { direction: input; }
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pin(Y) { direction: output; function: "(A*B*C*D)"; } }
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cell(AND3) {
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area: 15;
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pin(A) { direction: input; }
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pin(B) { direction: input; }
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pin(C) { direction: input; }
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pin(Y) { direction: output; function: "(A*B*C)"; } }
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cell(AND2) {
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area: 12;
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pin(A) { direction: input; }
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pin(B) { direction: input; }
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pin(Y) { direction: output; function: "(A*B)"; } }
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cell(NOR4) {
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area: 20;
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pin(A) { direction: input; }
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pin(B) { direction: input; }
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pin(C) { direction: input; }
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pin(D) { direction: input; }
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pin(Y) { direction: output; function: "(A+B+C+D)'"; } }
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cell(NOR3) {
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area: 15;
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pin(A) { direction: input; }
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pin(B) { direction: input; }
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pin(C) { direction: input; }
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pin(Y) { direction: output; function: "(A+B+C)'"; } }
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cell(NOR2) {
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area: 10;
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pin(A) { direction: input; }
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pin(B) { direction: input; }
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pin(Y) { direction: output; function: "(A+B)'"; } }
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cell(OR4) {
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area: 20;
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pin(A) { direction: input; }
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pin(B) { direction: input; }
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pin(C) { direction: input; }
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pin(D) { direction: input; }
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pin(Y) { direction: output; function: "(A+B+C+D)"; } }
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cell(OR3) {
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area: 15;
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pin(A) { direction: input; }
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pin(B) { direction: input; }
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pin(C) { direction: input; }
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pin(Y) { direction: output; function: "(A+B+C)"; } }
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cell(OR2) {
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area: 10;
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pin(A) { direction: input; }
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pin(B) { direction: input; }
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pin(Y) { direction: output; function: "(A+B)"; } }
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cell(XNOR2) {
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area: 25;
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pin(A) { direction: input; }
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pin(B) { direction: input; }
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pin(Y) { direction: output; function: "(A^B)'"; } }
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cell(XOR2) {
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area: 25;
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pin(A) { direction: input; }
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pin(B) { direction: input; }
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pin(Y) { direction: output; function: "(A^B)"; } }
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cell(BUF) {
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area: 12;
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pin(A) { direction: input; }
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pin(Y) { direction: output; function: "A"; } }
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cell(NOT) {
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area: 6;
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pin(A) { direction: input; }
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pin(Y) { direction: output; function: "A'"; } }
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}
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10
README.md
10
README.md
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## Intro
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一个工具可以把任意格式转换成只有基础门电路的 .bench 格式
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## 要求
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需要 yosys 处理 verilog
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需要 abc 进行逻辑综合
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这两个程序请加入到环境变量
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56
test.v
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56
test.v
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// Benchmark "test" written by ABC on Wed Jan 4 21:10:42 2023
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module test (
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NET_1, NET_2, NET_3, NET_4, NET_5, NET_6, NET_7,
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NET_112, NET_41, NET_42, NET_45, NET_46, NET_8, NET_9 );
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input NET_1, NET_2, NET_3, NET_4, NET_5, NET_6, NET_7;
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output NET_112, NET_41, NET_42, NET_45, NET_46, NET_8, NET_9;
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wire new_n15_, new_n17_, new_n18_, new_n19_, new_n20_, new_n21_, new_n22_,
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new_n23_, new_n24_, new_n25_, new_n26_, new_n27_, new_n28_, new_n29_,
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new_n30_, new_n32_, new_n33_, new_n34_, new_n35_, new_n36_, new_n38_,
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new_n39_, new_n40_, new_n41_, new_n42_, new_n43_, new_n44_, new_n46_,
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new_n47_, new_n48_, new_n49_, new_n50_, new_n51_, new_n52_;
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NOT g00(.A(NET_3), .Y(new_n15_));
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AND3 g01(.A(NET_5), .B(NET_4), .C(new_n15_), .Y(NET_112));
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NAND2 g02(.A(NET_2), .B(NET_1), .Y(new_n17_));
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OR2 g03(.A(NET_2), .B(NET_1), .Y(new_n18_));
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AND2 g04(.A(new_n18_), .B(new_n17_), .Y(new_n19_));
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NOT g05(.A(NET_1), .Y(new_n20_));
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NOT g06(.A(NET_2), .Y(new_n21_));
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NOR2 g07(.A(new_n21_), .B(new_n20_), .Y(new_n22_));
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NOR2 g08(.A(new_n22_), .B(NET_4), .Y(new_n23_));
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NAND3 g09(.A(new_n23_), .B(new_n19_), .C(NET_3), .Y(new_n24_));
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NAND3 g10(.A(new_n23_), .B(NET_5), .C(NET_3), .Y(new_n25_));
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NAND2 g11(.A(NET_4), .B(NET_3), .Y(new_n26_));
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NAND2 g12(.A(new_n26_), .B(new_n22_), .Y(new_n27_));
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NOT g13(.A(NET_4), .Y(new_n28_));
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NOR2 g14(.A(NET_5), .B(new_n28_), .Y(new_n29_));
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NAND2 g15(.A(new_n29_), .B(new_n15_), .Y(new_n30_));
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NAND4 g16(.A(new_n30_), .B(new_n27_), .C(new_n25_), .D(new_n24_), .Y(NET_41));
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NAND2 g17(.A(new_n18_), .B(new_n17_), .Y(new_n32_));
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NAND3 g18(.A(new_n32_), .B(new_n28_), .C(NET_3), .Y(new_n33_));
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NOR2 g19(.A(new_n29_), .B(new_n15_), .Y(new_n34_));
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OR2 g20(.A(new_n34_), .B(new_n32_), .Y(new_n35_));
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NAND3 g21(.A(new_n32_), .B(NET_5), .C(NET_3), .Y(new_n36_));
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NAND3 g22(.A(new_n36_), .B(new_n35_), .C(new_n33_), .Y(NET_42));
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NAND3 g23(.A(new_n19_), .B(NET_5), .C(NET_3), .Y(new_n38_));
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NAND2 g24(.A(new_n29_), .B(new_n22_), .Y(new_n39_));
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AND2 g25(.A(new_n39_), .B(new_n38_), .Y(new_n40_));
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OR2 g26(.A(new_n33_), .B(new_n22_), .Y(new_n41_));
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NAND3 g27(.A(new_n17_), .B(NET_5), .C(new_n28_), .Y(new_n42_));
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NAND3 g28(.A(new_n22_), .B(NET_5), .C(NET_3), .Y(new_n43_));
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AND3 g29(.A(new_n43_), .B(new_n42_), .C(new_n30_), .Y(new_n44_));
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NAND3 g30(.A(new_n44_), .B(new_n41_), .C(new_n40_), .Y(NET_45));
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NOT g31(.A(NET_5), .Y(new_n46_));
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NOR2 g32(.A(new_n46_), .B(NET_4), .Y(new_n47_));
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NOR2 g33(.A(new_n47_), .B(NET_3), .Y(new_n48_));
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OR2 g34(.A(new_n48_), .B(new_n17_), .Y(new_n49_));
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NAND4 g35(.A(new_n17_), .B(new_n46_), .C(new_n28_), .D(new_n15_), .Y(new_n50_));
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NAND2 g36(.A(new_n17_), .B(NET_112), .Y(new_n51_));
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AND2 g37(.A(new_n51_), .B(new_n50_), .Y(new_n52_));
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NAND4 g38(.A(new_n52_), .B(new_n49_), .C(new_n40_), .D(new_n24_), .Y(NET_46));
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BUF g39(.A(NET_6), .Y(NET_8));
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BUF g40(.A(NET_7), .Y(NET_9));
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endmodule
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64
verilog2bench.py
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64
verilog2bench.py
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import os
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import sys
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import re
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if len(sys.argv) == 1:
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print("usage: python verilog2bench.py <VERILOG>")
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exit(0)
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lines = open(sys.argv[1], "r").read().split(";")
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gates = ["AND2", "AND3", "AND4",
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"NAND2", "NAND3", "NAND4",
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"OR2", "OR3", "OR4",
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"NOR2", "NOR3", "NOR4",
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"XOR2", "XOR3", "XOR4",
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"NXOR2", "NXOR3", "NXOR4",
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"BUF", "NOT"]
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for line in lines:
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line = line.strip()
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if(line.startswith("//")): continue
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if(line.startswith("input")):
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for input in line[5:].split(","):
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print("INPUT(%s)" % input.strip())
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continue
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if(line.startswith("output")):
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for input in line[6:].split(","):
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print("OUTPUT(%s)" % input.strip())
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continue
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if(line.strip().startswith("wire")): continue
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if(line.strip().startswith("endmodule")):
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#print("reach endmodule!")
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break
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gate = line.strip().split(" ")[0]
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# print(gate)
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if gate not in gates:
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print("ERROR: %s is not valid gate!" % gate)
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exit(-1)
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# print(line)
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p1 = re.compile(r'\.\w+[(](.*?)[)]', re.S)
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wires = p1.findall(line)
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print(wires[0] + " = ( " + wires[1], end="")
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for i in range(2, len(wires)):
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print(", " + wires[i], end="")
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print(" )")
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