// Benchmark "test" written by ABC on Wed Jan  4 21:10:42 2023

module test ( 
    NET_1, NET_2, NET_3, NET_4, NET_5, NET_6, NET_7,
    NET_112, NET_41, NET_42, NET_45, NET_46, NET_8, NET_9  );
  input  NET_1, NET_2, NET_3, NET_4, NET_5, NET_6, NET_7;
  output NET_112, NET_41, NET_42, NET_45, NET_46, NET_8, NET_9;
  wire new_n15_, new_n17_, new_n18_, new_n19_, new_n20_, new_n21_, new_n22_,
    new_n23_, new_n24_, new_n25_, new_n26_, new_n27_, new_n28_, new_n29_,
    new_n30_, new_n32_, new_n33_, new_n34_, new_n35_, new_n36_, new_n38_,
    new_n39_, new_n40_, new_n41_, new_n42_, new_n43_, new_n44_, new_n46_,
    new_n47_, new_n48_, new_n49_, new_n50_, new_n51_, new_n52_;
  NOT      g00(.A(NET_3), .Y(new_n15_));
  AND3     g01(.A(NET_5), .B(NET_4), .C(new_n15_), .Y(NET_112));
  NAND2    g02(.A(NET_2), .B(NET_1), .Y(new_n17_));
  OR2      g03(.A(NET_2), .B(NET_1), .Y(new_n18_));
  AND2     g04(.A(new_n18_), .B(new_n17_), .Y(new_n19_));
  NOT      g05(.A(NET_1), .Y(new_n20_));
  NOT      g06(.A(NET_2), .Y(new_n21_));
  NOR2     g07(.A(new_n21_), .B(new_n20_), .Y(new_n22_));
  NOR2     g08(.A(new_n22_), .B(NET_4), .Y(new_n23_));
  NAND3    g09(.A(new_n23_), .B(new_n19_), .C(NET_3), .Y(new_n24_));
  NAND3    g10(.A(new_n23_), .B(NET_5), .C(NET_3), .Y(new_n25_));
  NAND2    g11(.A(NET_4), .B(NET_3), .Y(new_n26_));
  NAND2    g12(.A(new_n26_), .B(new_n22_), .Y(new_n27_));
  NOT      g13(.A(NET_4), .Y(new_n28_));
  NOR2     g14(.A(NET_5), .B(new_n28_), .Y(new_n29_));
  NAND2    g15(.A(new_n29_), .B(new_n15_), .Y(new_n30_));
  NAND4    g16(.A(new_n30_), .B(new_n27_), .C(new_n25_), .D(new_n24_), .Y(NET_41));
  NAND2    g17(.A(new_n18_), .B(new_n17_), .Y(new_n32_));
  NAND3    g18(.A(new_n32_), .B(new_n28_), .C(NET_3), .Y(new_n33_));
  NOR2     g19(.A(new_n29_), .B(new_n15_), .Y(new_n34_));
  OR2      g20(.A(new_n34_), .B(new_n32_), .Y(new_n35_));
  NAND3    g21(.A(new_n32_), .B(NET_5), .C(NET_3), .Y(new_n36_));
  NAND3    g22(.A(new_n36_), .B(new_n35_), .C(new_n33_), .Y(NET_42));
  NAND3    g23(.A(new_n19_), .B(NET_5), .C(NET_3), .Y(new_n38_));
  NAND2    g24(.A(new_n29_), .B(new_n22_), .Y(new_n39_));
  AND2     g25(.A(new_n39_), .B(new_n38_), .Y(new_n40_));
  OR2      g26(.A(new_n33_), .B(new_n22_), .Y(new_n41_));
  NAND3    g27(.A(new_n17_), .B(NET_5), .C(new_n28_), .Y(new_n42_));
  NAND3    g28(.A(new_n22_), .B(NET_5), .C(NET_3), .Y(new_n43_));
  AND3     g29(.A(new_n43_), .B(new_n42_), .C(new_n30_), .Y(new_n44_));
  NAND3    g30(.A(new_n44_), .B(new_n41_), .C(new_n40_), .Y(NET_45));
  NOT      g31(.A(NET_5), .Y(new_n46_));
  NOR2     g32(.A(new_n46_), .B(NET_4), .Y(new_n47_));
  NOR2     g33(.A(new_n47_), .B(NET_3), .Y(new_n48_));
  OR2      g34(.A(new_n48_), .B(new_n17_), .Y(new_n49_));
  NAND4    g35(.A(new_n17_), .B(new_n46_), .C(new_n28_), .D(new_n15_), .Y(new_n50_));
  NAND2    g36(.A(new_n17_), .B(NET_112), .Y(new_n51_));
  AND2     g37(.A(new_n51_), .B(new_n50_), .Y(new_n52_));
  NAND4    g38(.A(new_n52_), .B(new_n49_), .C(new_n40_), .D(new_n24_), .Y(NET_46));
  BUF      g39(.A(NET_6), .Y(NET_8));
  BUF      g40(.A(NET_7), .Y(NET_9));
endmodule