import os
import sys
import re

if len(sys.argv) == 1:
    print("usage: python verilog2bench.py <VERILOG>")
    exit(0)

lines = open(sys.argv[1], "r").read().split(";")

gates = ["AND2", "AND3", "AND4",
         "NAND2", "NAND3", "NAND4",
         "OR2", "OR3", "OR4",
         "NOR2", "NOR3", "NOR4",
         "XOR2", "XOR3", "XOR4",
         "NXOR2", "NXOR3", "NXOR4",
         "BUF", "NOT"]


for line in lines:
    line = line.strip()
    if(line.startswith("//")): continue
    if(line.startswith("input")):
        for input in line[5:].split(","):
            print("INPUT(%s)" % input.strip())
        continue
    if(line.startswith("output")):
        for input in line[6:].split(","):
            print("OUTPUT(%s)" % input.strip())
        continue

    if(line.strip().startswith("wire")): continue

    if(line.strip().startswith("endmodule")):
        #print("reach endmodule!")
        break

    

    gate = line.strip().split(" ")[0]
    # print(gate)

    if gate not in gates:
        print("ERROR: %s is not valid gate!" % gate)
        exit(-1)

    # print(line)

    p1 = re.compile(r'\.\w+[(](.*?)[)]', re.S)

    wires = p1.findall(line)

    print(wires[0] + " = ( " + wires[1], end="")
    for i in range(2, len(wires)):
        print(", " + wires[i], end="")
    print(" )")