65 lines
1.3 KiB
Python
65 lines
1.3 KiB
Python
import os
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import sys
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import re
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if len(sys.argv) == 1:
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print("usage: python verilog2bench.py <VERILOG>")
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exit(0)
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lines = open(sys.argv[1], "r").read().split(";")
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gates = ["AND2", "AND3", "AND4",
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"NAND2", "NAND3", "NAND4",
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"OR2", "OR3", "OR4",
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"NOR2", "NOR3", "NOR4",
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"XOR2", "XOR3", "XOR4",
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"NXOR2", "NXOR3", "NXOR4",
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"BUF", "NOT"]
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for line in lines:
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line = line.strip()
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if(line.startswith("//")): continue
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if(line.startswith("input")):
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for input in line[5:].split(","):
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print("INPUT(%s)" % input.strip())
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continue
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if(line.startswith("output")):
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for input in line[6:].split(","):
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print("OUTPUT(%s)" % input.strip())
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continue
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if(line.strip().startswith("wire")): continue
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if(line.strip().startswith("endmodule")):
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#print("reach endmodule!")
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break
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gate = line.strip().split(" ")[0]
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# print(gate)
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if gate not in gates:
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print("ERROR: %s is not valid gate!" % gate)
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exit(-1)
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# print(line)
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p1 = re.compile(r'\.\w+[(](.*?)[)]', re.S)
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wires = p1.findall(line)
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print(wires[0] + " = ( " + wires[1], end="")
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for i in range(2, len(wires)):
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print(", " + wires[i], end="")
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print(" )")
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