# generated by verilog2bench.py https://gitea.yuhangq.com/YuhangQ/any2bench

INPUT(NET_1)
INPUT(NET_2)
INPUT(NET_3)
INPUT(NET_4)
INPUT(NET_5)
INPUT(NET_6)
INPUT(NET_7)

OUTPUT(NET_112)
OUTPUT(NET_41)
OUTPUT(NET_42)
OUTPUT(NET_45)
OUTPUT(NET_46)
OUTPUT(NET_8)
OUTPUT(NET_9)

new_n15_ = NOT ( NET_3 )
NET_112 = AND ( NET_5, NET_4, new_n15_ )
new_n17_ = NAND ( NET_2, NET_1 )
new_n18_ = OR ( NET_2, NET_1 )
new_n19_ = AND ( new_n18_, new_n17_ )
new_n20_ = NOT ( NET_1 )
new_n21_ = NOT ( NET_2 )
new_n22_ = NOR ( new_n21_, new_n20_ )
new_n23_ = NOR ( new_n22_, NET_4 )
new_n24_ = NAND ( new_n23_, new_n19_, NET_3 )
new_n25_ = NAND ( new_n23_, NET_5, NET_3 )
new_n26_ = NAND ( NET_4, NET_3 )
new_n27_ = NAND ( new_n26_, new_n22_ )
new_n28_ = NOT ( NET_4 )
new_n29_ = NOR ( NET_5, new_n28_ )
new_n30_ = NAND ( new_n29_, new_n15_ )
NET_41 = NAND ( new_n30_, new_n27_, new_n25_, new_n24_ )
new_n32_ = NAND ( new_n18_, new_n17_ )
new_n33_ = NAND ( new_n32_, new_n28_, NET_3 )
new_n34_ = NOR ( new_n29_, new_n15_ )
new_n35_ = OR ( new_n34_, new_n32_ )
new_n36_ = NAND ( new_n32_, NET_5, NET_3 )
NET_42 = NAND ( new_n36_, new_n35_, new_n33_ )
new_n38_ = NAND ( new_n19_, NET_5, NET_3 )
new_n39_ = NAND ( new_n29_, new_n22_ )
new_n40_ = AND ( new_n39_, new_n38_ )
new_n41_ = OR ( new_n33_, new_n22_ )
new_n42_ = NAND ( new_n17_, NET_5, new_n28_ )
new_n43_ = NAND ( new_n22_, NET_5, NET_3 )
new_n44_ = AND ( new_n43_, new_n42_, new_n30_ )
NET_45 = NAND ( new_n44_, new_n41_, new_n40_ )
new_n46_ = NOT ( NET_5 )
new_n47_ = NOR ( new_n46_, NET_4 )
new_n48_ = NOR ( new_n47_, NET_3 )
new_n49_ = OR ( new_n48_, new_n17_ )
new_n50_ = NAND ( new_n17_, new_n46_, new_n28_, new_n15_ )
new_n51_ = NAND ( new_n17_, NET_112 )
new_n52_ = AND ( new_n51_, new_n50_ )
NET_46 = NAND ( new_n52_, new_n49_, new_n40_, new_n24_ )
NET_8 = BUF ( NET_6 )
NET_9 = BUF ( NET_7 )
