# generated by verilog2bench.py https://gitea.yuhangq.com/YuhangQ/any2bench
INPUT(NET_1)
INPUT(NET_10)
INPUT(NET_11)
INPUT(NET_2)
INPUT(NET_3)
INPUT(NET_4)
INPUT(NET_5)
INPUT(NET_6)
INPUT(NET_7)
INPUT(NET_8)
INPUT(NET_9)
OUTPUT(NET_12)
OUTPUT(NET_13)
OUTPUT(NET_135)
OUTPUT(NET_136)
OUTPUT(NET_14)
OUTPUT(NET_15)
OUTPUT(NET_16)
OUTPUT(NET_17)
OUTPUT(NET_48)
OUTPUT(NET_49)
OUTPUT(NET_50)
OUTPUT(NET_51)
OUTPUT(NET_52)
OUTPUT(NET_57)
OUTPUT(NET_60)
new_n27_ = OR ( NET_5, NET_3 )
new_n28_ = NOT ( NET_4 )
new_n29_ = OR ( new_n28_, NET_1 )
new_n30_ = OR ( new_n29_, new_n27_ )
new_n31_ = NAND ( NET_5, NET_3 )
new_n32_ = NOR ( new_n31_, new_n28_ )
new_n33_ = OR ( new_n32_, NET_2 )
NET_135 = NAND ( new_n33_, new_n30_ )
new_n35_ = NOR ( new_n28_, NET_1 )
new_n36_ = NOT ( NET_1 )
new_n37_ = NOR ( NET_4, new_n36_ )
new_n38_ = NOR ( new_n37_, new_n35_ )
new_n39_ = NAND ( NET_4, NET_1 )
new_n40_ = NAND ( new_n39_, NET_5 )
NET_48 = AND ( new_n40_, new_n38_, NET_3 )
new_n42_ = NOT ( NET_5 )
new_n43_ = NAND ( new_n42_, new_n28_, NET_3 )
new_n44_ = NOT ( NET_3 )
new_n45_ = NAND ( NET_5, new_n28_, new_n44_, new_n36_ )
new_n46_ = NAND ( NET_3, NET_1 )
NET_49 = NAND ( new_n46_, new_n45_, new_n43_ )
new_n48_ = OR ( new_n43_, NET_1 )
new_n49_ = OR ( new_n27_, new_n28_ )
new_n50_ = NAND ( NET_5, new_n44_, NET_1 )
NET_50 = NAND ( new_n50_, new_n49_, new_n48_, new_n39_ )
new_n52_ = OR ( new_n37_, new_n42_ )
new_n53_ = OR ( new_n27_, NET_4 )
NET_51 = NAND ( new_n53_, new_n52_, new_n29_ )
new_n55_ = OR ( new_n39_, NET_3 )
new_n56_ = AND ( new_n31_, new_n27_ )
NET_52 = NAND ( new_n56_, new_n55_, new_n38_ )
new_n58_ = NAND ( new_n56_, new_n28_ )
new_n59_ = OR ( new_n39_, NET_5 )
NET_57 = NAND ( new_n59_, new_n58_, new_n46_ )
new_n61_ = XOR ( new_n31_, NET_4 )
new_n62_ = OR ( new_n61_, new_n56_ )
new_n63_ = NAND ( new_n62_, new_n58_ )
NET_60 = NAND ( new_n63_, NET_1 )
NET_12 = BUF ( NET_6 )
NET_13 = BUF ( NET_7 )
NET_136 = NAND ( new_n33_, new_n30_ )
NET_14 = BUF ( NET_8 )
NET_15 = BUF ( NET_9 )
NET_16 = BUF ( NET_10 )
NET_17 = BUF ( NET_11 )
