347 lines
18 KiB
Plaintext
347 lines
18 KiB
Plaintext
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[H[2Jmake: 'atpg' is up to date.
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========================
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parsing file ./benchmark/c2670.bench ... Done.
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====== Circuit Statistics ======
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PI: 233
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PO: 140
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Gate: 1426
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Stem: 696
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Level: 12
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================================
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[SOL] flip: 0, stem: 0, fault:13379. flip_cnt: 0, stem_cnt: 696, fault_cnt:707
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coverage: 24.790% pattern: 1 before: 2852 now: 2145
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:5187. flip_cnt: 0, stem_cnt: 696, fault_cnt:536
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coverage: 34.362% pattern: 2 before: 2145 now: 1872
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:6579. flip_cnt: 0, stem_cnt: 696, fault_cnt:707
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coverage: 49.649% pattern: 3 before: 1872 now: 1436
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:2783. flip_cnt: 0, stem_cnt: 696, fault_cnt:723
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coverage: 55.049% pattern: 4 before: 1436 now: 1282
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:1520. flip_cnt: 0, stem_cnt: 696, fault_cnt:739
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coverage: 57.854% pattern: 5 before: 1282 now: 1202
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:2871. flip_cnt: 0, stem_cnt: 696, fault_cnt:635
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coverage: 63.359% pattern: 6 before: 1202 now: 1045
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:532. flip_cnt: 0, stem_cnt: 696, fault_cnt:487
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coverage: 64.341% pattern: 7 before: 1045 now: 1017
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:1444. flip_cnt: 0, stem_cnt: 696, fault_cnt:678
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coverage: 67.006% pattern: 8 before: 1017 now: 941
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:475. flip_cnt: 0, stem_cnt: 696, fault_cnt:663
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coverage: 67.882% pattern: 9 before: 941 now: 916
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:1026. flip_cnt: 0, stem_cnt: 696, fault_cnt:639
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coverage: 69.776% pattern: 10 before: 916 now: 862
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 696, fault_cnt:544
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coverage: 70.161% pattern: 11 before: 862 now: 851
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 696, fault_cnt:545
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coverage: 70.757% pattern: 12 before: 851 now: 834
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:523. flip_cnt: 0, stem_cnt: 696, fault_cnt:626
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coverage: 71.844% pattern: 13 before: 834 now: 803
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:274. flip_cnt: 0, stem_cnt: 696, fault_cnt:513
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coverage: 72.721% pattern: 14 before: 803 now: 778
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 696, fault_cnt:626
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coverage: 73.107% pattern: 15 before: 778 now: 767
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:285. flip_cnt: 0, stem_cnt: 696, fault_cnt:615
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coverage: 73.633% pattern: 16 before: 767 now: 752
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 696, fault_cnt:513
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coverage: 74.053% pattern: 17 before: 752 now: 740
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 696, fault_cnt:733
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coverage: 74.509% pattern: 18 before: 740 now: 727
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:244. flip_cnt: 0, stem_cnt: 696, fault_cnt:462
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coverage: 75.070% pattern: 19 before: 727 now: 711
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 696, fault_cnt:563
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coverage: 75.386% pattern: 20 before: 711 now: 702
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
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coverage: 75.386% pattern: 20 before: 702 now: 702
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:619
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coverage: 75.456% pattern: 21 before: 702 now: 700
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 696, fault_cnt:562
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coverage: 75.596% pattern: 22 before: 700 now: 696
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 696, fault_cnt:534
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coverage: 75.631% pattern: 23 before: 696 now: 695
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:439
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coverage: 75.631% pattern: 23 before: 695 now: 695
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 696, fault_cnt:569
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coverage: 75.842% pattern: 24 before: 695 now: 689
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 696, fault_cnt:694
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coverage: 75.982% pattern: 25 before: 689 now: 685
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
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coverage: 76.297% pattern: 26 before: 685 now: 676
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:342. flip_cnt: 0, stem_cnt: 696, fault_cnt:602
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coverage: 76.928% pattern: 27 before: 676 now: 658
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:479
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coverage: 76.928% pattern: 27 before: 658 now: 658
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:41. flip_cnt: 0, stem_cnt: 696, fault_cnt:604
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coverage: 77.034% pattern: 28 before: 658 now: 655
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 696, fault_cnt:567
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coverage: 77.174% pattern: 29 before: 655 now: 651
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:534
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coverage: 77.174% pattern: 29 before: 651 now: 651
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:646
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coverage: 77.174% pattern: 29 before: 651 now: 651
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:571
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coverage: 77.244% pattern: 30 before: 651 now: 649
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:497
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coverage: 77.244% pattern: 30 before: 649 now: 649
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 696, fault_cnt:540
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coverage: 77.840% pattern: 31 before: 649 now: 632
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:594
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coverage: 77.840% pattern: 31 before: 632 now: 632
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:479
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coverage: 77.840% pattern: 31 before: 632 now: 632
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:557
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coverage: 77.910% pattern: 32 before: 632 now: 630
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:490
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coverage: 77.910% pattern: 32 before: 630 now: 630
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:442
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coverage: 77.910% pattern: 32 before: 630 now: 630
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:494
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coverage: 77.910% pattern: 32 before: 630 now: 630
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:568
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coverage: 77.910% pattern: 32 before: 630 now: 630
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:630
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coverage: 77.910% pattern: 32 before: 630 now: 630
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:501
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coverage: 77.910% pattern: 32 before: 630 now: 630
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:476
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coverage: 77.910% pattern: 32 before: 630 now: 630
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
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coverage: 77.910% pattern: 32 before: 630 now: 630
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:399. flip_cnt: 0, stem_cnt: 696, fault_cnt:688
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coverage: 78.647% pattern: 33 before: 630 now: 609
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:624
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coverage: 78.647% pattern: 33 before: 609 now: 609
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:539
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coverage: 78.647% pattern: 33 before: 609 now: 609
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:438
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coverage: 78.647% pattern: 33 before: 609 now: 609
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 696, fault_cnt:588
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coverage: 78.857% pattern: 34 before: 609 now: 603
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:521
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coverage: 78.892% pattern: 35 before: 603 now: 602
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
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coverage: 78.962% pattern: 36 before: 602 now: 600
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:475. flip_cnt: 0, stem_cnt: 696, fault_cnt:655
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coverage: 79.839% pattern: 37 before: 600 now: 575
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:609
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coverage: 79.839% pattern: 37 before: 575 now: 575
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:583
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coverage: 79.874% pattern: 38 before: 575 now: 574
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 696, fault_cnt:756
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coverage: 80.435% pattern: 39 before: 574 now: 558
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
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coverage: 80.435% pattern: 39 before: 558 now: 558
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:771
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coverage: 80.505% pattern: 40 before: 558 now: 556
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:609
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coverage: 80.540% pattern: 41 before: 556 now: 555
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:523
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coverage: 80.540% pattern: 41 before: 555 now: 555
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:655
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coverage: 80.540% pattern: 41 before: 555 now: 555
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:629
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coverage: 80.540% pattern: 41 before: 555 now: 555
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:671
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coverage: 80.610% pattern: 42 before: 555 now: 553
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 696, fault_cnt:555
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coverage: 80.891% pattern: 43 before: 553 now: 545
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:667
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coverage: 80.891% pattern: 43 before: 545 now: 545
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:583
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coverage: 80.891% pattern: 43 before: 545 now: 545
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:588
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coverage: 80.891% pattern: 43 before: 545 now: 545
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:689
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coverage: 80.891% pattern: 43 before: 545 now: 545
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:641
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coverage: 80.891% pattern: 43 before: 545 now: 545
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:665
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coverage: 80.891% pattern: 43 before: 545 now: 545
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:444
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coverage: 80.891% pattern: 43 before: 545 now: 545
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:453
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coverage: 80.891% pattern: 43 before: 545 now: 545
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:482
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coverage: 80.891% pattern: 43 before: 545 now: 545
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checking valid circuit ... result: 1.
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[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:470
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coverage: 80.891% pattern: 43 before: 545 now: 545
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checking valid circuit ... result: 1.
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|
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:559
|
|||
|
|
coverage: 80.891% pattern: 43 before: 545 now: 545
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 696, fault_cnt:609
|
|||
|
|
coverage: 81.171% pattern: 44 before: 545 now: 537
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:611
|
|||
|
|
coverage: 81.206% pattern: 45 before: 537 now: 536
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:581
|
|||
|
|
coverage: 81.241% pattern: 46 before: 536 now: 535
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:681
|
|||
|
|
coverage: 81.241% pattern: 46 before: 535 now: 535
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 696, fault_cnt:520
|
|||
|
|
coverage: 81.452% pattern: 47 before: 535 now: 529
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:698
|
|||
|
|
coverage: 81.452% pattern: 47 before: 529 now: 529
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:594
|
|||
|
|
coverage: 81.452% pattern: 47 before: 529 now: 529
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:613
|
|||
|
|
coverage: 81.487% pattern: 48 before: 529 now: 528
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:530
|
|||
|
|
coverage: 81.487% pattern: 48 before: 528 now: 528
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:499
|
|||
|
|
coverage: 81.487% pattern: 48 before: 528 now: 528
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 696, fault_cnt:541
|
|||
|
|
coverage: 81.697% pattern: 49 before: 528 now: 522
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:641
|
|||
|
|
coverage: 81.697% pattern: 49 before: 522 now: 522
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:436
|
|||
|
|
coverage: 81.697% pattern: 49 before: 522 now: 522
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:678
|
|||
|
|
coverage: 81.697% pattern: 49 before: 522 now: 522
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:596
|
|||
|
|
coverage: 81.697% pattern: 49 before: 522 now: 522
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
|
|||
|
|
coverage: 81.697% pattern: 49 before: 522 now: 522
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:568
|
|||
|
|
coverage: 81.697% pattern: 49 before: 522 now: 522
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:715
|
|||
|
|
coverage: 81.697% pattern: 49 before: 522 now: 522
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:531
|
|||
|
|
coverage: 81.697% pattern: 49 before: 522 now: 522
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592
|
|||
|
|
coverage: 81.697% pattern: 49 before: 522 now: 522
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:643
|
|||
|
|
coverage: 81.697% pattern: 49 before: 522 now: 522
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:735
|
|||
|
|
coverage: 81.697% pattern: 49 before: 522 now: 522
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 696, fault_cnt:643
|
|||
|
|
coverage: 81.942% pattern: 50 before: 522 now: 515
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 696, fault_cnt:705
|
|||
|
|
coverage: 82.153% pattern: 51 before: 515 now: 509
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:598
|
|||
|
|
coverage: 82.153% pattern: 51 before: 509 now: 509
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:468
|
|||
|
|
coverage: 82.153% pattern: 51 before: 509 now: 509
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:513
|
|||
|
|
coverage: 82.188% pattern: 52 before: 509 now: 508
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:554
|
|||
|
|
coverage: 82.188% pattern: 52 before: 508 now: 508
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:509
|
|||
|
|
coverage: 82.188% pattern: 52 before: 508 now: 508
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:553
|
|||
|
|
coverage: 82.188% pattern: 52 before: 508 now: 508
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:590
|
|||
|
|
coverage: 82.188% pattern: 52 before: 508 now: 508
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:501
|
|||
|
|
coverage: 82.188% pattern: 52 before: 508 now: 508
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 696, fault_cnt:560
|
|||
|
|
coverage: 82.609% pattern: 53 before: 508 now: 496
|
|||
|
|
checking valid circuit ... result: 1.
|
|||
|
|
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:693
|
|||
|
|
coverage: 82.609% pattern: 53 before: 496 now: 496
|
|||
|
|
checking valid circuit ... result: 1.
|