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atpg-ls/exp_result/ATPG-LS_b10.bench.txt

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增加结果
2023-03-09 13:17:53 +08:00
make: 'atpg' is up to date.
========================
parsing file ./benchmark/b10.bench ... Done.
====== Circuit Statistics ======
PI: 28
PO: 23
Gate: 182
Stem: 91
Level: 3
================================
[SOL] flip: 0, stem: 0, fault:1187. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
coverage: 30.495% pattern: 1 before: 364 now: 253
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:779. flip_cnt: 0, stem_cnt: 91, fault_cnt:96
coverage: 41.758% pattern: 2 before: 253 now: 212
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:792. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 53.297% pattern: 3 before: 212 now: 170
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:453. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 67.308% pattern: 4 before: 170 now: 119
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 68.407% pattern: 5 before: 119 now: 115
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 68.956% pattern: 6 before: 115 now: 113
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:361. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
coverage: 74.176% pattern: 7 before: 113 now: 94
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 76.923% pattern: 8 before: 94 now: 84
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 77.473% pattern: 9 before: 84 now: 82
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:135. flip_cnt: 0, stem_cnt: 91, fault_cnt:114
coverage: 79.945% pattern: 10 before: 82 now: 73
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 79.945% pattern: 10 before: 73 now: 73
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 81.044% pattern: 11 before: 73 now: 69
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 82.692% pattern: 12 before: 69 now: 63
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 83.242% pattern: 13 before: 63 now: 61
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 91, fault_cnt:113
coverage: 84.066% pattern: 14 before: 61 now: 58
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 84.066% pattern: 14 before: 58 now: 58
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 85.440% pattern: 15 before: 58 now: 53
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
coverage: 85.440% pattern: 15 before: 53 now: 53
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
coverage: 85.989% pattern: 16 before: 53 now: 51
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 85.989% pattern: 16 before: 51 now: 51
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 85.989% pattern: 16 before: 51 now: 51
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 91, fault_cnt:113
coverage: 89.011% pattern: 17 before: 51 now: 40
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 89.286% pattern: 18 before: 40 now: 39
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 91, fault_cnt:117
coverage: 89.560% pattern: 19 before: 39 now: 38
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
coverage: 89.560% pattern: 19 before: 38 now: 38
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:110
coverage: 89.560% pattern: 19 before: 38 now: 38
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:120
coverage: 89.560% pattern: 19 before: 38 now: 38
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 89.560% pattern: 19 before: 38 now: 38
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
coverage: 90.110% pattern: 20 before: 38 now: 36
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 90.110% pattern: 20 before: 36 now: 36
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
coverage: 90.110% pattern: 20 before: 36 now: 36
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 90.110% pattern: 20 before: 36 now: 36
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:118
coverage: 90.110% pattern: 20 before: 36 now: 36
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 91.209% pattern: 21 before: 36 now: 32
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
coverage: 91.209% pattern: 21 before: 32 now: 32
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 92.033% pattern: 22 before: 32 now: 29
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
coverage: 92.033% pattern: 22 before: 29 now: 29
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
coverage: 92.033% pattern: 22 before: 29 now: 29
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 92.033% pattern: 22 before: 29 now: 29
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 92.033% pattern: 22 before: 29 now: 29
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 93.407% pattern: 23 before: 29 now: 24
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
coverage: 93.407% pattern: 23 before: 24 now: 24
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:85
coverage: 93.407% pattern: 23 before: 24 now: 24
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:113
coverage: 93.407% pattern: 23 before: 24 now: 24
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 93.407% pattern: 23 before: 24 now: 24
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 93.956% pattern: 24 before: 24 now: 22
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:110
coverage: 93.956% pattern: 24 before: 22 now: 22
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 93.956% pattern: 24 before: 22 now: 22
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 93.956% pattern: 24 before: 22 now: 22
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:95
coverage: 93.956% pattern: 24 before: 22 now: 22
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 93.956% pattern: 24 before: 22 now: 22
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 93.956% pattern: 24 before: 22 now: 22
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 93.956% pattern: 24 before: 22 now: 22
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 94.505% pattern: 25 before: 22 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:7. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 95.604% pattern: 26 before: 20 now: 16
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 95.604% pattern: 26 before: 16 now: 16
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 95.604% pattern: 26 before: 16 now: 16
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 95.604% pattern: 26 before: 16 now: 16
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 95.604% pattern: 26 before: 16 now: 16
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 95.604% pattern: 26 before: 16 now: 16
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 95.604% pattern: 26 before: 16 now: 16
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 95.604% pattern: 26 before: 16 now: 16
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:16. flip_cnt: 0, stem_cnt: 91, fault_cnt:115
coverage: 95.879% pattern: 27 before: 16 now: 15
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 95.879% pattern: 27 before: 15 now: 15
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
coverage: 96.429% pattern: 28 before: 15 now: 13
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
coverage: 96.429% pattern: 28 before: 13 now: 13
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 96.429% pattern: 28 before: 13 now: 13
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 96.429% pattern: 28 before: 13 now: 13
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:89
coverage: 96.429% pattern: 28 before: 13 now: 13
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
coverage: 96.429% pattern: 28 before: 13 now: 13
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
coverage: 96.429% pattern: 28 before: 13 now: 13
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 96.429% pattern: 28 before: 13 now: 13
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 96.703% pattern: 29 before: 13 now: 12
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 96.703% pattern: 29 before: 12 now: 12
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:110
coverage: 96.703% pattern: 29 before: 12 now: 12
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:59. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
coverage: 98.077% pattern: 30 before: 12 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:16. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
coverage: 98.626% pattern: 31 before: 7 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:115
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:94
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:114
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
coverage: 98.901% pattern: 32 before: 5 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:96
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:91
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:113
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:95
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:110
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:93
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:91
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:51. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
coverage: 100.000% pattern: 33 before: 4 now: 0
checking valid circuit ... result: 1.
real 0m36.403s
user 0m36.398s
sys 0m0.000s
Reference in New Issue Copy Permalink