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增量 STEM-INC 实验

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YuhangQ 2023-03-09 14:54:23 +08:00
parent 421d533c4a
commit 329f3a849f
31 changed files with 468404 additions and 171449 deletions
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atpg
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check.log
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@ -1,26 +1,26 @@
[1/26] 任务 ./benchmark/b22.bench [1/26] 任务 ./benchmark/c17.bench
[2/26] 任务 ./benchmark/b17.bench [2/26] 任务 ./benchmark/b06.bench
[3/26] 任务 ./benchmark/c5315.bench [3/26] 任务 ./benchmark/b01.bench
[4/26] 任务 ./benchmark/b13.bench [4/26] 任务 ./benchmark/b03.bench
[5/26] 任务 ./benchmark/b03.bench [5/26] 任务 ./benchmark/b09.bench
[6/26] 任务 ./benchmark/c880.bench [6/26] 任务 ./benchmark/c880.bench
[7/26] 任务 ./benchmark/b10.bench [7/26] 任务 ./benchmark/b10.bench
[8/26] 任务 ./benchmark/c6288.bench [8/26] 任务 ./benchmark/b08.bench
[9/26] 任务 ./benchmark/c1355.bench [9/26] 任务 ./benchmark/c499.bench
[10/26] 任务 ./benchmark/b20.bench [10/26] 任务 ./benchmark/c1355.bench
[11/26] 任务 ./benchmark/c17.bench [11/26] 任务 ./benchmark/c3540.bench
[12/26] 任务 ./benchmark/b07.bench [12/26] 任务 ./benchmark/c1908.bench
[13/26] 任务 ./benchmark/b01.bench [13/26] 任务 ./benchmark/b11.bench
[14/26] 任务 ./benchmark/c432.bench [14/26] 任务 ./benchmark/c6288.bench
[15/26] 任务 ./benchmark/b11.bench [15/26] 任务 ./benchmark/c2670.bench
[16/26] 任务 ./benchmark/b08.bench [16/26] 任务 ./benchmark/b21.bench
[17/26] 任务 ./benchmark/c3540.bench [17/26] 任务 ./benchmark/b13.bench
[18/26] 任务 ./benchmark/c2670.bench [18/26] 任务 ./benchmark/b22.bench
[19/26] 任务 ./benchmark/b09.bench [19/26] 任务 ./benchmark/b17.bench
[20/26] 任务 ./benchmark/c7552.bench [20/26] 任务 ./benchmark/b20.bench
[21/26] 任务 ./benchmark/b04.bench [21/26] 任务 ./benchmark/c7552.bench
[22/26] 任务 ./benchmark/b12.bench [22/26] 任务 ./benchmark/b12.bench
[23/26] 任务 ./benchmark/b21.bench [23/26] 任务 ./benchmark/c5315.bench
[24/26] 任务 ./benchmark/b06.bench [24/26] 任务 ./benchmark/b04.bench
[25/26] 任务 ./benchmark/c499.bench [25/26] 任务 ./benchmark/b07.bench
[26/26] 任务 ./benchmark/c1908.bench [26/26] 任务 ./benchmark/c432.bench

133
exp_result/ATPG-LS_b01.bench.txt
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@ -8,82 +8,85 @@ Gate: 48
Stem: 28 Stem: 28
Level: 3 Level: 3
================================ ================================
[SOL] flip: 0, stem: 0, fault:541. flip_cnt: 0, stem_cnt: 28, fault_cnt:42 [SOL] flip: 0, stem: 0, fault:181. flip_cnt: 0, stem_cnt: 28, fault_cnt:41
coverage: 43.750% pattern: 1 before: 96 now: 54 coverage: 42.708% pattern: 1 before: 96 now: 55
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:145. flip_cnt: 0, stem_cnt: 28, fault_cnt:39 [SOL] flip: 0, stem: 0, fault:227. flip_cnt: 0, stem_cnt: 28, fault_cnt:37
coverage: 63.542% pattern: 2 before: 54 now: 35 coverage: 64.583% pattern: 2 before: 55 now: 34
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:43. flip_cnt: 0, stem_cnt: 28, fault_cnt:21 [SOL] flip: 0, stem: 0, fault:59. flip_cnt: 0, stem_cnt: 28, fault_cnt:38
coverage: 68.750% pattern: 3 before: 35 now: 30 coverage: 77.083% pattern: 3 before: 34 now: 22
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 28, fault_cnt:38 [SOL] flip: 0, stem: 0, fault:71. flip_cnt: 0, stem_cnt: 28, fault_cnt:39
coverage: 76.042% pattern: 4 before: 30 now: 23 coverage: 82.292% pattern: 4 before: 22 now: 17
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:2. flip_cnt: 0, stem_cnt: 28, fault_cnt:21 [SOL] flip: 0, stem: 0, fault:5. flip_cnt: 0, stem_cnt: 28, fault_cnt:39
coverage: 78.125% pattern: 5 before: 23 now: 21 coverage: 85.417% pattern: 5 before: 17 now: 14
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 78.125% pattern: 5 before: 21 now: 21 coverage: 85.417% pattern: 5 before: 14 now: 14
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:51. flip_cnt: 0, stem_cnt: 28, fault_cnt:37
coverage: 88.542% pattern: 6 before: 14 now: 11
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:66. flip_cnt: 0, stem_cnt: 28, fault_cnt:32
coverage: 92.708% pattern: 7 before: 11 now: 7
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 78.125% pattern: 5 before: 21 now: 21 coverage: 92.708% pattern: 7 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 78.125% pattern: 5 before: 21 now: 21
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 78.125% pattern: 5 before: 21 now: 21
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:75. flip_cnt: 0, stem_cnt: 28, fault_cnt:32
coverage: 82.292% pattern: 6 before: 21 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 82.292% pattern: 6 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 82.292% pattern: 6 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 82.292% pattern: 6 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 82.292% pattern: 6 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:49. flip_cnt: 0, stem_cnt: 28, fault_cnt:38
coverage: 86.458% pattern: 7 before: 17 now: 13
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 28, fault_cnt:34
coverage: 88.542% pattern: 8 before: 13 now: 11
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:12. flip_cnt: 0, stem_cnt: 28, fault_cnt:37
coverage: 91.667% pattern: 9 before: 11 now: 8
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 28, fault_cnt:37
coverage: 94.792% pattern: 10 before: 8 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:13. flip_cnt: 0, stem_cnt: 28, fault_cnt:31
coverage: 95.833% pattern: 11 before: 5 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 28, fault_cnt:31
coverage: 96.875% pattern: 12 before: 4 now: 3
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:31
coverage: 96.875% pattern: 12 before: 3 now: 3
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:5. flip_cnt: 0, stem_cnt: 28, fault_cnt:38
coverage: 97.917% pattern: 13 before: 3 now: 2
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:38 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:38
coverage: 97.917% pattern: 13 before: 2 now: 2 coverage: 92.708% pattern: 7 before: 7 now: 7
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:11. flip_cnt: 0, stem_cnt: 28, fault_cnt:28 [SOL] flip: 0, stem: 0, fault:13. flip_cnt: 0, stem_cnt: 28, fault_cnt:31
coverage: 98.958% pattern: 14 before: 2 now: 1 coverage: 93.750% pattern: 8 before: 7 now: 6
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:7. flip_cnt: 0, stem_cnt: 28, fault_cnt:34 [SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 28, fault_cnt:34
coverage: 100.000% pattern: 15 before: 1 now: 0 coverage: 95.833% pattern: 9 before: 6 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:6. flip_cnt: 0, stem_cnt: 28, fault_cnt:37
coverage: 96.875% pattern: 10 before: 4 now: 3
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:6. flip_cnt: 0, stem_cnt: 28, fault_cnt:28
coverage: 97.917% pattern: 11 before: 3 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:37
coverage: 97.917% pattern: 11 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:38
coverage: 97.917% pattern: 11 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 97.917% pattern: 11 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 28, fault_cnt:33
coverage: 98.958% pattern: 12 before: 2 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:24
coverage: 98.958% pattern: 12 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 98.958% pattern: 12 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:39
coverage: 98.958% pattern: 12 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:38
coverage: 98.958% pattern: 12 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:25
coverage: 98.958% pattern: 12 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:34
coverage: 98.958% pattern: 12 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:31
coverage: 98.958% pattern: 12 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:17. flip_cnt: 0, stem_cnt: 28, fault_cnt:31
coverage: 100.000% pattern: 13 before: 1 now: 0
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
real 0m0.364s real 0m0.239s
user 0m0.359s user 0m0.237s
sys 0m0.004s sys 0m0.000s

7
exp_result/ATPG-LS_b02.bench.txt
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@ -1,7 +0,0 @@
make: 'atpg' is up to date.
========================
parsing file ./benchmark/b02.bench ...Error while reading file: DFF is not a valid gate.
real 0m0.003s
user 0m0.001s
sys 0m0.000s

158
exp_result/ATPG-LS_b03.bench.txt
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@ -8,118 +8,94 @@ Gate: 152
Stem: 86 Stem: 86
Level: 3 Level: 3
================================ ================================
[SOL] flip: 0, stem: 0, fault:1483. flip_cnt: 0, stem_cnt: 86, fault_cnt:117 [SOL] flip: 0, stem: 0, fault:741. flip_cnt: 0, stem_cnt: 86, fault_cnt:117
coverage: 38.487% pattern: 1 before: 304 now: 187 coverage: 38.487% pattern: 1 before: 304 now: 187
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1222. flip_cnt: 0, stem_cnt: 86, fault_cnt:121 [SOL] flip: 0, stem: 0, fault:440. flip_cnt: 0, stem_cnt: 86, fault_cnt:114
coverage: 60.526% pattern: 2 before: 187 now: 120 coverage: 65.789% pattern: 2 before: 187 now: 104
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:170. flip_cnt: 0, stem_cnt: 86, fault_cnt:107 [SOL] flip: 0, stem: 0, fault:338. flip_cnt: 0, stem_cnt: 86, fault_cnt:119
coverage: 73.026% pattern: 3 before: 120 now: 82 coverage: 78.618% pattern: 3 before: 104 now: 65
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:399. flip_cnt: 0, stem_cnt: 86, fault_cnt:124 [SOL] flip: 0, stem: 0, fault:113. flip_cnt: 0, stem_cnt: 86, fault_cnt:119
coverage: 79.934% pattern: 4 before: 82 now: 61 coverage: 84.539% pattern: 4 before: 65 now: 47
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:62. flip_cnt: 0, stem_cnt: 86, fault_cnt:117 [SOL] flip: 0, stem: 0, fault:137. flip_cnt: 0, stem_cnt: 86, fault_cnt:111
coverage: 83.224% pattern: 5 before: 61 now: 51 coverage: 92.434% pattern: 5 before: 47 now: 23
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:72. flip_cnt: 0, stem_cnt: 86, fault_cnt:113 [SOL] flip: 0, stem: 0, fault:32. flip_cnt: 0, stem_cnt: 86, fault_cnt:107
coverage: 84.539% pattern: 6 before: 51 now: 47 coverage: 94.737% pattern: 6 before: 23 now: 16
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 86, fault_cnt:121 [SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 86, fault_cnt:108
coverage: 85.526% pattern: 7 before: 47 now: 44 coverage: 95.724% pattern: 7 before: 16 now: 13
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 86, fault_cnt:115 [SOL] flip: 0, stem: 0, fault:2. flip_cnt: 0, stem_cnt: 86, fault_cnt:112
coverage: 89.803% pattern: 8 before: 44 now: 31 coverage: 96.382% pattern: 8 before: 13 now: 11
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:138. flip_cnt: 0, stem_cnt: 86, fault_cnt:117 [SOL] flip: 0, stem: 0, fault:2. flip_cnt: 0, stem_cnt: 86, fault_cnt:120
coverage: 92.434% pattern: 9 before: 31 now: 23 coverage: 96.711% pattern: 9 before: 11 now: 10
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 86, fault_cnt:114 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:112
coverage: 93.092% pattern: 10 before: 23 now: 21 coverage: 96.711% pattern: 9 before: 10 now: 10
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:119 [SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:115
coverage: 93.092% pattern: 10 before: 21 now: 21 coverage: 98.355% pattern: 10 before: 10 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:117
coverage: 93.421% pattern: 11 before: 21 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:127
coverage: 93.750% pattern: 12 before: 20 now: 19
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 86, fault_cnt:122
coverage: 94.408% pattern: 13 before: 19 now: 17
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:120 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:120
coverage: 94.408% pattern: 13 before: 17 now: 17 coverage: 98.355% pattern: 10 before: 5 now: 5
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:86. flip_cnt: 0, stem_cnt: 86, fault_cnt:111 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:125
coverage: 98.355% pattern: 14 before: 17 now: 5 coverage: 98.355% pattern: 10 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 86, fault_cnt:113
coverage: 99.013% pattern: 15 before: 5 now: 3
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:117
coverage: 99.342% pattern: 16 before: 3 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:116
coverage: 99.342% pattern: 16 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:116
coverage: 99.342% pattern: 16 before: 2 now: 2
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:118 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:118
coverage: 99.342% pattern: 16 before: 2 now: 2 coverage: 98.355% pattern: 10 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:119
coverage: 99.342% pattern: 16 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:115
coverage: 99.342% pattern: 16 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:122
coverage: 99.342% pattern: 16 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:113
coverage: 99.342% pattern: 16 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:114
coverage: 99.671% pattern: 17 before: 2 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:121
coverage: 99.671% pattern: 17 before: 1 now: 1
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:111 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:111
coverage: 99.671% pattern: 17 before: 1 now: 1 coverage: 98.355% pattern: 10 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:116
coverage: 99.671% pattern: 17 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:117
coverage: 99.671% pattern: 17 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:115
coverage: 99.671% pattern: 17 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:120
coverage: 99.671% pattern: 17 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:109
coverage: 99.671% pattern: 17 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:113
coverage: 99.671% pattern: 17 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:111
coverage: 99.671% pattern: 17 before: 1 now: 1
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:124 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:124
coverage: 99.671% pattern: 17 before: 1 now: 1 coverage: 98.355% pattern: 10 before: 5 now: 5
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:127 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:123
coverage: 100.000% pattern: 18 before: 1 now: 0 coverage: 98.355% pattern: 10 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:125
coverage: 98.355% pattern: 10 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:118
coverage: 98.355% pattern: 10 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:15. flip_cnt: 0, stem_cnt: 86, fault_cnt:109
coverage: 99.342% pattern: 11 before: 5 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:109
coverage: 99.342% pattern: 11 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:112
coverage: 99.342% pattern: 11 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1. flip_cnt: 0, stem_cnt: 86, fault_cnt:115
coverage: 99.671% pattern: 12 before: 2 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:115
coverage: 99.671% pattern: 12 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:114
coverage: 99.671% pattern: 12 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:116
coverage: 99.671% pattern: 12 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:111
coverage: 99.671% pattern: 12 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:117
coverage: 99.671% pattern: 12 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:3. flip_cnt: 0, stem_cnt: 86, fault_cnt:114
coverage: 100.000% pattern: 13 before: 1 now: 0
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
real 0m5.785s real 0m0.783s
user 0m5.778s user 0m0.778s
sys 0m0.004s sys 0m0.004s

38575
exp_result/ATPG-LS_b04.bench.txt
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80
exp_result/ATPG-LS_b06.bench.txt
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@ -8,49 +8,67 @@ Gate: 56
Stem: 42 Stem: 42
Level: 3 Level: 3
================================ ================================
[SOL] flip: 0, stem: 0, fault:513. flip_cnt: 0, stem_cnt: 42, fault_cnt:44 [SOL] flip: 0, stem: 0, fault:159. flip_cnt: 0, stem_cnt: 42, fault_cnt:43
coverage: 39.286% pattern: 1 before: 112 now: 68 coverage: 38.393% pattern: 1 before: 112 now: 69
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:99. flip_cnt: 0, stem_cnt: 42, fault_cnt:44 [SOL] flip: 0, stem: 0, fault:107. flip_cnt: 0, stem_cnt: 42, fault_cnt:43
coverage: 66.071% pattern: 2 before: 68 now: 38 coverage: 65.179% pattern: 2 before: 69 now: 39
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:10. flip_cnt: 0, stem_cnt: 42, fault_cnt:45 [SOL] flip: 0, stem: 0, fault:23. flip_cnt: 0, stem_cnt: 42, fault_cnt:45
coverage: 75.000% pattern: 3 before: 38 now: 28 coverage: 78.571% pattern: 3 before: 39 now: 24
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:204. flip_cnt: 0, stem_cnt: 42, fault_cnt:45 [SOL] flip: 0, stem: 0, fault:64. flip_cnt: 0, stem_cnt: 42, fault_cnt:46
coverage: 86.607% pattern: 4 before: 28 now: 15 coverage: 90.179% pattern: 4 before: 24 now: 11
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:56. flip_cnt: 0, stem_cnt: 42, fault_cnt:45 [SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 42, fault_cnt:41
coverage: 90.179% pattern: 5 before: 15 now: 11 coverage: 91.071% pattern: 5 before: 11 now: 10
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:12. flip_cnt: 0, stem_cnt: 42, fault_cnt:47 [SOL] flip: 0, stem: 0, fault:54. flip_cnt: 0, stem_cnt: 42, fault_cnt:45
coverage: 91.071% pattern: 6 before: 11 now: 10 coverage: 94.643% pattern: 6 before: 10 now: 6
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:6. flip_cnt: 0, stem_cnt: 42, fault_cnt:40 [SOL] flip: 0, stem: 0, fault:18. flip_cnt: 0, stem_cnt: 42, fault_cnt:36
coverage: 92.857% pattern: 7 before: 10 now: 8 coverage: 97.321% pattern: 7 before: 6 now: 3
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:8. flip_cnt: 0, stem_cnt: 42, fault_cnt:41 [SOL] flip: 0, stem: 0, fault:14. flip_cnt: 0, stem_cnt: 42, fault_cnt:43
coverage: 93.750% pattern: 8 before: 8 now: 7 coverage: 98.214% pattern: 8 before: 3 now: 2
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 42, fault_cnt:36 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:40
coverage: 96.429% pattern: 9 before: 7 now: 4 coverage: 98.214% pattern: 8 before: 2 now: 2
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:7. flip_cnt: 0, stem_cnt: 42, fault_cnt:40 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:44
coverage: 97.321% pattern: 10 before: 4 now: 3 coverage: 98.214% pattern: 8 before: 2 now: 2
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:3. flip_cnt: 0, stem_cnt: 42, fault_cnt:43 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:34
coverage: 98.214% pattern: 11 before: 3 now: 2 coverage: 98.214% pattern: 8 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:13. flip_cnt: 0, stem_cnt: 42, fault_cnt:44
coverage: 99.107% pattern: 12 before: 2 now: 1
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:46 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:46
coverage: 99.107% pattern: 12 before: 1 now: 1 coverage: 98.214% pattern: 8 before: 2 now: 2
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1. flip_cnt: 0, stem_cnt: 42, fault_cnt:40 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:45
coverage: 100.000% pattern: 13 before: 1 now: 0 coverage: 98.214% pattern: 8 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:35
coverage: 98.214% pattern: 8 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:36
coverage: 98.214% pattern: 8 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:41
coverage: 98.214% pattern: 8 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:13. flip_cnt: 0, stem_cnt: 42, fault_cnt:47
coverage: 99.107% pattern: 9 before: 2 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:41
coverage: 99.107% pattern: 9 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:46
coverage: 99.107% pattern: 9 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:15. flip_cnt: 0, stem_cnt: 42, fault_cnt:44
coverage: 100.000% pattern: 10 before: 1 now: 0
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
real 0m0.098s real 0m0.107s
user 0m0.093s user 0m0.105s
sys 0m0.004s sys 0m0.000s

54000
exp_result/ATPG-LS_b07.bench.txt
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exp_result/ATPG-LS_b08.bench.txt
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exp_result/ATPG-LS_b09.bench.txt
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exp_result/ATPG-LS_b10.bench.txt
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25388
exp_result/ATPG-LS_b11.bench.txt
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exp_result/ATPG-LS_b12.bench.txt
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108874
exp_result/ATPG-LS_b13.bench.txt
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69
exp_result/ATPG-LS_b20.bench.txt
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@ -8,3 +8,72 @@ Gate: 8734
Stem: 3428 Stem: 3428
Level: 7 Level: 7
================================ ================================
[SOL] flip: 0, stem: 0, fault:49107. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3179
coverage: 18.199% pattern: 1 before: 17468 now: 14289
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:28816. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3009
coverage: 27.908% pattern: 2 before: 14289 now: 12593
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:31154. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3635
coverage: 37.423% pattern: 3 before: 12593 now: 10931
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:7652. flip_cnt: 0, stem_cnt: 3428, fault_cnt:2945
coverage: 39.873% pattern: 4 before: 10931 now: 10503
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:3885. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3014
coverage: 41.127% pattern: 5 before: 10503 now: 10284
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:5760. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3259
coverage: 42.896% pattern: 6 before: 10284 now: 9975
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1034. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3045
coverage: 43.222% pattern: 7 before: 9975 now: 9918
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1011. flip_cnt: 0, stem_cnt: 3428, fault_cnt:2979
coverage: 43.537% pattern: 8 before: 9918 now: 9863
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:381. flip_cnt: 0, stem_cnt: 3428, fault_cnt:2987
coverage: 43.657% pattern: 9 before: 9863 now: 9842
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:10489. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3399
coverage: 46.823% pattern: 10 before: 9842 now: 9289
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:153. flip_cnt: 0, stem_cnt: 3428, fault_cnt:2905
coverage: 46.874% pattern: 11 before: 9289 now: 9280
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:5681. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3417
coverage: 48.586% pattern: 12 before: 9280 now: 8981
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:63. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3038
coverage: 48.615% pattern: 13 before: 8981 now: 8976
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 3428, fault_cnt:2944
coverage: 48.632% pattern: 14 before: 8976 now: 8973
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3002
coverage: 48.655% pattern: 15 before: 8973 now: 8969
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:23. flip_cnt: 0, stem_cnt: 3428, fault_cnt:2898
coverage: 48.666% pattern: 16 before: 8969 now: 8967
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3189
coverage: 48.683% pattern: 17 before: 8967 now: 8964
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3016
coverage: 48.683% pattern: 17 before: 8964 now: 8964
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 3428, fault_cnt:2987
coverage: 48.683% pattern: 17 before: 8964 now: 8964
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3030
coverage: 48.695% pattern: 18 before: 8964 now: 8962
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3133
coverage: 48.695% pattern: 18 before: 8962 now: 8962
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:874. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3187
coverage: 48.958% pattern: 19 before: 8962 now: 8916
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3076
coverage: 48.958% pattern: 19 before: 8916 now: 8916
checking valid circuit ... result: 1.

66
exp_result/ATPG-LS_b21.bench.txt
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@ -8,3 +8,69 @@ Gate: 8995
Stem: 3647 Stem: 3647
Level: 8 Level: 8
================================ ================================
[SOL] flip: 0, stem: 0, fault:51387. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2917
coverage: 16.215% pattern: 1 before: 17990 now: 15073
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:31083. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2990
coverage: 26.148% pattern: 2 before: 15073 now: 13286
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:13816. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2964
coverage: 30.812% pattern: 3 before: 13286 now: 12447
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:8210. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2890
coverage: 33.346% pattern: 4 before: 12447 now: 11991
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:14317. flip_cnt: 0, stem_cnt: 3647, fault_cnt:3232
coverage: 37.599% pattern: 5 before: 11991 now: 11226
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:2900. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2982
coverage: 38.471% pattern: 6 before: 11226 now: 11069
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1253. flip_cnt: 0, stem_cnt: 3647, fault_cnt:3028
coverage: 38.844% pattern: 7 before: 11069 now: 11002
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:3176. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2858
coverage: 39.789% pattern: 8 before: 11002 now: 10832
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:5492. flip_cnt: 0, stem_cnt: 3647, fault_cnt:3168
coverage: 41.401% pattern: 9 before: 10832 now: 10542
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:290. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2893
coverage: 41.501% pattern: 10 before: 10542 now: 10524
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:382. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2988
coverage: 41.618% pattern: 11 before: 10524 now: 10503
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:191. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2956
coverage: 41.679% pattern: 12 before: 10503 now: 10492
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2804
coverage: 41.723% pattern: 13 before: 10492 now: 10484
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1750. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2770
coverage: 42.240% pattern: 14 before: 10484 now: 10391
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:78. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2984
coverage: 42.268% pattern: 15 before: 10391 now: 10386
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2959
coverage: 42.279% pattern: 16 before: 10386 now: 10384
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2897
coverage: 42.279% pattern: 16 before: 10384 now: 10384
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:3610. flip_cnt: 0, stem_cnt: 3647, fault_cnt:3191
coverage: 43.335% pattern: 17 before: 10384 now: 10194
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:513. flip_cnt: 0, stem_cnt: 3647, fault_cnt:3083
coverage: 43.485% pattern: 18 before: 10194 now: 10167
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2897
coverage: 43.513% pattern: 19 before: 10167 now: 10162
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1501. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2843
coverage: 43.952% pattern: 20 before: 10162 now: 10083
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:4629. flip_cnt: 0, stem_cnt: 3647, fault_cnt:3206
coverage: 45.309% pattern: 21 before: 10083 now: 9839
checking valid circuit ... result: 1.

12
exp_result/ATPG-LS_b22.bench.txt
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@ -8,3 +8,15 @@ Gate: 13721
Stem: 5379 Stem: 5379
Level: 8 Level: 8
================================ ================================
[SOL] flip: 0, stem: 0, fault:75481. flip_cnt: 0, stem_cnt: 5379, fault_cnt:4379
coverage: 15.957% pattern: 1 before: 27442 now: 23063
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:42481. flip_cnt: 0, stem_cnt: 5379, fault_cnt:4587
coverage: 24.299% pattern: 2 before: 23063 now: 20774
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19160. flip_cnt: 0, stem_cnt: 5379, fault_cnt:4476
coverage: 28.613% pattern: 3 before: 20774 now: 19590
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:10322. flip_cnt: 0, stem_cnt: 5379, fault_cnt:4248
coverage: 30.701% pattern: 4 before: 19590 now: 19017
checking valid circuit ... result: 1.

55649
exp_result/ATPG-LS_c1355.bench.txt
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4
exp_result/ATPG-LS_c17.bench.txt
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@ -20,10 +20,10 @@ checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 9, fault_cnt:8 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 9, fault_cnt:8
coverage: 90.909% pattern: 3 before: 2 now: 2 coverage: 90.909% pattern: 3 before: 2 now: 2
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:2. flip_cnt: 0, stem_cnt: 9, fault_cnt:6 [SOL] flip: 0, stem: 0, fault:2. flip_cnt: 0, stem_cnt: 9, fault_cnt:5
coverage: 100.000% pattern: 4 before: 2 now: 0 coverage: 100.000% pattern: 4 before: 2 now: 0
checking valid circuit ... result: 1. checking valid circuit ... result: 1.
real 0m0.004s real 0m0.003s
user 0m0.002s user 0m0.002s
sys 0m0.000s sys 0m0.000s

25848
exp_result/ATPG-LS_c1908.bench.txt
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13745
exp_result/ATPG-LS_c2670.bench.txt
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1818
exp_result/ATPG-LS_c3540.bench.txt
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265492
exp_result/ATPG-LS_c432.bench.txt
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25118
exp_result/ATPG-LS_c499.bench.txt
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2424
exp_result/ATPG-LS_c5315.bench.txt
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996
exp_result/ATPG-LS_c6288.bench.txt
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2425
exp_result/ATPG-LS_c7552.bench.txt
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2978
exp_result/ATPG-LS_c880.bench.txt
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2
ls.cpp
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@ -109,7 +109,7 @@ bool Circuit::local_search(std::unordered_set<Fault*> &faults) {
CC[suc->id] = 1; CC[suc->id] = 1;
} }
printf("[UP] flip: %lld, stem: %lld, fault:%lld. flip_cnt: %lld, stem_cnt: %lld, fault_cnt:%lld\n", flip_total_weight, stem_total_weight, fault_total_weight, flip_total_cnt, stem_total_cnt, fault_total_cnt); //printf("[UP] flip: %lld, stem: %lld, fault:%lld. flip_cnt: %lld, stem_cnt: %lld, fault_cnt:%lld\n", flip_total_weight, stem_total_weight, fault_total_weight, flip_total_cnt, stem_total_cnt, fault_total_cnt);
} }
} }

30
report/atpg-ls-动态增量.txt Normal file
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@ -0,0 +1,30 @@
--------------------------------------------------------------------------------------------------------------
| data | fault coverage(ATPG-LS) | time(ATPG-LS) | cube(ATPG-LS) | pattern(ATPG-LS) |
| ----------------------- | ----------------------- | ------------------- | ------------- | ---------------- |
| ./benchmark/c17.bench | 100.000 | 0.11560654640197754 | 4 | 4 |
| ./benchmark/b06.bench | 100.000 | 0.11869049072265625 | 10 | 10 |
| ./benchmark/b01.bench | 100.000 | 0.3559579849243164 | 13 | 13 |
| ./benchmark/b03.bench | 100.000 | 0.8975160121917725 | 13 | 13 |
| ./benchmark/b09.bench | 100.000 | 6.73541784286499 | 20 | 20 |
| ./benchmark/c880.bench | 100.000 | 13.738963603973389 | 38 | 38 |
| ./benchmark/b10.bench | 100.000 | 13.915901899337769 | 31 | 31 |
| ./benchmark/b08.bench | 100.000 | 44.885215282440186 | 36 | 36 |
| ./benchmark/c499.bench | 100.000 | 72.9014344215393 | 59 | 59 |
| ./benchmark/c1355.bench | 100.000 | 354.89149928092957 | 93 | 93 |
| ./benchmark/c3540.bench | 92.932 | 2000.0045857429504 | 126 | 126 |
| ./benchmark/c1908.bench | 99.452 | 2000.0044167041779 | 85 | 85 |
| ./benchmark/b11.bench | 98.485 | 2000.0039746761322 | 59 | 59 |
| ./benchmark/c6288.bench | 99.653 | 2000.005141735077 | 37 | 37 |
| ./benchmark/c2670.bench | 94.881 | 2000.0041010379791 | 75 | 75 |
| ./benchmark/b21.bench | 45.309 | 2000.031025648117 | 21 | 21 |
| ./benchmark/b13.bench | 98.602 | 2000.030693769455 | 30 | 30 |
| ./benchmark/b22.bench | 30.701 | 2000.1147837638855 | 4 | 4 |
| ./benchmark/b17.bench | ERROR | 2000.1162934303284 | ERROR | ERROR |
| ./benchmark/b20.bench | 48.958 | 2000.1155791282654 | 19 | 19 |
| ./benchmark/c7552.bench | 95.832 | 2000.1170272827148 | 134 | 134 |
| ./benchmark/b12.bench | 94.418 | 2000.1147434711456 | 123 | 123 |
| ./benchmark/c5315.bench | 99.175 | 2000.1144452095032 | 139 | 139 |
| ./benchmark/b04.bench | 99.659 | 2000.1151909828186 | 50 | 50 |
| ./benchmark/b07.bench | 98.687 | 2000.1153008937836 | 34 | 34 |
| ./benchmark/c432.bench | 99.235 | 2000.1161303520203 | 28 | 28 |
--------------------------------------------------------------------------------------------------------------

6
run_exp.py
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@ -186,9 +186,9 @@ def multiprocess_run_solver(solver, input_file):
(path, filename) = os.path.split(input_file) (path, filename) = os.path.split(input_file)
out_file = os.path.join(res_dir,"%s_%s.txt" % (solver.name, filename)) out_file = os.path.join(res_dir,"%s_%s.txt" % (solver.name, filename))
#(status, time) = solver.run(input_file, out_file, TIMEOUT) (status, time) = solver.run(input_file, out_file, TIMEOUT)
time = "-*-" # time = "-*-"
status = ExitStatus.normal # status = ExitStatus.normal
fault = "-*-" fault = "-*-"
cube = "-*-" cube = "-*-"