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YuhangQ 2023-03-22 02:46:14 +00:00
parent c8ef5ac6dd
commit 39e218b333
94 changed files with 1760 additions and 574570 deletions
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CCAnr: cca.cpp cca.h basis.h cw.h preprocessor.h
g++ cca.cpp -O3 -static -o CCAnr

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#ifndef _BASIS_H_
#define _BASIS_H_
#include <iostream>
#include <fstream>
#include <cstdlib>
#include <cmath>
using namespace std;
enum type{SAT3, SAT5, SAT7, strSAT} probtype;
/* limits on the size of the problem. */
#define MAX_VARS 4000010
#define MAX_CLAUSES 20000000
// Define a data structure for a literal in the SAT problem.
struct lit {
int clause_num; //clause num, begin with 0
int var_num; //variable num, begin with 1
int sense; //is 1 for true literals, 0 for false literals.
};
/*parameters of the instance*/
int num_vars; //var index from 1 to num_vars
int num_clauses; //clause index from 0 to num_clauses-1
int max_clause_len;
int min_clause_len;
int formula_len=0;
double avg_clause_len;
double ratio;
/* literal arrays */
lit* var_lit[MAX_VARS]; //var_lit[i][j] means the j'th literal of var i.
int var_lit_count[MAX_VARS]; //amount of literals of each var
lit* clause_lit[MAX_CLAUSES]; //clause_lit[i][j] means the j'th literal of clause i.
int clause_lit_count[MAX_CLAUSES]; // amount of literals in each clause
lit* org_clause_lit[MAX_CLAUSES]; //clause_lit[i][j] means the j'th literal of clause i.
int org_clause_lit_count[MAX_CLAUSES]; // amount of literals in each clause
int simplify=0;
/* Information about the variables. */
int score[MAX_VARS];
int time_stamp[MAX_VARS];
int conf_change[MAX_VARS];
int* var_neighbor[MAX_VARS];
int var_neighbor_count[MAX_VARS];
//int pscore[MAX_VARS];
int fix[MAX_VARS];
/* Information about the clauses */
int clause_weight[MAX_CLAUSES];
int sat_count[MAX_CLAUSES];
int sat_var[MAX_CLAUSES];
//int sat_var2[MAX_CLAUSES];
//unsat clauses stack
int unsat_stack[MAX_CLAUSES]; //store the unsat clause number
int unsat_stack_fill_pointer;
int index_in_unsat_stack[MAX_CLAUSES];//which position is a clause in the unsat_stack
int this_try_best_unsat_stack_fill_pointer;
//variables in unsat clauses
int unsatvar_stack[MAX_VARS];
int unsatvar_stack_fill_pointer;
int index_in_unsatvar_stack[MAX_VARS];
int unsat_app_count[MAX_VARS]; //a varible appears in how many unsat clauses
//configuration changed decreasing variables (score>0 and confchange=1)
int goodvar_stack[MAX_VARS];
int goodvar_stack_fill_pointer;
int already_in_goodvar_stack[MAX_VARS];
//unit clauses preprocess
lit unitclause_queue[MAX_VARS];
int unitclause_queue_beg_pointer=0;
int unitclause_queue_end_pointer=0;
int clause_delete[MAX_CLAUSES];
/* Information about solution */
int cur_soln[MAX_VARS]; //the current solution, with 1's for True variables, and 0's for False variables
//cutoff
int max_tries = 10000;
int tries;
int max_flips = 2000000000;
int step;
void setup_datastructure();
void free_memory();
int build_instance(char *filename);
void build_neighbor_relation();
void free_memory()
{
int i;
for (i = 0; i < num_clauses; i++)
{
delete[] clause_lit[i];
}
for(i=1; i<=num_vars; ++i)
{
delete[] var_lit[i];
delete[] var_neighbor[i];
}
}
/*
* Read in the problem.
*/
int temp_lit[MAX_VARS]; //the max length of a clause can be MAX_VARS
int build_instance(char *filename)
{
char line[1000000];
char tempstr1[10];
char tempstr2[10];
int cur_lit;
int i,j;
int v,c;//var, clause
ifstream infile(filename);
if(!infile.is_open())
return 0;
/*** build problem data structures of the instance ***/
infile.getline(line,1000000);
while (line[0] != 'p')
infile.getline(line,1000000);
sscanf(line, "%s %s %d %d", tempstr1, tempstr2, &num_vars, &num_clauses);
::ratio = double(num_clauses) / num_vars;
if(num_vars>=MAX_VARS || num_clauses>=MAX_CLAUSES)
{
cout<<"the size of instance exceeds out limitation, please enlarge MAX_VARS and (or) MAX_CLAUSES."<<endl;
exit(-1);
}
for (c = 0; c < num_clauses; c++)
{
clause_lit_count[c] = 0;
clause_delete[c] = 0;
}
for (v=1; v<=num_vars; ++v)
{
var_lit_count[v] = 0;
fix[v] = 0;
}
max_clause_len = 0;
min_clause_len = num_vars;
//Now, read the clauses, one at a time.
for (c = 0; c < num_clauses; c++)
{
infile>>cur_lit;
while (cur_lit != 0) {
temp_lit[clause_lit_count[c]] = cur_lit;
clause_lit_count[c]++;
infile>>cur_lit;
}
clause_lit[c] = new lit[clause_lit_count[c]+1];
for(i=0; i<clause_lit_count[c]; ++i)
{
clause_lit[c][i].clause_num = c;
clause_lit[c][i].var_num = abs(temp_lit[i]);
if (temp_lit[i] > 0) clause_lit[c][i].sense = 1;
else clause_lit[c][i].sense = 0;
var_lit_count[clause_lit[c][i].var_num]++;
}
clause_lit[c][i].var_num=0;
clause_lit[c][i].clause_num = -1;
//unit clause
if(clause_lit_count[c]==1)
{
unitclause_queue[unitclause_queue_end_pointer++] = clause_lit[c][0];
clause_delete[c]=1;
}
if(clause_lit_count[c] > max_clause_len)
max_clause_len = clause_lit_count[c];
else if(clause_lit_count[c] < min_clause_len)
min_clause_len = clause_lit_count[c];
formula_len += clause_lit_count[c];
}
infile.close();
avg_clause_len = (double)formula_len/num_clauses;
if(unitclause_queue_end_pointer>0)
{
simplify = 1;
for (c = 0; c < num_clauses; c++)
{
org_clause_lit_count[c] = clause_lit_count[c];
org_clause_lit[c] = new lit[clause_lit_count[c]+1];
for(i=0; i<org_clause_lit_count[c]; ++i)
{
org_clause_lit[c][i] = clause_lit[c][i];
}
}
}
//creat var literal arrays
for (v=1; v<=num_vars; ++v)
{
var_lit[v] = new lit[var_lit_count[v]+1];
var_lit_count[v] = 0; //reset to 0, for build up the array
}
//scan all clauses to build up var literal arrays
for (c = 0; c < num_clauses; ++c)
{
for(i=0; i<clause_lit_count[c]; ++i)
{
v = clause_lit[c][i].var_num;
var_lit[v][var_lit_count[v]] = clause_lit[c][i];
++var_lit_count[v];
}
}
for (v=1; v<=num_vars; ++v) //set boundary
var_lit[v][var_lit_count[v]].clause_num=-1;
return 1;
}
void build_neighbor_relation()
{
int* neighbor_flag = new int[num_vars+1];
int i,j,count;
int v,c;
for(v=1; v<=num_vars; ++v)
{
var_neighbor_count[v] = 0;
if(fix[v]==1) continue;
for(i=1; i<=num_vars; ++i)
neighbor_flag[i] = 0;
neighbor_flag[v] = 1;
for(i=0; i<var_lit_count[v]; ++i)
{
c = var_lit[v][i].clause_num;
if(clause_delete[c]==1) continue;
for(j=0; j<clause_lit_count[c]; ++j)
{
if(neighbor_flag[clause_lit[c][j].var_num]==0)
{
var_neighbor_count[v]++;
neighbor_flag[clause_lit[c][j].var_num] = 1;
}
}
}
neighbor_flag[v] = 0;
var_neighbor[v] = new int[var_neighbor_count[v]+1];
count = 0;
for(i=1; i<=num_vars; ++i)
{
if(fix[i]==1) continue;
if(neighbor_flag[i]==1)
{
var_neighbor[v][count] = i;
count++;
}
}
var_neighbor[v][count]=0;
}
delete[] neighbor_flag; neighbor_flag=NULL;
}
void print_solution()
{
int i;
cout<<"v ";
for (i=1; i<=num_vars; i++) {
if(cur_soln[i]==0) cout<<"-";
cout<<i;
if(i%10==0) cout<<endl<<"v ";
else cout<<' ';
}
cout<<"0"<<endl;
}
int verify_sol()
{
int c,j;
int flag;
if(simplify==0)
{
for (c = 0; c<num_clauses; ++c)
{
flag = 0;
for(j=0; j<clause_lit_count[c]; ++j)
if (cur_soln[clause_lit[c][j].var_num] == clause_lit[c][j].sense) {flag = 1; break;}
if(flag ==0){//output the clause unsatisfied by the solution
cout<<"c clause "<<c<<" is not satisfied"<<endl;
cout<<"c ";
for(j=0; j<clause_lit_count[c]; ++j)
{
if(clause_lit[c][j].sense==0)cout<<"-";
cout<<clause_lit[c][j].var_num<<" ";
}
cout<<endl;
for(j=0; j<clause_lit_count[c]; ++j)
cout<<cur_soln[clause_lit[c][j].var_num]<<" ";
cout<<endl;
return 0;
}
}
}
if(simplify==1)
{
for (c = 0; c<num_clauses; ++c)
{
flag = 0;
for(j=0; j<org_clause_lit_count[c]; ++j)
if (cur_soln[org_clause_lit[c][j].var_num] == org_clause_lit[c][j].sense) {flag = 1; break;}
if(flag ==0){//output the clause unsatisfied by the solution
cout<<"c clause "<<c<<" is not satisfied"<<endl;
if(clause_delete[c]==1)cout<<"c this clause is deleted by UP."<<endl;
cout<<"c ";
for(j=0; j<org_clause_lit_count[c]; ++j)
{
if(org_clause_lit[c][j].sense==0)cout<<"-";
cout<<org_clause_lit[c][j].var_num<<" ";
}
cout<<endl;
for(j=0; j<org_clause_lit_count[c]; ++j)
cout<<cur_soln[org_clause_lit[c][j].var_num]<<" ";
cout<<endl;
return 0;
}
}
}
return 1;
}
#endif

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#include "basis.h"
#include "cca.h"
#include "cw.h"
#include "preprocessor.h"
#include <string.h>
#include <sys/times.h> //these two h files are for linux
#include <unistd.h>
#include "ccanr.h"
char * inst;
int seed;
long long ls_no_improv_times;
bool aspiration_active;
static int pick_var(void)
{
int i,k,c,v;
int best_var;
lit* clause_c;
/**Greedy Mode**/
/*CCD (configuration changed decreasing) mode, the level with configuation chekcing*/
if(goodvar_stack_fill_pointer>0)
{
//if(goodvar_stack_fill_pointer<balancePar)
//{
best_var = goodvar_stack[0];
for(i=1; i<goodvar_stack_fill_pointer; ++i)
{
v=goodvar_stack[i];
if(score[v]>score[best_var]) best_var = v;
else if(score[v]==score[best_var])
{
//if(unsat_app_count[v]>unsat_app_count[best_var]) best_var = v;
//else if(unsat_app_count[v]==unsat_app_count[best_var]&&time_stamp[v]<time_stamp[best_var]) best_var = v;
if(time_stamp[v]<time_stamp[best_var]) best_var = v;
}
}
return best_var;
//}
/*else
{
best_var = goodvar_stack[rand()%goodvar_stack_fill_pointer];
for(int j=1;j<balancePar;++j)
{
v = goodvar_stack[rand()%goodvar_stack_fill_pointer];
if(score[v]>score[best_var]) best_var = v;
else if(score[v]==score[best_var])
{
//if(unsat_app_count[v]>unsat_app_count[best_var]) best_var = v;
//else if(unsat_app_count[v]==unsat_app_count[best_var]&&time_stamp[v]<time_stamp[best_var]) best_var = v;
if(time_stamp[v]<time_stamp[best_var]) best_var = v;
}
}
return best_var;
}*/
}
/*aspiration*/
if (aspiration_active)
{
best_var = 0;
for(i=0; i<unsatvar_stack_fill_pointer; ++i)
{
if(score[unsatvar_stack[i]]>ave_weight)
{
best_var = unsatvar_stack[i];
break;
}
}
for(++i; i<unsatvar_stack_fill_pointer; ++i)
{
v=unsatvar_stack[i];
if(score[v]>score[best_var]) best_var = v;
else if(score[v]==score[best_var] && time_stamp[v]<time_stamp[best_var]) best_var = v;
}
if(best_var!=0) return best_var;
}
/*****end aspiration*******************/
update_clause_weights();
/*focused random walk*/
c = unsat_stack[rand()%unsat_stack_fill_pointer];
clause_c = clause_lit[c];
best_var = clause_c[0].var_num;
for(k=1; k<clause_lit_count[c]; ++k)
{
v=clause_c[k].var_num;
//using score
//if(score[v]>score[best_var]) best_var = v;
//else if(score[v]==score[best_var]&&time_stamp[v]<time_stamp[best_var]) best_var = v;
//using unweighted make
if(unsat_app_count[v]>unsat_app_count[best_var]) best_var = v;
//else if(unsat_app_count[v]==unsat_app_count[best_var] && time_stamp[v]<time_stamp[best_var]) best_var = v;
else if(unsat_app_count[v]==unsat_app_count[best_var])
{
if(score[v]>score[best_var]) best_var = v;
else if(score[v]==score[best_var]&&time_stamp[v]<time_stamp[best_var]) best_var = v;
}
}
return best_var;
}
//set functions in the algorithm
void settings()
{
//set_clause_weighting();
//aspiration_active = false; //
}
/*
void local_search(int max_flips)
{
int flipvar;
for (step = 0; step<max_flips; step++)
{
//find a solution
if(unsat_stack_fill_pointer==0) return;
flipvar = pick_var();
flip(flipvar);
time_stamp[flipvar] = step;
}
}
*/
void local_search(long long no_improv_times)
{
int flipvar;
long long notime = 1 + no_improv_times;
// printf("cur_sol: ");
// for(int i=1; i<=num_vars; i++) {
// printf("%d ", cur_soln[i]);
// }
// printf("\n");
while(--notime)
{
flipvar = pick_var();
flip(flipvar);
time_stamp[flipvar] = step;
step++;
if(unsat_stack_fill_pointer < this_try_best_unsat_stack_fill_pointer)
{
this_try_best_unsat_stack_fill_pointer = unsat_stack_fill_pointer;
notime = 1 + no_improv_times;
}
if(unsat_stack_fill_pointer == 0)
{
return;
}
}
return;
}
void default_settings()
{
seed = 1;
ls_no_improv_times = 200000;
p_scale = 0.3;
q_scale = 0.7;
threshold = 50;
aspiration_active = false; //
}
int CCAnr::module_pick_var() {
return pick_var();
}
void CCAnr::module_flip_var(int flipvar) {
flip(flipvar);
time_stamp[flipvar] = step;
step++;
if(unsat_stack_fill_pointer < this_try_best_unsat_stack_fill_pointer)
{
this_try_best_unsat_stack_fill_pointer = unsat_stack_fill_pointer;
}
if(unsat_stack_fill_pointer == 0)
{
printf("[CCAnr] find solution!\n");
if(verify_sol()!=1) {
cout<<"c Sorry, something is wrong."<<endl;
exit(-1);
}
}
}
int* CCAnr::module_cur_soln() {
return cur_soln;
}
void CCAnr::module_reset() {
settings();
init();
}
void CCAnr::module_init()
{
int seed,i;
int satisfy_flag=0;
struct tms start, stop;
cout<<"c This is CCAnr 2.0 [Version: 2018.01.28] [Author: Shaowei Cai]."<<endl;
times(&start);
default_settings();
build_instance("test.cnf");
srand(seed);
//if(unitclause_queue_end_pointer > 0) preprocess();
build_neighbor_relation();
scale_ave=(threshold+1)*q_scale; //
cout<<"c Instance: Number of variables = "<<num_vars<<endl;
cout<<"c Instance: Number of clauses = "<<num_clauses<<endl;
cout<<"c Instance: Ratio = "<<::ratio<<endl;
cout<<"c Instance: Formula length = "<<formula_len<<endl;
cout<<"c Instance: Avg (Min,Max) clause length = "<<avg_clause_len<<" ("<<min_clause_len<<","<<max_clause_len<<")"<<endl;
cout<<"c Algorithmic: Random seed = "<<seed<<endl;
cout<<"c Algorithmic: ls_no_improv_steps = " << ls_no_improv_times << endl;
cout<<"c Algorithmic: swt_p = " << p_scale << endl;
cout<<"c Algorithmic: swt_q = " << q_scale << endl;
cout<<"c Algorithmic: swt_threshold = " << threshold << endl;
cout<<"c Algorithmic: scale_ave = " << scale_ave << endl;
if(aspiration_active) cout<<"c Algorithmic: aspiration_active = true" << endl;
else cout<<"c Algorithmic: aspiration_active = false" << endl;
// for (tries = 0; tries <= max_tries; tries++)
// {
// settings();
// init();
// local_search(ls_no_improv_times);
// if (unsat_stack_fill_pointer==0)
// {
// if(verify_sol()==1) {satisfy_flag = 1; break;}
// else cout<<"c Sorry, something is wrong."<<endl;/////
// }
// }
// times(&stop);
// double comp_time = double(stop.tms_utime - start.tms_utime +stop.tms_stime - start.tms_stime) / sysconf(_SC_CLK_TCK);
// if(satisfy_flag==1)
// {
// cout<<"s SATISFIABLE"<<endl;
// //print_solution();
// }
// else cout<<"s UNKNOWN"<<endl;
// cout<<"c solveSteps = "<<tries<<" tries + "<<step<<" steps (each try has "<<max_flips<<" steps)."<<endl;
// cout<<"c solveTime = "<<comp_time<<endl;
// free_memory();
return;
}

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/************************************=== CCAnr ===***************************************
** CCAnr is a local search solver for the Boolean Satisfiability (SAT) problem,
** which is especially designed for non-random instances.
** CCAnr is designed and implemented by Shaowei Cai (email: shaoweicai.cs@gmail.com),
*****************************************************************************************/
/*****************************=== Develpment history ===*************************************
** 2011.5
** SWCC (Smoothed Weighting and Configuration Checking) by Shaowei Cai
** New Idea: Configuration Checking (CC)
** A variable is configuration changed, if since its last flip, at least one of its
** neighboring var has been flipped.
** In the greedy mode, Swcc picks the best Configuration Changed Decreasing var to flip.
** In the random mode, it updates weights, and flips the oldest var in a random unsat clause.
** 2011.9
** SWCCA (Smoothed Weighting and Configuration Checking with Aspiration) by Shaowei Cai
** New Idea: CC with Aspiration (CCA)
** Modification: in greedy mode, it first prefers to flip the best CCD var. If there is
** no CCD variable, then flip the best significant decreasing var, i.e., with a great
** positive score (in Swcca, bigger than averaged clause weight), if there exsit such vars.
** 2013.4
** CCAnr (CCA for non-random SAT)
** Modifications: Generalize the smoothig fomula as w(ci)=w(ci)*p+ave_w*q; pick the greediest
** variable in the diversification mode.
************************************************************************************************/
#ifndef _CCA_H_
#define _CCA_H_
#include "basis.h"
#define pop(stack) stack[--stack ## _fill_pointer]
#define push(item, stack) stack[stack ## _fill_pointer++] = item
inline void unsat(int clause)
{
index_in_unsat_stack[clause] = unsat_stack_fill_pointer;
push(clause,unsat_stack);
//update appreance count of each var in unsat clause and update stack of vars in unsat clauses
int v;
for(lit* p=clause_lit[clause]; (v=p->var_num)!=0; p++)
{
unsat_app_count[v]++;
if(unsat_app_count[v]==1)
{
index_in_unsatvar_stack[v] = unsatvar_stack_fill_pointer;
push(v,unsatvar_stack);
}
}
}
inline void sat(int clause)
{
int index,last_unsat_clause;
//since the clause is satisfied, its position can be reused to store the last_unsat_clause
last_unsat_clause = pop(unsat_stack);
index = index_in_unsat_stack[clause];
unsat_stack[index] = last_unsat_clause;
index_in_unsat_stack[last_unsat_clause] = index;
//update appreance count of each var in unsat clause and update stack of vars in unsat clauses
int v,last_unsat_var;
for(lit* p=clause_lit[clause]; (v=p->var_num)!=0; p++)
{
unsat_app_count[v]--;
if(unsat_app_count[v]==0)
{
last_unsat_var = pop(unsatvar_stack);
index = index_in_unsatvar_stack[v];
unsatvar_stack[index] = last_unsat_var;
index_in_unsatvar_stack[last_unsat_var] = index;
}
}
}
//initiation of the algorithm
void init()
{
int v,c;
int i,j;
int clause;
//Initialize edge weights
for (c = 0; c<num_clauses; c++)
clause_weight[c] = 1;
//init unsat_stack
unsat_stack_fill_pointer = 0;
unsatvar_stack_fill_pointer = 0;
//init solution
for (v = 1; v <= num_vars; v++) {
if(fix[v]==0){
if(rand()%2==1) cur_soln[v] = 1;
else cur_soln[v] = 0;
time_stamp[v] = 0;
conf_change[v] = 1;
unsat_app_count[v] = 0;
//pscore[v] = 0;
}
}
/* figure out sat_count, and init unsat_stack */
for (c=0; c<num_clauses; ++c)
{
if(clause_delete[c]==1) continue;
sat_count[c] = 0;
for(j=0; j<clause_lit_count[c]; ++j)
{
if (cur_soln[clause_lit[c][j].var_num] == clause_lit[c][j].sense)
{
sat_count[c]++;
sat_var[c] = clause_lit[c][j].var_num;
}
}
if (sat_count[c] == 0)
unsat(c);
}
/*figure out var score*/
int lit_count;
for (v=1; v<=num_vars; v++)
{
if(fix[v]==1)
{
score[v] = -100000;
continue;
}
score[v] = 0;
lit_count = var_lit_count[v];
for(i=0; i<lit_count; ++i)
{
c = var_lit[v][i].clause_num;
if (sat_count[c]==0) score[v]++;
else if (sat_count[c]==1 && var_lit[v][i].sense==cur_soln[v]) score[v]--;
}
}
/*
int flag;
//compute pscore and record sat_var and sat_var2 for 2sat clauses
for (c=0; c<num_clauses; ++c)
{
if(clause_delete[c]==1) continue;
if (sat_count[c]==1)
{
for(j=0;j<clause_lit_count[c];++j)
{
v=clause_lit[c][j].var_num;
if(v!=sat_var[c])pscore[v]++;
}
}
else if(sat_count[c]==2)
{
flag=0;
for(j=0;j<clause_lit_count[c];++j)
{
v=clause_lit[c][j].var_num;
if(clause_lit[c][j].sense == cur_soln[v])
{
pscore[v]--;
if(flag==0){sat_var[c] = v; flag=1;}
else {sat_var2[c] = v; break;}
}
}
}
}
*/
//init goodvars stack
goodvar_stack_fill_pointer = 0;
for (v=1; v<=num_vars; v++)
{
if(fix[v]==1) continue;
if(score[v]>0)// && conf_change[v]==1)
{
already_in_goodvar_stack[v] = 1;
push(v,goodvar_stack);
}
else already_in_goodvar_stack[v] = 0;
}
//setting for the virtual var 0
time_stamp[0]=0;
//pscore[0]=0;
this_try_best_unsat_stack_fill_pointer = unsat_stack_fill_pointer;
}
void flip(int flipvar)
{
cur_soln[flipvar] = 1 - cur_soln[flipvar];
int i,j;
int v,c;
lit* clause_c;
int org_flipvar_score = score[flipvar];
//update related clauses and neighbor vars
for(lit *q = var_lit[flipvar]; (c=q->clause_num)>=0; q++)
{
clause_c = clause_lit[c];
if(cur_soln[flipvar] == q->sense)
{
++sat_count[c];
if (sat_count[c] == 2) //sat_count from 1 to 2
score[sat_var[c]] += clause_weight[c];
else if (sat_count[c] == 1) // sat_count from 0 to 1
{
sat_var[c] = flipvar;//record the only true lit's var
for(lit* p=clause_c; (v=p->var_num)!=0; p++) score[v] -= clause_weight[c];
sat(c);
}
}
else // cur_soln[flipvar] != cur_lit.sense
{
--sat_count[c];
if (sat_count[c] == 1) //sat_count from 2 to 1
{
for(lit* p=clause_c; (v=p->var_num)!=0; p++)
{
if(p->sense == cur_soln[v] )
{
score[v] -= clause_weight[c];
sat_var[c] = v;
break;
}
}
}
else if (sat_count[c] == 0) //sat_count from 1 to 0
{
for(lit* p=clause_c; (v=p->var_num)!=0; p++) score[v] += clause_weight[c];
unsat(c);
}//end else if
}//end else
}
score[flipvar] = -org_flipvar_score;
/*update CCD */
int index;
conf_change[flipvar] = 0;
//remove the vars no longer goodvar in goodvar stack
for(index=goodvar_stack_fill_pointer-1; index>=0; index--)
{
v = goodvar_stack[index];
if(score[v]<=0)
{
goodvar_stack[index] = pop(goodvar_stack);
already_in_goodvar_stack[v] = 0;
}
}
//update all flipvar's neighbor's conf_change to be 1, add goodvar
int* p;
for(p=var_neighbor[flipvar]; (v=*p)!=0; p++)
{
conf_change[v] = 1;
if(score[v]>0 && already_in_goodvar_stack[v] ==0)
{
push(v,goodvar_stack);
already_in_goodvar_stack[v] = 1;
}
}
}
#endif

9
CCAnr/ccanr.h Normal file
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namespace CCAnr {
void module_init();
int module_pick_var();
void module_flip_var(int var);
void module_reset();
int* module_cur_soln();
}

103
CCAnr/cw.h Normal file
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#ifndef _CW_H_
#define _CW_H_
#include "basis.h"
#define sigscore ave_weight //significant score needed for aspiration
int ave_weight=1;
int delta_total_weight=0;
/**************************************** clause weighting for 3sat **************************************************/
int threshold;
float p_scale;//w=w*p+ave_w*q
float q_scale=0;
int scale_ave;//scale_ave==ave_weight*q_scale
int q_init=0;
void smooth_clause_weights()
{
int i,j,c,v;
int new_total_weight=0;
for (v=1; v<=num_vars; ++v)
score[v] = 0;
//smooth clause score and update score of variables
for (c = 0; c<num_clauses; ++c)
{
clause_weight[c] = clause_weight[c]*p_scale+scale_ave;
if(clause_weight[c]<1) clause_weight[c] = 1;
new_total_weight+=clause_weight[c];
//update score of variables in this clause
if (sat_count[c]==0)
{
for(j=0; j<clause_lit_count[c]; ++j)
{
score[clause_lit[c][j].var_num] += clause_weight[c];
}
}
else if(sat_count[c]==1)
score[sat_var[c]]-=clause_weight[c];
}
ave_weight=new_total_weight/num_clauses;
}
void update_clause_weights()
{
int i,v;
for(i=0; i < unsat_stack_fill_pointer; ++i)
clause_weight[unsat_stack[i]]++;
for(i=0; i<unsatvar_stack_fill_pointer; ++i)
{
v = unsatvar_stack[i];
score[v] += unsat_app_count[v];
if(score[v]>0 && conf_change[v]==1 && already_in_goodvar_stack[v] ==0)
{
push(v,goodvar_stack);
already_in_goodvar_stack[v] =1;
}
}
delta_total_weight+=unsat_stack_fill_pointer;
if(delta_total_weight>=num_clauses)
{
ave_weight+=1;
delta_total_weight -= num_clauses;
//smooth weights
if(ave_weight>threshold)
smooth_clause_weights();
}
}
void set_clause_weighting()
{
threshold=300;
p_scale=0.3;
if(q_init==0)
{
if(::ratio<=15) q_scale=0;
else q_scale=0.7;
}
else
{
if(q_scale<0.5) //0
q_scale = 0.7;
else
q_scale = 0;
}
scale_ave=(threshold+1)*q_scale;
q_init = 1;
}
#endif

133
CCAnr/preprocessor.h Normal file
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#include "basis.h"
//preprocess
void unit_propagation()
{
lit uc_lit;
int uc_clause;
int uc_var;
bool uc_sense;
int c,v;
int i,j;
lit cur, cur_c;
//while (unitclause_queue_beg_pointer < unitclause_queue_end_pointer)
for(unitclause_queue_beg_pointer=0; unitclause_queue_beg_pointer < unitclause_queue_end_pointer; unitclause_queue_beg_pointer++)
{
uc_lit = unitclause_queue[unitclause_queue_beg_pointer];
uc_var = uc_lit.var_num;
uc_sense = uc_lit.sense;
if(fix[uc_var]==1) {if(uc_sense!=cur_soln[uc_var])cout<<"c wants to fix a variable twice, forbid."<<endl; continue;}
cur_soln[uc_var] = uc_sense;//fix the variable in unit clause
fix[uc_var] = 1;
for(i = 0; i<var_lit_count[uc_var]; ++i)
{
cur = var_lit[uc_var][i];
c = cur.clause_num;
if(clause_delete[c]==1) continue;
if(cur.sense == uc_sense)//then remove the clause from var's var_lit[] array
{
clause_delete[c]=1;
}
else
{
if(clause_lit_count[c]==2)
{
if(clause_lit[c][0].var_num == uc_var)
{
unitclause_queue[unitclause_queue_end_pointer++] = clause_lit[c][1];
}
else
{
unitclause_queue[unitclause_queue_end_pointer++] = clause_lit[c][0];
}
clause_delete[c]=1;
}
else
{
for(j=0; j<clause_lit_count[c]; ++j)
{
if(clause_lit[c][j].var_num == uc_var)
{
clause_lit[c][j]=clause_lit[c][clause_lit_count[c]-1];
clause_lit_count[c]--;
break;
}
}//for
}
}
}//for
}//begpointer to endpointer for
}
void preprocess()
{
int c,v,i;
int delete_clause_count=0;
int fix_var_count=0;
unit_propagation();
//rescan all clauses to build up var literal arrays
for (v=1; v<=num_vars; ++v)
var_lit_count[v] = 0;
max_clause_len = 0;
min_clause_len = num_vars;
int formula_len=0;
for (c = 0; c < num_clauses; ++c)
{
if(clause_delete[c]==1) {
delete_clause_count++;
continue;
}
for(i=0; i<clause_lit_count[c]; ++i)
{
v = clause_lit[c][i].var_num;
var_lit[v][var_lit_count[v]] = clause_lit[c][i];
++var_lit_count[v];
}
clause_lit[c][i].var_num=0; //new clause boundary
clause_lit[c][i].clause_num = -1;
//about clause length
formula_len += clause_lit_count[c];
if(clause_lit_count[c] > max_clause_len)
max_clause_len = clause_lit_count[c];
else if(clause_lit_count[c] < min_clause_len)
min_clause_len = clause_lit_count[c];
}
avg_clause_len = (double)formula_len/num_clauses;
for (v=1; v<=num_vars; ++v)
{
if(fix[v]==1)
{
fix_var_count++;
}
var_lit[v][var_lit_count[v]].clause_num=-1;//new var_lit boundary
}
cout<<"c unit propagation fixes "<<fix_var_count<<" variables, and delets "<<delete_clause_count<<" clauses"<<endl;
}

515
CCAnr/test.cnf Normal file
View File

@ -0,0 +1,515 @@
p cnf 196 514
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37 1 0
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38 2 0
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64 43 0
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109
ISCAS85/Mylib.lib
View File

@ -1,109 +0,0 @@
library(demo) {
cell(NAND4) {
area: 15;
pin(A) { direction: input; }
pin(B) { direction: input; }
pin(C) { direction: input; }
pin(D) { direction: input; }
pin(Y) { direction: output; function: "(A*B*C*D)'"; } }
cell(NAND3) {
area: 12;
pin(A) { direction: input; }
pin(B) { direction: input; }
pin(C) { direction: input; }
pin(Y) { direction: output; function: "(A*B*C)'"; } }
cell(NAND2) {
area: 10;
pin(A) { direction: input; }
pin(B) { direction: input; }
pin(Y) { direction: output; function: "(A*B)'"; } }
cell(AND4) {
area: 20;
pin(A) { direction: input; }
pin(B) { direction: input; }
pin(C) { direction: input; }
pin(D) { direction: input; }
pin(Y) { direction: output; function: "(A*B*C*D)"; } }
cell(AND3) {
area: 15;
pin(A) { direction: input; }
pin(B) { direction: input; }
pin(C) { direction: input; }
pin(Y) { direction: output; function: "(A*B*C)"; } }
cell(AND2) {
area: 12;
pin(A) { direction: input; }
pin(B) { direction: input; }
pin(Y) { direction: output; function: "(A*B)"; } }
cell(NOR4) {
area: 20;
pin(A) { direction: input; }
pin(B) { direction: input; }
pin(C) { direction: input; }
pin(D) { direction: input; }
pin(Y) { direction: output; function: "(A+B+C+D)'"; } }
cell(NOR3) {
area: 15;
pin(A) { direction: input; }
pin(B) { direction: input; }
pin(C) { direction: input; }
pin(Y) { direction: output; function: "(A+B+C)'"; } }
cell(NOR2) {
area: 10;
pin(A) { direction: input; }
pin(B) { direction: input; }
pin(Y) { direction: output; function: "(A+B)'"; } }
cell(OR4) {
area: 20;
pin(A) { direction: input; }
pin(B) { direction: input; }
pin(C) { direction: input; }
pin(D) { direction: input; }
pin(Y) { direction: output; function: "(A+B+C+D)"; } }
cell(OR3) {
area: 15;
pin(A) { direction: input; }
pin(B) { direction: input; }
pin(C) { direction: input; }
pin(Y) { direction: output; function: "(A+B+C)"; } }
cell(OR2) {
area: 10;
pin(A) { direction: input; }
pin(B) { direction: input; }
pin(Y) { direction: output; function: "(A+B)"; } }
cell(XNOR2) {
area: 25;
pin(A) { direction: input; }
pin(B) { direction: input; }
pin(Y) { direction: output; function: "(A^B)'"; } }
cell(XOR2) {
area: 25;
pin(A) { direction: input; }
pin(B) { direction: input; }
pin(Y) { direction: output; function: "(A^B)"; } }
cell(BUF) {
area: 12;
pin(A) { direction: input; }
pin(Y) { direction: output; function: "A"; } }
cell(NOT) {
area: 6;
pin(A) { direction: input; }
pin(Y) { direction: output; function: "A'"; } }
}

623
ISCAS85/c1355.bench
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@ -1,623 +0,0 @@
# c1355
INPUT(1)
INPUT(8)
INPUT(15)
INPUT(22)
INPUT(29)
INPUT(36)
INPUT(43)
INPUT(50)
INPUT(57)
INPUT(64)
INPUT(71)
INPUT(78)
INPUT(85)
INPUT(92)
INPUT(99)
INPUT(106)
INPUT(113)
INPUT(120)
INPUT(127)
INPUT(134)
INPUT(141)
INPUT(148)
INPUT(155)
INPUT(162)
INPUT(169)
INPUT(176)
INPUT(183)
INPUT(190)
INPUT(197)
INPUT(204)
INPUT(211)
INPUT(218)
INPUT(225)
INPUT(226)
INPUT(227)
INPUT(228)
INPUT(229)
INPUT(230)
INPUT(231)
INPUT(232)
INPUT(233)
OUTPUT(1324)
OUTPUT(1325)
OUTPUT(1326)
OUTPUT(1327)
OUTPUT(1328)
OUTPUT(1329)
OUTPUT(1330)
OUTPUT(1331)
OUTPUT(1332)
OUTPUT(1333)
OUTPUT(1334)
OUTPUT(1335)
OUTPUT(1336)
OUTPUT(1337)
OUTPUT(1338)
OUTPUT(1339)
OUTPUT(1340)
OUTPUT(1341)
OUTPUT(1342)
OUTPUT(1343)
OUTPUT(1344)
OUTPUT(1345)
OUTPUT(1346)
OUTPUT(1347)
OUTPUT(1348)
OUTPUT(1349)
OUTPUT(1350)
OUTPUT(1351)
OUTPUT(1352)
OUTPUT(1353)
OUTPUT(1354)
OUTPUT(1355)
242 = AND(225, 233)
245 = AND(226, 233)
248 = AND(227, 233)
251 = AND(228, 233)
254 = AND(229, 233)
257 = AND(230, 233)
260 = AND(231, 233)
263 = AND(232, 233)
266 = NAND(1, 8)
269 = NAND(15, 22)
272 = NAND(29, 36)
275 = NAND(43, 50)
278 = NAND(57, 64)
281 = NAND(71, 78)
284 = NAND(85, 92)
287 = NAND(99, 106)
290 = NAND(113, 120)
293 = NAND(127, 134)
296 = NAND(141, 148)
299 = NAND(155, 162)
302 = NAND(169, 176)
305 = NAND(183, 190)
308 = NAND(197, 204)
311 = NAND(211, 218)
314 = NAND(1, 29)
317 = NAND(57, 85)
320 = NAND(8, 36)
323 = NAND(64, 92)
326 = NAND(15, 43)
329 = NAND(71, 99)
332 = NAND(22, 50)
335 = NAND(78, 106)
338 = NAND(113, 141)
341 = NAND(169, 197)
344 = NAND(120, 148)
347 = NAND(176, 204)
350 = NAND(127, 155)
353 = NAND(183, 211)
356 = NAND(134, 162)
359 = NAND(190, 218)
362 = NAND(1, 266)
363 = NAND(8, 266)
364 = NAND(15, 269)
365 = NAND(22, 269)
366 = NAND(29, 272)
367 = NAND(36, 272)
368 = NAND(43, 275)
369 = NAND(50, 275)
370 = NAND(57, 278)
371 = NAND(64, 278)
372 = NAND(71, 281)
373 = NAND(78, 281)
374 = NAND(85, 284)
375 = NAND(92, 284)
376 = NAND(99, 287)
377 = NAND(106, 287)
378 = NAND(113, 290)
379 = NAND(120, 290)
380 = NAND(127, 293)
381 = NAND(134, 293)
382 = NAND(141, 296)
383 = NAND(148, 296)
384 = NAND(155, 299)
385 = NAND(162, 299)
386 = NAND(169, 302)
387 = NAND(176, 302)
388 = NAND(183, 305)
389 = NAND(190, 305)
390 = NAND(197, 308)
391 = NAND(204, 308)
392 = NAND(211, 311)
393 = NAND(218, 311)
394 = NAND(1, 314)
395 = NAND(29, 314)
396 = NAND(57, 317)
397 = NAND(85, 317)
398 = NAND(8, 320)
399 = NAND(36, 320)
400 = NAND(64, 323)
401 = NAND(92, 323)
402 = NAND(15, 326)
403 = NAND(43, 326)
404 = NAND(71, 329)
405 = NAND(99, 329)
406 = NAND(22, 332)
407 = NAND(50, 332)
408 = NAND(78, 335)
409 = NAND(106, 335)
410 = NAND(113, 338)
411 = NAND(141, 338)
412 = NAND(169, 341)
413 = NAND(197, 341)
414 = NAND(120, 344)
415 = NAND(148, 344)
416 = NAND(176, 347)
417 = NAND(204, 347)
418 = NAND(127, 350)
419 = NAND(155, 350)
420 = NAND(183, 353)
421 = NAND(211, 353)
422 = NAND(134, 356)
423 = NAND(162, 356)
424 = NAND(190, 359)
425 = NAND(218, 359)
426 = NAND(362, 363)
429 = NAND(364, 365)
432 = NAND(366, 367)
435 = NAND(368, 369)
438 = NAND(370, 371)
441 = NAND(372, 373)
444 = NAND(374, 375)
447 = NAND(376, 377)
450 = NAND(378, 379)
453 = NAND(380, 381)
456 = NAND(382, 383)
459 = NAND(384, 385)
462 = NAND(386, 387)
465 = NAND(388, 389)
468 = NAND(390, 391)
471 = NAND(392, 393)
474 = NAND(394, 395)
477 = NAND(396, 397)
480 = NAND(398, 399)
483 = NAND(400, 401)
486 = NAND(402, 403)
489 = NAND(404, 405)
492 = NAND(406, 407)
495 = NAND(408, 409)
498 = NAND(410, 411)
501 = NAND(412, 413)
504 = NAND(414, 415)
507 = NAND(416, 417)
510 = NAND(418, 419)
513 = NAND(420, 421)
516 = NAND(422, 423)
519 = NAND(424, 425)
522 = NAND(426, 429)
525 = NAND(432, 435)
528 = NAND(438, 441)
531 = NAND(444, 447)
534 = NAND(450, 453)
537 = NAND(456, 459)
540 = NAND(462, 465)
543 = NAND(468, 471)
546 = NAND(474, 477)
549 = NAND(480, 483)
552 = NAND(486, 489)
555 = NAND(492, 495)
558 = NAND(498, 501)
561 = NAND(504, 507)
564 = NAND(510, 513)
567 = NAND(516, 519)
570 = NAND(426, 522)
571 = NAND(429, 522)
572 = NAND(432, 525)
573 = NAND(435, 525)
574 = NAND(438, 528)
575 = NAND(441, 528)
576 = NAND(444, 531)
577 = NAND(447, 531)
578 = NAND(450, 534)
579 = NAND(453, 534)
580 = NAND(456, 537)
581 = NAND(459, 537)
582 = NAND(462, 540)
583 = NAND(465, 540)
584 = NAND(468, 543)
585 = NAND(471, 543)
586 = NAND(474, 546)
587 = NAND(477, 546)
588 = NAND(480, 549)
589 = NAND(483, 549)
590 = NAND(486, 552)
591 = NAND(489, 552)
592 = NAND(492, 555)
593 = NAND(495, 555)
594 = NAND(498, 558)
595 = NAND(501, 558)
596 = NAND(504, 561)
597 = NAND(507, 561)
598 = NAND(510, 564)
599 = NAND(513, 564)
600 = NAND(516, 567)
601 = NAND(519, 567)
602 = NAND(570, 571)
607 = NAND(572, 573)
612 = NAND(574, 575)
617 = NAND(576, 577)
622 = NAND(578, 579)
627 = NAND(580, 581)
632 = NAND(582, 583)
637 = NAND(584, 585)
642 = NAND(586, 587)
645 = NAND(588, 589)
648 = NAND(590, 591)
651 = NAND(592, 593)
654 = NAND(594, 595)
657 = NAND(596, 597)
660 = NAND(598, 599)
663 = NAND(600, 601)
666 = NAND(602, 607)
669 = NAND(612, 617)
672 = NAND(602, 612)
675 = NAND(607, 617)
678 = NAND(622, 627)
681 = NAND(632, 637)
684 = NAND(622, 632)
687 = NAND(627, 637)
690 = NAND(602, 666)
691 = NAND(607, 666)
692 = NAND(612, 669)
693 = NAND(617, 669)
694 = NAND(602, 672)
695 = NAND(612, 672)
696 = NAND(607, 675)
697 = NAND(617, 675)
698 = NAND(622, 678)
699 = NAND(627, 678)
700 = NAND(632, 681)
701 = NAND(637, 681)
702 = NAND(622, 684)
703 = NAND(632, 684)
704 = NAND(627, 687)
705 = NAND(637, 687)
706 = NAND(690, 691)
709 = NAND(692, 693)
712 = NAND(694, 695)
715 = NAND(696, 697)
718 = NAND(698, 699)
721 = NAND(700, 701)
724 = NAND(702, 703)
727 = NAND(704, 705)
730 = NAND(242, 718)
733 = NAND(245, 721)
736 = NAND(248, 724)
739 = NAND(251, 727)
742 = NAND(254, 706)
745 = NAND(257, 709)
748 = NAND(260, 712)
751 = NAND(263, 715)
754 = NAND(242, 730)
755 = NAND(718, 730)
756 = NAND(245, 733)
757 = NAND(721, 733)
758 = NAND(248, 736)
759 = NAND(724, 736)
760 = NAND(251, 739)
761 = NAND(727, 739)
762 = NAND(254, 742)
763 = NAND(706, 742)
764 = NAND(257, 745)
765 = NAND(709, 745)
766 = NAND(260, 748)
767 = NAND(712, 748)
768 = NAND(263, 751)
769 = NAND(715, 751)
770 = NAND(754, 755)
773 = NAND(756, 757)
776 = NAND(758, 759)
779 = NAND(760, 761)
782 = NAND(762, 763)
785 = NAND(764, 765)
788 = NAND(766, 767)
791 = NAND(768, 769)
794 = NAND(642, 770)
797 = NAND(645, 773)
800 = NAND(648, 776)
803 = NAND(651, 779)
806 = NAND(654, 782)
809 = NAND(657, 785)
812 = NAND(660, 788)
815 = NAND(663, 791)
818 = NAND(642, 794)
819 = NAND(770, 794)
820 = NAND(645, 797)
821 = NAND(773, 797)
822 = NAND(648, 800)
823 = NAND(776, 800)
824 = NAND(651, 803)
825 = NAND(779, 803)
826 = NAND(654, 806)
827 = NAND(782, 806)
828 = NAND(657, 809)
829 = NAND(785, 809)
830 = NAND(660, 812)
831 = NAND(788, 812)
832 = NAND(663, 815)
833 = NAND(791, 815)
834 = NAND(818, 819)
847 = NAND(820, 821)
860 = NAND(822, 823)
873 = NAND(824, 825)
886 = NAND(828, 829)
899 = NAND(832, 833)
912 = NAND(830, 831)
925 = NAND(826, 827)
938 = NOT(834)
939 = NOT(847)
940 = NOT(860)
941 = NOT(834)
942 = NOT(847)
943 = NOT(873)
944 = NOT(834)
945 = NOT(860)
946 = NOT(873)
947 = NOT(847)
948 = NOT(860)
949 = NOT(873)
950 = NOT(886)
951 = NOT(899)
952 = NOT(886)
953 = NOT(912)
954 = NOT(925)
955 = NOT(899)
956 = NOT(925)
957 = NOT(912)
958 = NOT(925)
959 = NOT(886)
960 = NOT(912)
961 = NOT(925)
962 = NOT(886)
963 = NOT(899)
964 = NOT(925)
965 = NOT(912)
966 = NOT(899)
967 = NOT(886)
968 = NOT(912)
969 = NOT(899)
970 = NOT(847)
971 = NOT(873)
972 = NOT(847)
973 = NOT(860)
974 = NOT(834)
975 = NOT(873)
976 = NOT(834)
977 = NOT(860)
978 = AND(938, 939, 940, 873)
979 = AND(941, 942, 860, 943)
980 = AND(944, 847, 945, 946)
981 = AND(834, 947, 948, 949)
982 = AND(958, 959, 960, 899)
983 = AND(961, 962, 912, 963)
984 = AND(964, 886, 965, 966)
985 = AND(925, 967, 968, 969)
986 = OR(978, 979, 980, 981)
991 = OR(982, 983, 984, 985)
996 = AND(925, 950, 912, 951, 986)
1001 = AND(925, 952, 953, 899, 986)
1006 = AND(954, 886, 912, 955, 986)
1011 = AND(956, 886, 957, 899, 986)
1016 = AND(834, 970, 860, 971, 991)
1021 = AND(834, 972, 973, 873, 991)
1026 = AND(974, 847, 860, 975, 991)
1031 = AND(976, 847, 977, 873, 991)
1036 = AND(834, 996)
1039 = AND(847, 996)
1042 = AND(860, 996)
1045 = AND(873, 996)
1048 = AND(834, 1001)
1051 = AND(847, 1001)
1054 = AND(860, 1001)
1057 = AND(873, 1001)
1060 = AND(834, 1006)
1063 = AND(847, 1006)
1066 = AND(860, 1006)
1069 = AND(873, 1006)
1072 = AND(834, 1011)
1075 = AND(847, 1011)
1078 = AND(860, 1011)
1081 = AND(873, 1011)
1084 = AND(925, 1016)
1087 = AND(886, 1016)
1090 = AND(912, 1016)
1093 = AND(899, 1016)
1096 = AND(925, 1021)
1099 = AND(886, 1021)
1102 = AND(912, 1021)
1105 = AND(899, 1021)
1108 = AND(925, 1026)
1111 = AND(886, 1026)
1114 = AND(912, 1026)
1117 = AND(899, 1026)
1120 = AND(925, 1031)
1123 = AND(886, 1031)
1126 = AND(912, 1031)
1129 = AND(899, 1031)
1132 = NAND(1, 1036)
1135 = NAND(8, 1039)
1138 = NAND(15, 1042)
1141 = NAND(22, 1045)
1144 = NAND(29, 1048)
1147 = NAND(36, 1051)
1150 = NAND(43, 1054)
1153 = NAND(50, 1057)
1156 = NAND(57, 1060)
1159 = NAND(64, 1063)
1162 = NAND(71, 1066)
1165 = NAND(78, 1069)
1168 = NAND(85, 1072)
1171 = NAND(92, 1075)
1174 = NAND(99, 1078)
1177 = NAND(106, 1081)
1180 = NAND(113, 1084)
1183 = NAND(120, 1087)
1186 = NAND(127, 1090)
1189 = NAND(134, 1093)
1192 = NAND(141, 1096)
1195 = NAND(148, 1099)
1198 = NAND(155, 1102)
1201 = NAND(162, 1105)
1204 = NAND(169, 1108)
1207 = NAND(176, 1111)
1210 = NAND(183, 1114)
1213 = NAND(190, 1117)
1216 = NAND(197, 1120)
1219 = NAND(204, 1123)
1222 = NAND(211, 1126)
1225 = NAND(218, 1129)
1228 = NAND(1, 1132)
1229 = NAND(1036, 1132)
1230 = NAND(8, 1135)
1231 = NAND(1039, 1135)
1232 = NAND(15, 1138)
1233 = NAND(1042, 1138)
1234 = NAND(22, 1141)
1235 = NAND(1045, 1141)
1236 = NAND(29, 1144)
1237 = NAND(1048, 1144)
1238 = NAND(36, 1147)
1239 = NAND(1051, 1147)
1240 = NAND(43, 1150)
1241 = NAND(1054, 1150)
1242 = NAND(50, 1153)
1243 = NAND(1057, 1153)
1244 = NAND(57, 1156)
1245 = NAND(1060, 1156)
1246 = NAND(64, 1159)
1247 = NAND(1063, 1159)
1248 = NAND(71, 1162)
1249 = NAND(1066, 1162)
1250 = NAND(78, 1165)
1251 = NAND(1069, 1165)
1252 = NAND(85, 1168)
1253 = NAND(1072, 1168)
1254 = NAND(92, 1171)
1255 = NAND(1075, 1171)
1256 = NAND(99, 1174)
1257 = NAND(1078, 1174)
1258 = NAND(106, 1177)
1259 = NAND(1081, 1177)
1260 = NAND(113, 1180)
1261 = NAND(1084, 1180)
1262 = NAND(120, 1183)
1263 = NAND(1087, 1183)
1264 = NAND(127, 1186)
1265 = NAND(1090, 1186)
1266 = NAND(134, 1189)
1267 = NAND(1093, 1189)
1268 = NAND(141, 1192)
1269 = NAND(1096, 1192)
1270 = NAND(148, 1195)
1271 = NAND(1099, 1195)
1272 = NAND(155, 1198)
1273 = NAND(1102, 1198)
1274 = NAND(162, 1201)
1275 = NAND(1105, 1201)
1276 = NAND(169, 1204)
1277 = NAND(1108, 1204)
1278 = NAND(176, 1207)
1279 = NAND(1111, 1207)
1280 = NAND(183, 1210)
1281 = NAND(1114, 1210)
1282 = NAND(190, 1213)
1283 = NAND(1117, 1213)
1284 = NAND(197, 1216)
1285 = NAND(1120, 1216)
1286 = NAND(204, 1219)
1287 = NAND(1123, 1219)
1288 = NAND(211, 1222)
1289 = NAND(1126, 1222)
1290 = NAND(218, 1225)
1291 = NAND(1129, 1225)
1292 = NAND(1228, 1229)
1293 = NAND(1230, 1231)
1294 = NAND(1232, 1233)
1295 = NAND(1234, 1235)
1296 = NAND(1236, 1237)
1297 = NAND(1238, 1239)
1298 = NAND(1240, 1241)
1299 = NAND(1242, 1243)
1300 = NAND(1244, 1245)
1301 = NAND(1246, 1247)
1302 = NAND(1248, 1249)
1303 = NAND(1250, 1251)
1304 = NAND(1252, 1253)
1305 = NAND(1254, 1255)
1306 = NAND(1256, 1257)
1307 = NAND(1258, 1259)
1308 = NAND(1260, 1261)
1309 = NAND(1262, 1263)
1310 = NAND(1264, 1265)
1311 = NAND(1266, 1267)
1312 = NAND(1268, 1269)
1313 = NAND(1270, 1271)
1314 = NAND(1272, 1273)
1315 = NAND(1274, 1275)
1316 = NAND(1276, 1277)
1317 = NAND(1278, 1279)
1318 = NAND(1280, 1281)
1319 = NAND(1282, 1283)
1320 = NAND(1284, 1285)
1321 = NAND(1286, 1287)
1322 = NAND(1288, 1289)
1323 = NAND(1290, 1291)
1324 = BUFF(1292)
1325 = BUFF(1293)
1326 = BUFF(1294)
1327 = BUFF(1295)
1328 = BUFF(1296)
1329 = BUFF(1297)
1330 = BUFF(1298)
1331 = BUFF(1299)
1332 = BUFF(1300)
1333 = BUFF(1301)
1334 = BUFF(1302)
1335 = BUFF(1303)
1336 = BUFF(1304)
1337 = BUFF(1305)
1338 = BUFF(1306)
1339 = BUFF(1307)
1340 = BUFF(1308)
1341 = BUFF(1309)
1342 = BUFF(1310)
1343 = BUFF(1311)
1344 = BUFF(1312)
1345 = BUFF(1313)
1346 = BUFF(1314)
1347 = BUFF(1315)
1348 = BUFF(1316)
1349 = BUFF(1317)
1350 = BUFF(1318)
1351 = BUFF(1319)
1352 = BUFF(1320)
1353 = BUFF(1321)
1354 = BUFF(1322)
1355 = BUFF(1323)

17
ISCAS85/c17.bench
View File

@ -1,17 +0,0 @@
# c17
INPUT(1)
INPUT(2)
INPUT(3)
INPUT(6)
INPUT(7)
OUTPUT(22)
OUTPUT(23)
10 = NAND(1, 3)
11 = NAND(3, 6)
16 = NAND(2, 11)
19 = NAND(11, 7)
22 = NAND(10, 16)
23 = NAND(16, 19)

0
ISCAS85/c17.test
View File

942
ISCAS85/c1908.bench
View File

@ -1,942 +0,0 @@
# c1908
INPUT(1)
INPUT(4)
INPUT(7)
INPUT(10)
INPUT(13)
INPUT(16)
INPUT(19)
INPUT(22)
INPUT(25)
INPUT(28)
INPUT(31)
INPUT(34)
INPUT(37)
INPUT(40)
INPUT(43)
INPUT(46)
INPUT(49)
INPUT(53)
INPUT(56)
INPUT(60)
INPUT(63)
INPUT(66)
INPUT(69)
INPUT(72)
INPUT(76)
INPUT(79)
INPUT(82)
INPUT(85)
INPUT(88)
INPUT(91)
INPUT(94)
INPUT(99)
INPUT(104)
OUTPUT(2753)
OUTPUT(2754)
OUTPUT(2755)
OUTPUT(2756)
OUTPUT(2762)
OUTPUT(2767)
OUTPUT(2768)
OUTPUT(2779)
OUTPUT(2780)
OUTPUT(2781)
OUTPUT(2782)
OUTPUT(2783)
OUTPUT(2784)
OUTPUT(2785)
OUTPUT(2786)
OUTPUT(2787)
OUTPUT(2811)
OUTPUT(2886)
OUTPUT(2887)
OUTPUT(2888)
OUTPUT(2889)
OUTPUT(2890)
OUTPUT(2891)
OUTPUT(2892)
OUTPUT(2899)
190 = NOT(1)
194 = NOT(4)
197 = NOT(7)
201 = NOT(10)
206 = NOT(13)
209 = NOT(16)
212 = NOT(19)
216 = NOT(22)
220 = NOT(25)
225 = NOT(28)
229 = NOT(31)
232 = NOT(34)
235 = NOT(37)
239 = NOT(40)
243 = NOT(43)
247 = NOT(46)
251 = NAND(63, 88)
252 = NAND(66, 91)
253 = NOT(72)
256 = NOT(72)
257 = BUFF(69)
260 = BUFF(69)
263 = NOT(76)
266 = NOT(79)
269 = NOT(82)
272 = NOT(85)
275 = NOT(104)
276 = NOT(104)
277 = NOT(88)
280 = NOT(91)
283 = BUFF(94)
290 = NOT(94)
297 = BUFF(94)
300 = NOT(94)
303 = BUFF(99)
306 = NOT(99)
313 = NOT(99)
316 = BUFF(104)
319 = NOT(104)
326 = BUFF(104)
331 = BUFF(104)
338 = NOT(104)
343 = BUFF(1)
346 = BUFF(4)
349 = BUFF(7)
352 = BUFF(10)
355 = BUFF(13)
358 = BUFF(16)
361 = BUFF(19)
364 = BUFF(22)
367 = BUFF(25)
370 = BUFF(28)
373 = BUFF(31)
376 = BUFF(34)
379 = BUFF(37)
382 = BUFF(40)
385 = BUFF(43)
388 = BUFF(46)
534 = NOT(343)
535 = NOT(346)
536 = NOT(349)
537 = NOT(352)
538 = NOT(355)
539 = NOT(358)
540 = NOT(361)
541 = NOT(364)
542 = NOT(367)
543 = NOT(370)
544 = NOT(373)
545 = NOT(376)
546 = NOT(379)
547 = NOT(382)
548 = NOT(385)
549 = NOT(388)
550 = NAND(306, 331)
551 = NAND(306, 331)
552 = NAND(306, 331)
553 = NAND(306, 331)
554 = NAND(306, 331)
555 = NAND(306, 331)
556 = BUFF(190)
559 = BUFF(194)
562 = BUFF(206)
565 = BUFF(209)
568 = BUFF(225)
571 = BUFF(243)
574 = AND(63, 319)
577 = BUFF(220)
580 = BUFF(229)
583 = BUFF(232)
586 = AND(66, 319)
589 = BUFF(239)
592 = AND(49, 253, 319)
595 = BUFF(247)
598 = BUFF(239)
601 = NAND(326, 277)
602 = NAND(326, 280)
603 = NAND(260, 72)
608 = NAND(260, 300)
612 = NAND(256, 300)
616 = BUFF(201)
619 = BUFF(216)
622 = BUFF(220)
625 = BUFF(239)
628 = BUFF(190)
631 = BUFF(190)
634 = BUFF(194)
637 = BUFF(229)
640 = BUFF(197)
643 = AND(56, 257, 319)
646 = BUFF(232)
649 = BUFF(201)
652 = BUFF(235)
655 = AND(60, 257, 319)
658 = BUFF(263)
661 = BUFF(263)
664 = BUFF(266)
667 = BUFF(266)
670 = BUFF(269)
673 = BUFF(269)
676 = BUFF(272)
679 = BUFF(272)
682 = AND(251, 316)
685 = AND(252, 316)
688 = BUFF(197)
691 = BUFF(197)
694 = BUFF(212)
697 = BUFF(212)
700 = BUFF(247)
703 = BUFF(247)
706 = BUFF(235)
709 = BUFF(235)
712 = BUFF(201)
715 = BUFF(201)
718 = BUFF(206)
721 = BUFF(216)
724 = AND(53, 253, 319)
727 = BUFF(243)
730 = BUFF(220)
733 = BUFF(220)
736 = BUFF(209)
739 = BUFF(216)
742 = BUFF(225)
745 = BUFF(243)
748 = BUFF(212)
751 = BUFF(225)
886 = NOT(682)
887 = NOT(685)
888 = NOT(616)
889 = NOT(619)
890 = NOT(622)
891 = NOT(625)
892 = NOT(631)
893 = NOT(643)
894 = NOT(649)
895 = NOT(652)
896 = NOT(655)
897 = AND(49, 612)
898 = AND(56, 608)
899 = NAND(53, 612)
903 = NAND(60, 608)
907 = NAND(49, 612)
910 = NAND(56, 608)
913 = NOT(661)
914 = NOT(658)
915 = NOT(667)
916 = NOT(664)
917 = NOT(673)
918 = NOT(670)
919 = NOT(679)
920 = NOT(676)
921 = NAND(277, 297, 326, 603)
922 = NAND(280, 297, 326, 603)
923 = NAND(303, 338, 603)
926 = AND(303, 338, 603)
935 = BUFF(556)
938 = NOT(688)
939 = BUFF(556)
942 = NOT(691)
943 = BUFF(562)
946 = NOT(694)
947 = BUFF(562)
950 = NOT(697)
951 = BUFF(568)
954 = NOT(700)
955 = BUFF(568)
958 = NOT(703)
959 = BUFF(574)
962 = BUFF(574)
965 = BUFF(580)
968 = NOT(706)
969 = BUFF(580)
972 = NOT(709)
973 = BUFF(586)
976 = NOT(712)
977 = BUFF(586)
980 = NOT(715)
981 = BUFF(592)
984 = NOT(628)
985 = BUFF(592)
988 = NOT(718)
989 = NOT(721)
990 = NOT(634)
991 = NOT(724)
992 = NOT(727)
993 = NOT(637)
994 = BUFF(595)
997 = NOT(730)
998 = BUFF(595)
1001 = NOT(733)
1002 = NOT(736)
1003 = NOT(739)
1004 = NOT(640)
1005 = NOT(742)
1006 = NOT(745)
1007 = NOT(646)
1008 = NOT(748)
1009 = NOT(751)
1010 = BUFF(559)
1013 = BUFF(559)
1016 = BUFF(565)
1019 = BUFF(565)
1022 = BUFF(571)
1025 = BUFF(571)
1028 = BUFF(577)
1031 = BUFF(577)
1034 = BUFF(583)
1037 = BUFF(583)
1040 = BUFF(589)
1043 = BUFF(589)
1046 = BUFF(598)
1049 = BUFF(598)
1054 = NAND(619, 888)
1055 = NAND(616, 889)
1063 = NAND(625, 890)
1064 = NAND(622, 891)
1067 = NAND(655, 895)
1068 = NAND(652, 896)
1119 = NAND(721, 988)
1120 = NAND(718, 989)
1121 = NAND(727, 991)
1122 = NAND(724, 992)
1128 = NAND(739, 1002)
1129 = NAND(736, 1003)
1130 = NAND(745, 1005)
1131 = NAND(742, 1006)
1132 = NAND(751, 1008)
1133 = NAND(748, 1009)
1148 = NOT(939)
1149 = NOT(935)
1150 = NAND(1054, 1055)
1151 = NOT(943)
1152 = NOT(947)
1153 = NOT(955)
1154 = NOT(951)
1155 = NOT(962)
1156 = NOT(969)
1157 = NOT(977)
1158 = NAND(1063, 1064)
1159 = NOT(985)
1160 = NAND(985, 892)
1161 = NOT(998)
1162 = NAND(1067, 1068)
1163 = NOT(899)
1164 = BUFF(899)
1167 = NOT(903)
1168 = BUFF(903)
1171 = NAND(921, 923)
1188 = NAND(922, 923)
1205 = NOT(1010)
1206 = NAND(1010, 938)
1207 = NOT(1013)
1208 = NAND(1013, 942)
1209 = NOT(1016)
1210 = NAND(1016, 946)
1211 = NOT(1019)
1212 = NAND(1019, 950)
1213 = NOT(1022)
1214 = NAND(1022, 954)
1215 = NOT(1025)
1216 = NAND(1025, 958)
1217 = NOT(1028)
1218 = NOT(959)
1219 = NOT(1031)
1220 = NOT(1034)
1221 = NAND(1034, 968)
1222 = NOT(965)
1223 = NOT(1037)
1224 = NAND(1037, 972)
1225 = NOT(1040)
1226 = NAND(1040, 976)
1227 = NOT(973)
1228 = NOT(1043)
1229 = NAND(1043, 980)
1230 = NOT(981)
1231 = NAND(981, 984)
1232 = NAND(1119, 1120)
1235 = NAND(1121, 1122)
1238 = NOT(1046)
1239 = NAND(1046, 997)
1240 = NOT(994)
1241 = NOT(1049)
1242 = NAND(1049, 1001)
1243 = NAND(1128, 1129)
1246 = NAND(1130, 1131)
1249 = NAND(1132, 1133)
1252 = BUFF(907)
1255 = BUFF(907)
1258 = BUFF(910)
1261 = BUFF(910)
1264 = NOT(1150)
1267 = NAND(631, 1159)
1309 = NAND(688, 1205)
1310 = NAND(691, 1207)
1311 = NAND(694, 1209)
1312 = NAND(697, 1211)
1313 = NAND(700, 1213)
1314 = NAND(703, 1215)
1315 = NAND(706, 1220)
1316 = NAND(709, 1223)
1317 = NAND(712, 1225)
1318 = NAND(715, 1228)
1319 = NOT(1158)
1322 = NAND(628, 1230)
1327 = NAND(730, 1238)
1328 = NAND(733, 1241)
1334 = NOT(1162)
1344 = NAND(1267, 1160)
1345 = NAND(1249, 894)
1346 = NOT(1249)
1348 = NOT(1255)
1349 = NOT(1252)
1350 = NOT(1261)
1351 = NOT(1258)
1352 = NAND(1309, 1206)
1355 = NAND(1310, 1208)
1358 = NAND(1311, 1210)
1361 = NAND(1312, 1212)
1364 = NAND(1313, 1214)
1367 = NAND(1314, 1216)
1370 = NAND(1315, 1221)
1373 = NAND(1316, 1224)
1376 = NAND(1317, 1226)
1379 = NAND(1318, 1229)
1383 = NAND(1322, 1231)
1386 = NOT(1232)
1387 = NAND(1232, 990)
1388 = NOT(1235)
1389 = NAND(1235, 993)
1390 = NAND(1327, 1239)
1393 = NAND(1328, 1242)
1396 = NOT(1243)
1397 = NAND(1243, 1004)
1398 = NOT(1246)
1399 = NAND(1246, 1007)
1409 = NOT(1319)
1412 = NAND(649, 1346)
1413 = NOT(1334)
1416 = BUFF(1264)
1419 = BUFF(1264)
1433 = NAND(634, 1386)
1434 = NAND(637, 1388)
1438 = NAND(640, 1396)
1439 = NAND(646, 1398)
1440 = NOT(1344)
1443 = NAND(1355, 1148)
1444 = NOT(1355)
1445 = NAND(1352, 1149)
1446 = NOT(1352)
1447 = NAND(1358, 1151)
1448 = NOT(1358)
1451 = NAND(1361, 1152)
1452 = NOT(1361)
1453 = NAND(1367, 1153)
1454 = NOT(1367)
1455 = NAND(1364, 1154)
1456 = NOT(1364)
1457 = NAND(1373, 1156)
1458 = NOT(1373)
1459 = NAND(1379, 1157)
1460 = NOT(1379)
1461 = NOT(1383)
1462 = NAND(1393, 1161)
1463 = NOT(1393)
1464 = NAND(1345, 1412)
1468 = NOT(1370)
1469 = NAND(1370, 1222)
1470 = NOT(1376)
1471 = NAND(1376, 1227)
1472 = NAND(1387, 1433)
1475 = NOT(1390)
1476 = NAND(1390, 1240)
1478 = NAND(1389, 1434)
1481 = NAND(1399, 1439)
1484 = NAND(1397, 1438)
1487 = NAND(939, 1444)
1488 = NAND(935, 1446)
1489 = NAND(943, 1448)
1490 = NOT(1419)
1491 = NOT(1416)
1492 = NAND(947, 1452)
1493 = NAND(955, 1454)
1494 = NAND(951, 1456)
1495 = NAND(969, 1458)
1496 = NAND(977, 1460)
1498 = NAND(998, 1463)
1499 = NOT(1440)
1500 = NAND(965, 1468)
1501 = NAND(973, 1470)
1504 = NAND(994, 1475)
1510 = NOT(1464)
1513 = NAND(1443, 1487)
1514 = NAND(1445, 1488)
1517 = NAND(1447, 1489)
1520 = NAND(1451, 1492)
1521 = NAND(1453, 1493)
1522 = NAND(1455, 1494)
1526 = NAND(1457, 1495)
1527 = NAND(1459, 1496)
1528 = NOT(1472)
1529 = NAND(1462, 1498)
1530 = NOT(1478)
1531 = NOT(1481)
1532 = NOT(1484)
1534 = NAND(1471, 1501)
1537 = NAND(1469, 1500)
1540 = NAND(1476, 1504)
1546 = NOT(1513)
1554 = NOT(1521)
1557 = NOT(1526)
1561 = NOT(1520)
1567 = NAND(1484, 1531)
1568 = NAND(1481, 1532)
1569 = NOT(1510)
1571 = NOT(1527)
1576 = NOT(1529)
1588 = BUFF(1522)
1591 = NOT(1534)
1593 = NOT(1537)
1594 = NAND(1540, 1530)
1595 = NOT(1540)
1596 = NAND(1567, 1568)
1600 = BUFF(1517)
1603 = BUFF(1517)
1606 = BUFF(1522)
1609 = BUFF(1522)
1612 = BUFF(1514)
1615 = BUFF(1514)
1620 = BUFF(1557)
1623 = BUFF(1554)
1635 = NOT(1571)
1636 = NAND(1478, 1595)
1638 = NAND(1576, 1569)
1639 = NOT(1576)
1640 = BUFF(1561)
1643 = BUFF(1561)
1647 = BUFF(1546)
1651 = BUFF(1546)
1658 = BUFF(1554)
1661 = BUFF(1557)
1664 = BUFF(1557)
1671 = NAND(1596, 893)
1672 = NOT(1596)
1675 = NOT(1600)
1677 = NOT(1603)
1678 = NAND(1606, 1217)
1679 = NOT(1606)
1680 = NAND(1609, 1219)
1681 = NOT(1609)
1682 = NOT(1612)
1683 = NOT(1615)
1685 = NAND(1594, 1636)
1688 = NAND(1510, 1639)
1697 = BUFF(1588)
1701 = BUFF(1588)
1706 = NAND(643, 1672)
1707 = NOT(1643)
1708 = NAND(1647, 1675)
1709 = NOT(1647)
1710 = NAND(1651, 1677)
1711 = NOT(1651)
1712 = NAND(1028, 1679)
1713 = NAND(1031, 1681)
1714 = BUFF(1620)
1717 = BUFF(1620)
1720 = NAND(1658, 1593)
1721 = NOT(1658)
1723 = NAND(1638, 1688)
1727 = NOT(1661)
1728 = NOT(1640)
1730 = NOT(1664)
1731 = BUFF(1623)
1734 = BUFF(1623)
1740 = NAND(1685, 1528)
1741 = NOT(1685)
1742 = NAND(1671, 1706)
1746 = NAND(1600, 1709)
1747 = NAND(1603, 1711)
1748 = NAND(1678, 1712)
1751 = NAND(1680, 1713)
1759 = NAND(1537, 1721)
1761 = NOT(1697)
1762 = NAND(1697, 1727)
1763 = NOT(1701)
1764 = NAND(1701, 1730)
1768 = NOT(1717)
1769 = NAND(1472, 1741)
1772 = NAND(1723, 1413)
1773 = NOT(1723)
1774 = NAND(1708, 1746)
1777 = NAND(1710, 1747)
1783 = NOT(1731)
1784 = NAND(1731, 1682)
1785 = NOT(1714)
1786 = NOT(1734)
1787 = NAND(1734, 1683)
1788 = NAND(1720, 1759)
1791 = NAND(1661, 1761)
1792 = NAND(1664, 1763)
1795 = NAND(1751, 1155)
1796 = NOT(1751)
1798 = NAND(1740, 1769)
1801 = NAND(1334, 1773)
1802 = NAND(1742, 290)
1807 = NOT(1748)
1808 = NAND(1748, 1218)
1809 = NAND(1612, 1783)
1810 = NAND(1615, 1786)
1812 = NAND(1791, 1762)
1815 = NAND(1792, 1764)
1818 = BUFF(1742)
1821 = NAND(1777, 1490)
1822 = NOT(1777)
1823 = NAND(1774, 1491)
1824 = NOT(1774)
1825 = NAND(962, 1796)
1826 = NAND(1788, 1409)
1827 = NOT(1788)
1830 = NAND(1772, 1801)
1837 = NAND(959, 1807)
1838 = NAND(1809, 1784)
1841 = NAND(1810, 1787)
1848 = NAND(1419, 1822)
1849 = NAND(1416, 1824)
1850 = NAND(1795, 1825)
1852 = NAND(1319, 1827)
1855 = NAND(1815, 1707)
1856 = NOT(1815)
1857 = NOT(1818)
1858 = NAND(1798, 290)
1864 = NOT(1812)
1865 = NAND(1812, 1728)
1866 = BUFF(1798)
1869 = BUFF(1802)
1872 = BUFF(1802)
1875 = NAND(1808, 1837)
1878 = NAND(1821, 1848)
1879 = NAND(1823, 1849)
1882 = NAND(1841, 1768)
1883 = NOT(1841)
1884 = NAND(1826, 1852)
1885 = NAND(1643, 1856)
1889 = NAND(1830, 290)
1895 = NOT(1838)
1896 = NAND(1838, 1785)
1897 = NAND(1640, 1864)
1898 = NOT(1850)
1902 = BUFF(1830)
1910 = NOT(1878)
1911 = NAND(1717, 1883)
1912 = NOT(1884)
1913 = NAND(1855, 1885)
1915 = NOT(1866)
1919 = NAND(1872, 919)
1920 = NOT(1872)
1921 = NAND(1869, 920)
1922 = NOT(1869)
1923 = NOT(1875)
1924 = NAND(1714, 1895)
1927 = BUFF(1858)
1930 = BUFF(1858)
1933 = NAND(1865, 1897)
1936 = NAND(1882, 1911)
1937 = NOT(1898)
1938 = NOT(1902)
1941 = NAND(679, 1920)
1942 = NAND(676, 1922)
1944 = BUFF(1879)
1947 = NOT(1913)
1950 = BUFF(1889)
1953 = BUFF(1889)
1958 = BUFF(1879)
1961 = NAND(1896, 1924)
1965 = AND(1910, 601)
1968 = AND(602, 1912)
1975 = NAND(1930, 917)
1976 = NOT(1930)
1977 = NAND(1927, 918)
1978 = NOT(1927)
1979 = NAND(1919, 1941)
1980 = NAND(1921, 1942)
1985 = NOT(1933)
1987 = NOT(1936)
1999 = NOT(1944)
2000 = NAND(1944, 1937)
2002 = NOT(1947)
2003 = NAND(1947, 1499)
2004 = NAND(1953, 1350)
2005 = NOT(1953)
2006 = NAND(1950, 1351)
2007 = NOT(1950)
2008 = NAND(673, 1976)
2009 = NAND(670, 1978)
2012 = NOT(1979)
2013 = NOT(1958)
2014 = NAND(1958, 1923)
2015 = NOT(1961)
2016 = NAND(1961, 1635)
2018 = NOT(1965)
2019 = NOT(1968)
2020 = NAND(1898, 1999)
2021 = NOT(1987)
2022 = NAND(1987, 1591)
2023 = NAND(1440, 2002)
2024 = NAND(1261, 2005)
2025 = NAND(1258, 2007)
2026 = NAND(1975, 2008)
2027 = NAND(1977, 2009)
2030 = NOT(1980)
2033 = BUFF(1980)
2036 = NAND(1875, 2013)
2037 = NAND(1571, 2015)
2038 = NAND(2020, 2000)
2039 = NAND(1534, 2021)
2040 = NAND(2023, 2003)
2041 = NAND(2004, 2024)
2042 = NAND(2006, 2025)
2047 = NOT(2026)
2052 = NAND(2036, 2014)
2055 = NAND(2037, 2016)
2060 = NOT(2038)
2061 = NAND(2039, 2022)
2062 = NAND(2040, 290)
2067 = NOT(2041)
2068 = NOT(2027)
2071 = BUFF(2027)
2076 = NOT(2052)
2077 = NOT(2055)
2078 = NAND(2060, 290)
2081 = NAND(2061, 290)
2086 = NOT(2042)
2089 = BUFF(2042)
2104 = AND(2030, 2068)
2119 = AND(2033, 2068)
2129 = AND(2030, 2071)
2143 = AND(2033, 2071)
2148 = BUFF(2062)
2151 = BUFF(2062)
2196 = BUFF(2078)
2199 = BUFF(2078)
2202 = BUFF(2081)
2205 = BUFF(2081)
2214 = NAND(2151, 915)
2215 = NOT(2151)
2216 = NAND(2148, 916)
2217 = NOT(2148)
2222 = NAND(2199, 1348)
2223 = NOT(2199)
2224 = NAND(2196, 1349)
2225 = NOT(2196)
2226 = NAND(2205, 913)
2227 = NOT(2205)
2228 = NAND(2202, 914)
2229 = NOT(2202)
2230 = NAND(667, 2215)
2231 = NAND(664, 2217)
2232 = NAND(1255, 2223)
2233 = NAND(1252, 2225)
2234 = NAND(661, 2227)
2235 = NAND(658, 2229)
2236 = NAND(2214, 2230)
2237 = NAND(2216, 2231)
2240 = NAND(2222, 2232)
2241 = NAND(2224, 2233)
2244 = NAND(2226, 2234)
2245 = NAND(2228, 2235)
2250 = NOT(2236)
2253 = NOT(2240)
2256 = NOT(2244)
2257 = NOT(2237)
2260 = BUFF(2237)
2263 = NOT(2241)
2266 = AND(1164, 2241)
2269 = NOT(2245)
2272 = AND(1168, 2245)
2279 = NAND(2067, 2012, 2047, 2250, 899, 2256, 2253, 903)
2286 = BUFF(2266)
2297 = BUFF(2266)
2315 = BUFF(2272)
2326 = BUFF(2272)
2340 = AND(2086, 2257)
2353 = AND(2089, 2257)
2361 = AND(2086, 2260)
2375 = AND(2089, 2260)
2384 = AND(338, 2279, 313, 313)
2385 = AND(1163, 2263)
2386 = AND(1164, 2263)
2426 = AND(1167, 2269)
2427 = AND(1168, 2269)
2537 = NAND(2286, 2315, 2361, 2104, 1171)
2540 = NAND(2286, 2315, 2340, 2129, 1171)
2543 = NAND(2286, 2315, 2340, 2119, 1171)
2546 = NAND(2286, 2315, 2353, 2104, 1171)
2549 = NAND(2297, 2315, 2375, 2119, 1188)
2552 = NAND(2297, 2326, 2361, 2143, 1188)
2555 = NAND(2297, 2326, 2375, 2129, 1188)
2558 = AND(2286, 2315, 2361, 2104, 1171)
2561 = AND(2286, 2315, 2340, 2129, 1171)
2564 = AND(2286, 2315, 2340, 2119, 1171)
2567 = AND(2286, 2315, 2353, 2104, 1171)
2570 = AND(2297, 2315, 2375, 2119, 1188)
2573 = AND(2297, 2326, 2361, 2143, 1188)
2576 = AND(2297, 2326, 2375, 2129, 1188)
2594 = NAND(2286, 2427, 2361, 2129, 1171)
2597 = NAND(2297, 2427, 2361, 2119, 1171)
2600 = NAND(2297, 2427, 2375, 2104, 1171)
2603 = NAND(2297, 2427, 2340, 2143, 1171)
2606 = NAND(2297, 2427, 2353, 2129, 1188)
2611 = NAND(2386, 2326, 2361, 2129, 1188)
2614 = NAND(2386, 2326, 2361, 2119, 1188)
2617 = NAND(2386, 2326, 2375, 2104, 1188)
2620 = NAND(2386, 2326, 2353, 2129, 1188)
2627 = NAND(2297, 2427, 2340, 2104, 926)
2628 = NAND(2386, 2326, 2340, 2104, 926)
2629 = NAND(2386, 2427, 2361, 2104, 926)
2630 = NAND(2386, 2427, 2340, 2129, 926)
2631 = NAND(2386, 2427, 2340, 2119, 926)
2632 = NAND(2386, 2427, 2353, 2104, 926)
2633 = NAND(2386, 2426, 2340, 2104, 926)
2634 = NAND(2385, 2427, 2340, 2104, 926)
2639 = AND(2286, 2427, 2361, 2129, 1171)
2642 = AND(2297, 2427, 2361, 2119, 1171)
2645 = AND(2297, 2427, 2375, 2104, 1171)
2648 = AND(2297, 2427, 2340, 2143, 1171)
2651 = AND(2297, 2427, 2353, 2129, 1188)
2655 = AND(2386, 2326, 2361, 2129, 1188)
2658 = AND(2386, 2326, 2361, 2119, 1188)
2661 = AND(2386, 2326, 2375, 2104, 1188)
2664 = AND(2386, 2326, 2353, 2129, 1188)
2669 = NAND(2558, 534)
2670 = NOT(2558)
2671 = NAND(2561, 535)
2672 = NOT(2561)
2673 = NAND(2564, 536)
2674 = NOT(2564)
2675 = NAND(2567, 537)
2676 = NOT(2567)
2682 = NAND(2570, 543)
2683 = NOT(2570)
2688 = NAND(2573, 548)
2689 = NOT(2573)
2690 = NAND(2576, 549)
2691 = NOT(2576)
2710 = AND(2627, 2628, 2629, 2630, 2631, 2632, 2633, 2634)
2720 = NAND(343, 2670)
2721 = NAND(346, 2672)
2722 = NAND(349, 2674)
2723 = NAND(352, 2676)
2724 = NAND(2639, 538)
2725 = NOT(2639)
2726 = NAND(2642, 539)
2727 = NOT(2642)
2728 = NAND(2645, 540)
2729 = NOT(2645)
2730 = NAND(2648, 541)
2731 = NOT(2648)
2732 = NAND(2651, 542)
2733 = NOT(2651)
2734 = NAND(370, 2683)
2735 = NAND(2655, 544)
2736 = NOT(2655)
2737 = NAND(2658, 545)
2738 = NOT(2658)
2739 = NAND(2661, 546)
2740 = NOT(2661)
2741 = NAND(2664, 547)
2742 = NOT(2664)
2743 = NAND(385, 2689)
2744 = NAND(388, 2691)
2745 = NAND(2537, 2540, 2543, 2546, 2594, 2597, 2600, 2603)
2746 = NAND(2606, 2549, 2611, 2614, 2617, 2620, 2552, 2555)
2747 = AND(2537, 2540, 2543, 2546, 2594, 2597, 2600, 2603)
2750 = AND(2606, 2549, 2611, 2614, 2617, 2620, 2552, 2555)
2753 = NAND(2669, 2720)
2754 = NAND(2671, 2721)
2755 = NAND(2673, 2722)
2756 = NAND(2675, 2723)
2757 = NAND(355, 2725)
2758 = NAND(358, 2727)
2759 = NAND(361, 2729)
2760 = NAND(364, 2731)
2761 = NAND(367, 2733)
2762 = NAND(2682, 2734)
2763 = NAND(373, 2736)
2764 = NAND(376, 2738)
2765 = NAND(379, 2740)
2766 = NAND(382, 2742)
2767 = NAND(2688, 2743)
2768 = NAND(2690, 2744)
2773 = AND(2745, 275)
2776 = AND(2746, 276)
2779 = NAND(2724, 2757)
2780 = NAND(2726, 2758)
2781 = NAND(2728, 2759)
2782 = NAND(2730, 2760)
2783 = NAND(2732, 2761)
2784 = NAND(2735, 2763)
2785 = NAND(2737, 2764)
2786 = NAND(2739, 2765)
2787 = NAND(2741, 2766)
2788 = AND(2747, 2750, 2710)
2789 = NAND(2747, 2750)
2800 = AND(338, 2279, 99, 2788)
2807 = NAND(2773, 2018)
2808 = NOT(2773)
2809 = NAND(2776, 2019)
2810 = NOT(2776)
2811 = NOR(2384, 2800)
2812 = AND(897, 283, 2789)
2815 = AND(76, 283, 2789)
2818 = AND(82, 283, 2789)
2821 = AND(85, 283, 2789)
2824 = AND(898, 283, 2789)
2827 = NAND(1965, 2808)
2828 = NAND(1968, 2810)
2829 = AND(79, 283, 2789)
2843 = NAND(2807, 2827)
2846 = NAND(2809, 2828)
2850 = NAND(2812, 2076)
2851 = NAND(2815, 2077)
2852 = NAND(2818, 1915)
2853 = NAND(2821, 1857)
2854 = NAND(2824, 1938)
2857 = NOT(2812)
2858 = NOT(2815)
2859 = NOT(2818)
2860 = NOT(2821)
2861 = NOT(2824)
2862 = NOT(2829)
2863 = NAND(2829, 1985)
2866 = NAND(2052, 2857)
2867 = NAND(2055, 2858)
2868 = NAND(1866, 2859)
2869 = NAND(1818, 2860)
2870 = NAND(1902, 2861)
2871 = NAND(2843, 886)
2872 = NOT(2843)
2873 = NAND(2846, 887)
2874 = NOT(2846)
2875 = NAND(1933, 2862)
2876 = NAND(2866, 2850)
2877 = NAND(2867, 2851)
2878 = NAND(2868, 2852)
2879 = NAND(2869, 2853)
2880 = NAND(2870, 2854)
2881 = NAND(682, 2872)
2882 = NAND(685, 2874)
2883 = NAND(2875, 2863)
2886 = AND(2876, 550)
2887 = AND(551, 2877)
2888 = AND(553, 2878)
2889 = AND(2879, 554)
2890 = AND(555, 2880)
2891 = NAND(2871, 2881)
2892 = NAND(2873, 2882)
2895 = NAND(2883, 1461)
2896 = NOT(2883)
2897 = NAND(1383, 2896)
2898 = NAND(2895, 2897)
2899 = AND(2898, 552)

1570
ISCAS85/c2670.bench
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0
ISCAS85/c2670.test
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1745
ISCAS85/c3540.bench
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207
ISCAS85/c432.bench
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@ -1,207 +0,0 @@
# c432
INPUT(1)
INPUT(4)
INPUT(8)
INPUT(11)
INPUT(14)
INPUT(17)
INPUT(21)
INPUT(24)
INPUT(27)
INPUT(30)
INPUT(34)
INPUT(37)
INPUT(40)
INPUT(43)
INPUT(47)
INPUT(50)
INPUT(53)
INPUT(56)
INPUT(60)
INPUT(63)
INPUT(66)
INPUT(69)
INPUT(73)
INPUT(76)
INPUT(79)
INPUT(82)
INPUT(86)
INPUT(89)
INPUT(92)
INPUT(95)
INPUT(99)
INPUT(102)
INPUT(105)
INPUT(108)
INPUT(112)
INPUT(115)
OUTPUT(223)
OUTPUT(329)
OUTPUT(370)
OUTPUT(421)
OUTPUT(430)
OUTPUT(431)
OUTPUT(432)
118 = NOT(1)
119 = NOT(4)
122 = NOT(11)
123 = NOT(17)
126 = NOT(24)
127 = NOT(30)
130 = NOT(37)
131 = NOT(43)
134 = NOT(50)
135 = NOT(56)
138 = NOT(63)
139 = NOT(69)
142 = NOT(76)
143 = NOT(82)
146 = NOT(89)
147 = NOT(95)
150 = NOT(102)
151 = NOT(108)
154 = NAND(118, 4)
157 = NOR(8, 119)
158 = NOR(14, 119)
159 = NAND(122, 17)
162 = NAND(126, 30)
165 = NAND(130, 43)
168 = NAND(134, 56)
171 = NAND(138, 69)
174 = NAND(142, 82)
177 = NAND(146, 95)
180 = NAND(150, 108)
183 = NOR(21, 123)
184 = NOR(27, 123)
185 = NOR(34, 127)
186 = NOR(40, 127)
187 = NOR(47, 131)
188 = NOR(53, 131)
189 = NOR(60, 135)
190 = NOR(66, 135)
191 = NOR(73, 139)
192 = NOR(79, 139)
193 = NOR(86, 143)
194 = NOR(92, 143)
195 = NOR(99, 147)
196 = NOR(105, 147)
197 = NOR(112, 151)
198 = NOR(115, 151)
199 = AND(154, 159, 162, 165, 168, 171, 174, 177, 180)
203 = NOT(199)
213 = NOT(199)
223 = NOT(199)
224 = XOR(203, 154)
227 = XOR(203, 159)
230 = XOR(203, 162)
233 = XOR(203, 165)
236 = XOR(203, 168)
239 = XOR(203, 171)
242 = NAND(1, 213)
243 = XOR(203, 174)
246 = NAND(213, 11)
247 = XOR(203, 177)
250 = NAND(213, 24)
251 = XOR(203, 180)
254 = NAND(213, 37)
255 = NAND(213, 50)
256 = NAND(213, 63)
257 = NAND(213, 76)
258 = NAND(213, 89)
259 = NAND(213, 102)
260 = NAND(224, 157)
263 = NAND(224, 158)
264 = NAND(227, 183)
267 = NAND(230, 185)
270 = NAND(233, 187)
273 = NAND(236, 189)
276 = NAND(239, 191)
279 = NAND(243, 193)
282 = NAND(247, 195)
285 = NAND(251, 197)
288 = NAND(227, 184)
289 = NAND(230, 186)
290 = NAND(233, 188)
291 = NAND(236, 190)
292 = NAND(239, 192)
293 = NAND(243, 194)
294 = NAND(247, 196)
295 = NAND(251, 198)
296 = AND(260, 264, 267, 270, 273, 276, 279, 282, 285)
300 = NOT(263)
301 = NOT(288)
302 = NOT(289)
303 = NOT(290)
304 = NOT(291)
305 = NOT(292)
306 = NOT(293)
307 = NOT(294)
308 = NOT(295)
309 = NOT(296)
319 = NOT(296)
329 = NOT(296)
330 = XOR(309, 260)
331 = XOR(309, 264)
332 = XOR(309, 267)
333 = XOR(309, 270)
334 = NAND(8, 319)
335 = XOR(309, 273)
336 = NAND(319, 21)
337 = XOR(309, 276)
338 = NAND(319, 34)
339 = XOR(309, 279)
340 = NAND(319, 47)
341 = XOR(309, 282)
342 = NAND(319, 60)
343 = XOR(309, 285)
344 = NAND(319, 73)
345 = NAND(319, 86)
346 = NAND(319, 99)
347 = NAND(319, 112)
348 = NAND(330, 300)
349 = NAND(331, 301)
350 = NAND(332, 302)
351 = NAND(333, 303)
352 = NAND(335, 304)
353 = NAND(337, 305)
354 = NAND(339, 306)
355 = NAND(341, 307)
356 = NAND(343, 308)
357 = AND(348, 349, 350, 351, 352, 353, 354, 355, 356)
360 = NOT(357)
370 = NOT(357)
371 = NAND(14, 360)
372 = NAND(360, 27)
373 = NAND(360, 40)
374 = NAND(360, 53)
375 = NAND(360, 66)
376 = NAND(360, 79)
377 = NAND(360, 92)
378 = NAND(360, 105)
379 = NAND(360, 115)
380 = NAND(4, 242, 334, 371)
381 = NAND(246, 336, 372, 17)
386 = NAND(250, 338, 373, 30)
393 = NAND(254, 340, 374, 43)
399 = NAND(255, 342, 375, 56)
404 = NAND(256, 344, 376, 69)
407 = NAND(257, 345, 377, 82)
411 = NAND(258, 346, 378, 95)
414 = NAND(259, 347, 379, 108)
415 = NOT(380)
416 = AND(381, 386, 393, 399, 404, 407, 411, 414)
417 = NOT(393)
418 = NOT(404)
419 = NOT(407)
420 = NOT(411)
421 = NOR(415, 416)
422 = NAND(386, 417)
425 = NAND(386, 393, 418, 399)
428 = NAND(399, 393, 419)
429 = NAND(386, 393, 407, 420)
430 = NAND(381, 386, 422, 399)
431 = NAND(381, 386, 425, 428)
432 = NAND(381, 422, 425, 429)

279
ISCAS85/c499.bench
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# c499
INPUT(1)
INPUT(5)
INPUT(9)
INPUT(13)
INPUT(17)
INPUT(21)
INPUT(25)
INPUT(29)
INPUT(33)
INPUT(37)
INPUT(41)
INPUT(45)
INPUT(49)
INPUT(53)
INPUT(57)
INPUT(61)
INPUT(65)
INPUT(69)
INPUT(73)
INPUT(77)
INPUT(81)
INPUT(85)
INPUT(89)
INPUT(93)
INPUT(97)
INPUT(101)
INPUT(105)
INPUT(109)
INPUT(113)
INPUT(117)
INPUT(121)
INPUT(125)
INPUT(129)
INPUT(130)
INPUT(131)
INPUT(132)
INPUT(133)
INPUT(134)
INPUT(135)
INPUT(136)
INPUT(137)
OUTPUT(724)
OUTPUT(725)
OUTPUT(726)
OUTPUT(727)
OUTPUT(728)
OUTPUT(729)
OUTPUT(730)
OUTPUT(731)
OUTPUT(732)
OUTPUT(733)
OUTPUT(734)
OUTPUT(735)
OUTPUT(736)
OUTPUT(737)
OUTPUT(738)
OUTPUT(739)
OUTPUT(740)
OUTPUT(741)
OUTPUT(742)
OUTPUT(743)
OUTPUT(744)
OUTPUT(745)
OUTPUT(746)
OUTPUT(747)
OUTPUT(748)
OUTPUT(749)
OUTPUT(750)
OUTPUT(751)
OUTPUT(752)
OUTPUT(753)
OUTPUT(754)
OUTPUT(755)
250 = XOR(1, 5)
251 = XOR(9, 13)
252 = XOR(17, 21)
253 = XOR(25, 29)
254 = XOR(33, 37)
255 = XOR(41, 45)
256 = XOR(49, 53)
257 = XOR(57, 61)
258 = XOR(65, 69)
259 = XOR(73, 77)
260 = XOR(81, 85)
261 = XOR(89, 93)
262 = XOR(97, 101)
263 = XOR(105, 109)
264 = XOR(113, 117)
265 = XOR(121, 125)
266 = AND(129, 137)
267 = AND(130, 137)
268 = AND(131, 137)
269 = AND(132, 137)
270 = AND(133, 137)
271 = AND(134, 137)
272 = AND(135, 137)
273 = AND(136, 137)
274 = XOR(1, 17)
275 = XOR(33, 49)
276 = XOR(5, 21)
277 = XOR(37, 53)
278 = XOR(9, 25)
279 = XOR(41, 57)
280 = XOR(13, 29)
281 = XOR(45, 61)
282 = XOR(65, 81)
283 = XOR(97, 113)
284 = XOR(69, 85)
285 = XOR(101, 117)
286 = XOR(73, 89)
287 = XOR(105, 121)
288 = XOR(77, 93)
289 = XOR(109, 125)
290 = XOR(250, 251)
293 = XOR(252, 253)
296 = XOR(254, 255)
299 = XOR(256, 257)
302 = XOR(258, 259)
305 = XOR(260, 261)
308 = XOR(262, 263)
311 = XOR(264, 265)
314 = XOR(274, 275)
315 = XOR(276, 277)
316 = XOR(278, 279)
317 = XOR(280, 281)
318 = XOR(282, 283)
319 = XOR(284, 285)
320 = XOR(286, 287)
321 = XOR(288, 289)
338 = XOR(290, 293)
339 = XOR(296, 299)
340 = XOR(290, 296)
341 = XOR(293, 299)
342 = XOR(302, 305)
343 = XOR(308, 311)
344 = XOR(302, 308)
345 = XOR(305, 311)
346 = XOR(266, 342)
347 = XOR(267, 343)
348 = XOR(268, 344)
349 = XOR(269, 345)
350 = XOR(270, 338)
351 = XOR(271, 339)
352 = XOR(272, 340)
353 = XOR(273, 341)
354 = XOR(314, 346)
367 = XOR(315, 347)
380 = XOR(316, 348)
393 = XOR(317, 349)
406 = XOR(318, 350)
419 = XOR(319, 351)
432 = XOR(320, 352)
445 = XOR(321, 353)
554 = NOT(354)
555 = NOT(367)
556 = NOT(380)
557 = NOT(354)
558 = NOT(367)
559 = NOT(393)
560 = NOT(354)
561 = NOT(380)
562 = NOT(393)
563 = NOT(367)
564 = NOT(380)
565 = NOT(393)
566 = NOT(419)
567 = NOT(445)
568 = NOT(419)
569 = NOT(432)
570 = NOT(406)
571 = NOT(445)
572 = NOT(406)
573 = NOT(432)
574 = NOT(406)
575 = NOT(419)
576 = NOT(432)
577 = NOT(406)
578 = NOT(419)
579 = NOT(445)
580 = NOT(406)
581 = NOT(432)
582 = NOT(445)
583 = NOT(419)
584 = NOT(432)
585 = NOT(445)
586 = NOT(367)
587 = NOT(393)
588 = NOT(367)
589 = NOT(380)
590 = NOT(354)
591 = NOT(393)
592 = NOT(354)
593 = NOT(380)
594 = AND(554, 555, 556, 393)
595 = AND(557, 558, 380, 559)
596 = AND(560, 367, 561, 562)
597 = AND(354, 563, 564, 565)
598 = AND(574, 575, 576, 445)
599 = AND(577, 578, 432, 579)
600 = AND(580, 419, 581, 582)
601 = AND(406, 583, 584, 585)
602 = OR(594, 595, 596, 597)
607 = OR(598, 599, 600, 601)
620 = AND(406, 566, 432, 567, 602)
625 = AND(406, 568, 569, 445, 602)
630 = AND(570, 419, 432, 571, 602)
635 = AND(572, 419, 573, 445, 602)
640 = AND(354, 586, 380, 587, 607)
645 = AND(354, 588, 589, 393, 607)
650 = AND(590, 367, 380, 591, 607)
655 = AND(592, 367, 593, 393, 607)
692 = AND(354, 620)
693 = AND(367, 620)
694 = AND(380, 620)
695 = AND(393, 620)
696 = AND(354, 625)
697 = AND(367, 625)
698 = AND(380, 625)
699 = AND(393, 625)
700 = AND(354, 630)
701 = AND(367, 630)
702 = AND(380, 630)
703 = AND(393, 630)
704 = AND(354, 635)
705 = AND(367, 635)
706 = AND(380, 635)
707 = AND(393, 635)
708 = AND(406, 640)
709 = AND(419, 640)
710 = AND(432, 640)
711 = AND(445, 640)
712 = AND(406, 645)
713 = AND(419, 645)
714 = AND(432, 645)
715 = AND(445, 645)
716 = AND(406, 650)
717 = AND(419, 650)
718 = AND(432, 650)
719 = AND(445, 650)
720 = AND(406, 655)
721 = AND(419, 655)
722 = AND(432, 655)
723 = AND(445, 655)
724 = XOR(1, 692)
725 = XOR(5, 693)
726 = XOR(9, 694)
727 = XOR(13, 695)
728 = XOR(17, 696)
729 = XOR(21, 697)
730 = XOR(25, 698)
731 = XOR(29, 699)
732 = XOR(33, 700)
733 = XOR(37, 701)
734 = XOR(41, 702)
735 = XOR(45, 703)
736 = XOR(49, 704)
737 = XOR(53, 705)
738 = XOR(57, 706)
739 = XOR(61, 707)
740 = XOR(65, 708)
741 = XOR(69, 709)
742 = XOR(73, 710)
743 = XOR(77, 711)
744 = XOR(81, 712)
745 = XOR(85, 713)
746 = XOR(89, 714)
747 = XOR(93, 715)
748 = XOR(97, 716)
749 = XOR(101, 717)
750 = XOR(105, 718)
751 = XOR(109, 719)
752 = XOR(113, 720)
753 = XOR(117, 721)
754 = XOR(121, 722)
755 = XOR(125, 723)

2612
ISCAS85/c5315.bench
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2484
ISCAS85/c6288.bench
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3831
ISCAS85/c7552.bench
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473
ISCAS85/c880.bench
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# c880
INPUT(1)
INPUT(8)
INPUT(13)
INPUT(17)
INPUT(26)
INPUT(29)
INPUT(36)
INPUT(42)
INPUT(51)
INPUT(55)
INPUT(59)
INPUT(68)
INPUT(72)
INPUT(73)
INPUT(74)
INPUT(75)
INPUT(80)
INPUT(85)
INPUT(86)
INPUT(87)
INPUT(88)
INPUT(89)
INPUT(90)
INPUT(91)
INPUT(96)
INPUT(101)
INPUT(106)
INPUT(111)
INPUT(116)
INPUT(121)
INPUT(126)
INPUT(130)
INPUT(135)
INPUT(138)
INPUT(143)
INPUT(146)
INPUT(149)
INPUT(152)
INPUT(153)
INPUT(156)
INPUT(159)
INPUT(165)
INPUT(171)
INPUT(177)
INPUT(183)
INPUT(189)
INPUT(195)
INPUT(201)
INPUT(207)
INPUT(210)
INPUT(219)
INPUT(228)
INPUT(237)
INPUT(246)
INPUT(255)
INPUT(259)
INPUT(260)
INPUT(261)
INPUT(267)
INPUT(268)
OUTPUT(388)
OUTPUT(389)
OUTPUT(390)
OUTPUT(391)
OUTPUT(418)
OUTPUT(419)
OUTPUT(420)
OUTPUT(421)
OUTPUT(422)
OUTPUT(423)
OUTPUT(446)
OUTPUT(447)
OUTPUT(448)
OUTPUT(449)
OUTPUT(450)
OUTPUT(767)
OUTPUT(768)
OUTPUT(850)
OUTPUT(863)
OUTPUT(864)
OUTPUT(865)
OUTPUT(866)
OUTPUT(874)
OUTPUT(878)
OUTPUT(879)
OUTPUT(880)
269 = NAND(1, 8, 13, 17)
270 = NAND(1, 26, 13, 17)
273 = AND(29, 36, 42)
276 = AND(1, 26, 51)
279 = NAND(1, 8, 51, 17)
280 = NAND(1, 8, 13, 55)
284 = NAND(59, 42, 68, 72)
285 = NAND(29, 68)
286 = NAND(59, 68, 74)
287 = AND(29, 75, 80)
290 = AND(29, 75, 42)
291 = AND(29, 36, 80)
292 = AND(29, 36, 42)
293 = AND(59, 75, 80)
294 = AND(59, 75, 42)
295 = AND(59, 36, 80)
296 = AND(59, 36, 42)
297 = AND(85, 86)
298 = OR(87, 88)
301 = NAND(91, 96)
302 = OR(91, 96)
303 = NAND(101, 106)
304 = OR(101, 106)
305 = NAND(111, 116)
306 = OR(111, 116)
307 = NAND(121, 126)
308 = OR(121, 126)
309 = AND(8, 138)
310 = NOT(268)
316 = AND(51, 138)
317 = AND(17, 138)
318 = AND(152, 138)
319 = NAND(59, 156)
322 = NOR(17, 42)
323 = AND(17, 42)
324 = NAND(159, 165)
325 = OR(159, 165)
326 = NAND(171, 177)
327 = OR(171, 177)
328 = NAND(183, 189)
329 = OR(183, 189)
330 = NAND(195, 201)
331 = OR(195, 201)
332 = AND(210, 91)
333 = AND(210, 96)
334 = AND(210, 101)
335 = AND(210, 106)
336 = AND(210, 111)
337 = AND(255, 259)
338 = AND(210, 116)
339 = AND(255, 260)
340 = AND(210, 121)
341 = AND(255, 267)
342 = NOT(269)
343 = NOT(273)
344 = OR(270, 273)
345 = NOT(276)
346 = NOT(276)
347 = NOT(279)
348 = NOR(280, 284)
349 = OR(280, 285)
350 = OR(280, 286)
351 = NOT(293)
352 = NOT(294)
353 = NOT(295)
354 = NOT(296)
355 = NAND(89, 298)
356 = AND(90, 298)
357 = NAND(301, 302)
360 = NAND(303, 304)
363 = NAND(305, 306)
366 = NAND(307, 308)
369 = NOT(310)
375 = NOR(322, 323)
376 = NAND(324, 325)
379 = NAND(326, 327)
382 = NAND(328, 329)
385 = NAND(330, 331)
388 = BUFF(290)
389 = BUFF(291)
390 = BUFF(292)
391 = BUFF(297)
392 = OR(270, 343)
393 = NOT(345)
399 = NOT(346)
400 = AND(348, 73)
401 = NOT(349)
402 = NOT(350)
403 = NOT(355)
404 = NOT(357)
405 = NOT(360)
406 = AND(357, 360)
407 = NOT(363)
408 = NOT(366)
409 = AND(363, 366)
410 = NAND(347, 352)
411 = NOT(376)
412 = NOT(379)
413 = AND(376, 379)
414 = NOT(382)
415 = NOT(385)
416 = AND(382, 385)
417 = AND(210, 369)
418 = BUFF(342)
419 = BUFF(344)
420 = BUFF(351)
421 = BUFF(353)
422 = BUFF(354)
423 = BUFF(356)
424 = NOT(400)
425 = AND(404, 405)
426 = AND(407, 408)
427 = AND(319, 393, 55)
432 = AND(393, 17, 287)
437 = NAND(393, 287, 55)
442 = NAND(375, 59, 156, 393)
443 = NAND(393, 319, 17)
444 = AND(411, 412)
445 = AND(414, 415)
446 = BUFF(392)
447 = BUFF(399)
448 = BUFF(401)
449 = BUFF(402)
450 = BUFF(403)
451 = NOT(424)
460 = NOR(406, 425)
463 = NOR(409, 426)
466 = NAND(442, 410)
475 = AND(143, 427)
476 = AND(310, 432)
477 = AND(146, 427)
478 = AND(310, 432)
479 = AND(149, 427)
480 = AND(310, 432)
481 = AND(153, 427)
482 = AND(310, 432)
483 = NAND(443, 1)
488 = OR(369, 437)
489 = OR(369, 437)
490 = OR(369, 437)
491 = OR(369, 437)
492 = NOR(413, 444)
495 = NOR(416, 445)
498 = NAND(130, 460)
499 = OR(130, 460)
500 = NAND(463, 135)
501 = OR(463, 135)
502 = AND(91, 466)
503 = NOR(475, 476)
504 = AND(96, 466)
505 = NOR(477, 478)
506 = AND(101, 466)
507 = NOR(479, 480)
508 = AND(106, 466)
509 = NOR(481, 482)
510 = AND(143, 483)
511 = AND(111, 466)
512 = AND(146, 483)
513 = AND(116, 466)
514 = AND(149, 483)
515 = AND(121, 466)
516 = AND(153, 483)
517 = AND(126, 466)
518 = NAND(130, 492)
519 = OR(130, 492)
520 = NAND(495, 207)
521 = OR(495, 207)
522 = AND(451, 159)
523 = AND(451, 165)
524 = AND(451, 171)
525 = AND(451, 177)
526 = AND(451, 183)
527 = NAND(451, 189)
528 = NAND(451, 195)
529 = NAND(451, 201)
530 = NAND(498, 499)
533 = NAND(500, 501)
536 = NOR(309, 502)
537 = NOR(316, 504)
538 = NOR(317, 506)
539 = NOR(318, 508)
540 = NOR(510, 511)
541 = NOR(512, 513)
542 = NOR(514, 515)
543 = NOR(516, 517)
544 = NAND(518, 519)
547 = NAND(520, 521)
550 = NOT(530)
551 = NOT(533)
552 = AND(530, 533)
553 = NAND(536, 503)
557 = NAND(537, 505)
561 = NAND(538, 507)
565 = NAND(539, 509)
569 = NAND(488, 540)
573 = NAND(489, 541)
577 = NAND(490, 542)
581 = NAND(491, 543)
585 = NOT(544)
586 = NOT(547)
587 = AND(544, 547)
588 = AND(550, 551)
589 = AND(585, 586)
590 = NAND(553, 159)
593 = OR(553, 159)
596 = AND(246, 553)
597 = NAND(557, 165)
600 = OR(557, 165)
605 = AND(246, 557)
606 = NAND(561, 171)
609 = OR(561, 171)
615 = AND(246, 561)
616 = NAND(565, 177)
619 = OR(565, 177)
624 = AND(246, 565)
625 = NAND(569, 183)
628 = OR(569, 183)
631 = AND(246, 569)
632 = NAND(573, 189)
635 = OR(573, 189)
640 = AND(246, 573)
641 = NAND(577, 195)
644 = OR(577, 195)
650 = AND(246, 577)
651 = NAND(581, 201)
654 = OR(581, 201)
659 = AND(246, 581)
660 = NOR(552, 588)
661 = NOR(587, 589)
662 = NOT(590)
665 = AND(593, 590)
669 = NOR(596, 522)
670 = NOT(597)
673 = AND(600, 597)
677 = NOR(605, 523)
678 = NOT(606)
682 = AND(609, 606)
686 = NOR(615, 524)
687 = NOT(616)
692 = AND(619, 616)
696 = NOR(624, 525)
697 = NOT(625)
700 = AND(628, 625)
704 = NOR(631, 526)
705 = NOT(632)
708 = AND(635, 632)
712 = NOR(337, 640)
713 = NOT(641)
717 = AND(644, 641)
721 = NOR(339, 650)
722 = NOT(651)
727 = AND(654, 651)
731 = NOR(341, 659)
732 = NAND(654, 261)
733 = NAND(644, 654, 261)
734 = NAND(635, 644, 654, 261)
735 = NOT(662)
736 = AND(228, 665)
737 = AND(237, 662)
738 = NOT(670)
739 = AND(228, 673)
740 = AND(237, 670)
741 = NOT(678)
742 = AND(228, 682)
743 = AND(237, 678)
744 = NOT(687)
745 = AND(228, 692)
746 = AND(237, 687)
747 = NOT(697)
748 = AND(228, 700)
749 = AND(237, 697)
750 = NOT(705)
751 = AND(228, 708)
752 = AND(237, 705)
753 = NOT(713)
754 = AND(228, 717)
755 = AND(237, 713)
756 = NOT(722)
757 = NOR(727, 261)
758 = AND(727, 261)
759 = AND(228, 727)
760 = AND(237, 722)
761 = NAND(644, 722)
762 = NAND(635, 713)
763 = NAND(635, 644, 722)
764 = NAND(609, 687)
765 = NAND(600, 678)
766 = NAND(600, 609, 687)
767 = BUFF(660)
768 = BUFF(661)
769 = NOR(736, 737)
770 = NOR(739, 740)
771 = NOR(742, 743)
772 = NOR(745, 746)
773 = NAND(750, 762, 763, 734)
777 = NOR(748, 749)
778 = NAND(753, 761, 733)
781 = NOR(751, 752)
782 = NAND(756, 732)
785 = NOR(754, 755)
786 = NOR(757, 758)
787 = NOR(759, 760)
788 = NOR(700, 773)
789 = AND(700, 773)
790 = NOR(708, 778)
791 = AND(708, 778)
792 = NOR(717, 782)
793 = AND(717, 782)
794 = AND(219, 786)
795 = NAND(628, 773)
796 = NAND(795, 747)
802 = NOR(788, 789)
803 = NOR(790, 791)
804 = NOR(792, 793)
805 = NOR(340, 794)
806 = NOR(692, 796)
807 = AND(692, 796)
808 = AND(219, 802)
809 = AND(219, 803)
810 = AND(219, 804)
811 = NAND(805, 787, 731, 529)
812 = NAND(619, 796)
813 = NAND(609, 619, 796)
814 = NAND(600, 609, 619, 796)
815 = NAND(738, 765, 766, 814)
819 = NAND(741, 764, 813)
822 = NAND(744, 812)
825 = NOR(806, 807)
826 = NOR(335, 808)
827 = NOR(336, 809)
828 = NOR(338, 810)
829 = NOT(811)
830 = NOR(665, 815)
831 = AND(665, 815)
832 = NOR(673, 819)
833 = AND(673, 819)
834 = NOR(682, 822)
835 = AND(682, 822)
836 = AND(219, 825)
837 = NAND(826, 777, 704)
838 = NAND(827, 781, 712, 527)
839 = NAND(828, 785, 721, 528)
840 = NOT(829)
841 = NAND(815, 593)
842 = NOR(830, 831)
843 = NOR(832, 833)
844 = NOR(834, 835)
845 = NOR(334, 836)
846 = NOT(837)
847 = NOT(838)
848 = NOT(839)
849 = AND(735, 841)
850 = BUFF(840)
851 = AND(219, 842)
852 = AND(219, 843)
853 = AND(219, 844)
854 = NAND(845, 772, 696)
855 = NOT(846)
856 = NOT(847)
857 = NOT(848)
858 = NOT(849)
859 = NOR(417, 851)
860 = NOR(332, 852)
861 = NOR(333, 853)
862 = NOT(854)
863 = BUFF(855)
864 = BUFF(856)
865 = BUFF(857)
866 = BUFF(858)
867 = NAND(859, 769, 669)
868 = NAND(860, 770, 677)
869 = NAND(861, 771, 686)
870 = NOT(862)
871 = NOT(867)
872 = NOT(868)
873 = NOT(869)
874 = BUFF(870)
875 = NOT(871)
876 = NOT(872)
877 = NOT(873)
878 = BUFF(875)
879 = BUFF(876)
880 = BUFF(877)

17
ISCAS85/convert.py
View File

@ -1,17 +0,0 @@
import os
import re
for file in os.listdir("."):
if not file.endswith(".bench"): continue
content = open(file, "r").read()
content = re.sub(r"(\d+)", r"\\\1", content)
print(content)
f = open("new/" + file, "w")
f.write(content)
f.close()

623
ISCAS85/new/c1355.bench
View File

@ -1,623 +0,0 @@
# c\1355
INPUT(\1)
INPUT(\8)
INPUT(\15)
INPUT(\22)
INPUT(\29)
INPUT(\36)
INPUT(\43)
INPUT(\50)
INPUT(\57)
INPUT(\64)
INPUT(\71)
INPUT(\78)
INPUT(\85)
INPUT(\92)
INPUT(\99)
INPUT(\106)
INPUT(\113)
INPUT(\120)
INPUT(\127)
INPUT(\134)
INPUT(\141)
INPUT(\148)
INPUT(\155)
INPUT(\162)
INPUT(\169)
INPUT(\176)
INPUT(\183)
INPUT(\190)
INPUT(\197)
INPUT(\204)
INPUT(\211)
INPUT(\218)
INPUT(\225)
INPUT(\226)
INPUT(\227)
INPUT(\228)
INPUT(\229)
INPUT(\230)
INPUT(\231)
INPUT(\232)
INPUT(\233)
OUTPUT(\1324)
OUTPUT(\1325)
OUTPUT(\1326)
OUTPUT(\1327)
OUTPUT(\1328)
OUTPUT(\1329)
OUTPUT(\1330)
OUTPUT(\1331)
OUTPUT(\1332)
OUTPUT(\1333)
OUTPUT(\1334)
OUTPUT(\1335)
OUTPUT(\1336)
OUTPUT(\1337)
OUTPUT(\1338)
OUTPUT(\1339)
OUTPUT(\1340)
OUTPUT(\1341)
OUTPUT(\1342)
OUTPUT(\1343)
OUTPUT(\1344)
OUTPUT(\1345)
OUTPUT(\1346)
OUTPUT(\1347)
OUTPUT(\1348)
OUTPUT(\1349)
OUTPUT(\1350)
OUTPUT(\1351)
OUTPUT(\1352)
OUTPUT(\1353)
OUTPUT(\1354)
OUTPUT(\1355)
\242 = AND(\225, \233)
\245 = AND(\226, \233)
\248 = AND(\227, \233)
\251 = AND(\228, \233)
\254 = AND(\229, \233)
\257 = AND(\230, \233)
\260 = AND(\231, \233)
\263 = AND(\232, \233)
\266 = NAND(\1, \8)
\269 = NAND(\15, \22)
\272 = NAND(\29, \36)
\275 = NAND(\43, \50)
\278 = NAND(\57, \64)
\281 = NAND(\71, \78)
\284 = NAND(\85, \92)
\287 = NAND(\99, \106)
\290 = NAND(\113, \120)
\293 = NAND(\127, \134)
\296 = NAND(\141, \148)
\299 = NAND(\155, \162)
\302 = NAND(\169, \176)
\305 = NAND(\183, \190)
\308 = NAND(\197, \204)
\311 = NAND(\211, \218)
\314 = NAND(\1, \29)
\317 = NAND(\57, \85)
\320 = NAND(\8, \36)
\323 = NAND(\64, \92)
\326 = NAND(\15, \43)
\329 = NAND(\71, \99)
\332 = NAND(\22, \50)
\335 = NAND(\78, \106)
\338 = NAND(\113, \141)
\341 = NAND(\169, \197)
\344 = NAND(\120, \148)
\347 = NAND(\176, \204)
\350 = NAND(\127, \155)
\353 = NAND(\183, \211)
\356 = NAND(\134, \162)
\359 = NAND(\190, \218)
\362 = NAND(\1, \266)
\363 = NAND(\8, \266)
\364 = NAND(\15, \269)
\365 = NAND(\22, \269)
\366 = NAND(\29, \272)
\367 = NAND(\36, \272)
\368 = NAND(\43, \275)
\369 = NAND(\50, \275)
\370 = NAND(\57, \278)
\371 = NAND(\64, \278)
\372 = NAND(\71, \281)
\373 = NAND(\78, \281)
\374 = NAND(\85, \284)
\375 = NAND(\92, \284)
\376 = NAND(\99, \287)
\377 = NAND(\106, \287)
\378 = NAND(\113, \290)
\379 = NAND(\120, \290)
\380 = NAND(\127, \293)
\381 = NAND(\134, \293)
\382 = NAND(\141, \296)
\383 = NAND(\148, \296)
\384 = NAND(\155, \299)
\385 = NAND(\162, \299)
\386 = NAND(\169, \302)
\387 = NAND(\176, \302)
\388 = NAND(\183, \305)
\389 = NAND(\190, \305)
\390 = NAND(\197, \308)
\391 = NAND(\204, \308)
\392 = NAND(\211, \311)
\393 = NAND(\218, \311)
\394 = NAND(\1, \314)
\395 = NAND(\29, \314)
\396 = NAND(\57, \317)
\397 = NAND(\85, \317)
\398 = NAND(\8, \320)
\399 = NAND(\36, \320)
\400 = NAND(\64, \323)
\401 = NAND(\92, \323)
\402 = NAND(\15, \326)
\403 = NAND(\43, \326)
\404 = NAND(\71, \329)
\405 = NAND(\99, \329)
\406 = NAND(\22, \332)
\407 = NAND(\50, \332)
\408 = NAND(\78, \335)
\409 = NAND(\106, \335)
\410 = NAND(\113, \338)
\411 = NAND(\141, \338)
\412 = NAND(\169, \341)
\413 = NAND(\197, \341)
\414 = NAND(\120, \344)
\415 = NAND(\148, \344)
\416 = NAND(\176, \347)
\417 = NAND(\204, \347)
\418 = NAND(\127, \350)
\419 = NAND(\155, \350)
\420 = NAND(\183, \353)
\421 = NAND(\211, \353)
\422 = NAND(\134, \356)
\423 = NAND(\162, \356)
\424 = NAND(\190, \359)
\425 = NAND(\218, \359)
\426 = NAND(\362, \363)
\429 = NAND(\364, \365)
\432 = NAND(\366, \367)
\435 = NAND(\368, \369)
\438 = NAND(\370, \371)
\441 = NAND(\372, \373)
\444 = NAND(\374, \375)
\447 = NAND(\376, \377)
\450 = NAND(\378, \379)
\453 = NAND(\380, \381)
\456 = NAND(\382, \383)
\459 = NAND(\384, \385)
\462 = NAND(\386, \387)
\465 = NAND(\388, \389)
\468 = NAND(\390, \391)
\471 = NAND(\392, \393)
\474 = NAND(\394, \395)
\477 = NAND(\396, \397)
\480 = NAND(\398, \399)
\483 = NAND(\400, \401)
\486 = NAND(\402, \403)
\489 = NAND(\404, \405)
\492 = NAND(\406, \407)
\495 = NAND(\408, \409)
\498 = NAND(\410, \411)
\501 = NAND(\412, \413)
\504 = NAND(\414, \415)
\507 = NAND(\416, \417)
\510 = NAND(\418, \419)
\513 = NAND(\420, \421)
\516 = NAND(\422, \423)
\519 = NAND(\424, \425)
\522 = NAND(\426, \429)
\525 = NAND(\432, \435)
\528 = NAND(\438, \441)
\531 = NAND(\444, \447)
\534 = NAND(\450, \453)
\537 = NAND(\456, \459)
\540 = NAND(\462, \465)
\543 = NAND(\468, \471)
\546 = NAND(\474, \477)
\549 = NAND(\480, \483)
\552 = NAND(\486, \489)
\555 = NAND(\492, \495)
\558 = NAND(\498, \501)
\561 = NAND(\504, \507)
\564 = NAND(\510, \513)
\567 = NAND(\516, \519)
\570 = NAND(\426, \522)
\571 = NAND(\429, \522)
\572 = NAND(\432, \525)
\573 = NAND(\435, \525)
\574 = NAND(\438, \528)
\575 = NAND(\441, \528)
\576 = NAND(\444, \531)
\577 = NAND(\447, \531)
\578 = NAND(\450, \534)
\579 = NAND(\453, \534)
\580 = NAND(\456, \537)
\581 = NAND(\459, \537)
\582 = NAND(\462, \540)
\583 = NAND(\465, \540)
\584 = NAND(\468, \543)
\585 = NAND(\471, \543)
\586 = NAND(\474, \546)
\587 = NAND(\477, \546)
\588 = NAND(\480, \549)
\589 = NAND(\483, \549)
\590 = NAND(\486, \552)
\591 = NAND(\489, \552)
\592 = NAND(\492, \555)
\593 = NAND(\495, \555)
\594 = NAND(\498, \558)
\595 = NAND(\501, \558)
\596 = NAND(\504, \561)
\597 = NAND(\507, \561)
\598 = NAND(\510, \564)
\599 = NAND(\513, \564)
\600 = NAND(\516, \567)
\601 = NAND(\519, \567)
\602 = NAND(\570, \571)
\607 = NAND(\572, \573)
\612 = NAND(\574, \575)
\617 = NAND(\576, \577)
\622 = NAND(\578, \579)
\627 = NAND(\580, \581)
\632 = NAND(\582, \583)
\637 = NAND(\584, \585)
\642 = NAND(\586, \587)
\645 = NAND(\588, \589)
\648 = NAND(\590, \591)
\651 = NAND(\592, \593)
\654 = NAND(\594, \595)
\657 = NAND(\596, \597)
\660 = NAND(\598, \599)
\663 = NAND(\600, \601)
\666 = NAND(\602, \607)
\669 = NAND(\612, \617)
\672 = NAND(\602, \612)
\675 = NAND(\607, \617)
\678 = NAND(\622, \627)
\681 = NAND(\632, \637)
\684 = NAND(\622, \632)
\687 = NAND(\627, \637)
\690 = NAND(\602, \666)
\691 = NAND(\607, \666)
\692 = NAND(\612, \669)
\693 = NAND(\617, \669)
\694 = NAND(\602, \672)
\695 = NAND(\612, \672)
\696 = NAND(\607, \675)
\697 = NAND(\617, \675)
\698 = NAND(\622, \678)
\699 = NAND(\627, \678)
\700 = NAND(\632, \681)
\701 = NAND(\637, \681)
\702 = NAND(\622, \684)
\703 = NAND(\632, \684)
\704 = NAND(\627, \687)
\705 = NAND(\637, \687)
\706 = NAND(\690, \691)
\709 = NAND(\692, \693)
\712 = NAND(\694, \695)
\715 = NAND(\696, \697)
\718 = NAND(\698, \699)
\721 = NAND(\700, \701)
\724 = NAND(\702, \703)
\727 = NAND(\704, \705)
\730 = NAND(\242, \718)
\733 = NAND(\245, \721)
\736 = NAND(\248, \724)
\739 = NAND(\251, \727)
\742 = NAND(\254, \706)
\745 = NAND(\257, \709)
\748 = NAND(\260, \712)
\751 = NAND(\263, \715)
\754 = NAND(\242, \730)
\755 = NAND(\718, \730)
\756 = NAND(\245, \733)
\757 = NAND(\721, \733)
\758 = NAND(\248, \736)
\759 = NAND(\724, \736)
\760 = NAND(\251, \739)
\761 = NAND(\727, \739)
\762 = NAND(\254, \742)
\763 = NAND(\706, \742)
\764 = NAND(\257, \745)
\765 = NAND(\709, \745)
\766 = NAND(\260, \748)
\767 = NAND(\712, \748)
\768 = NAND(\263, \751)
\769 = NAND(\715, \751)
\770 = NAND(\754, \755)
\773 = NAND(\756, \757)
\776 = NAND(\758, \759)
\779 = NAND(\760, \761)
\782 = NAND(\762, \763)
\785 = NAND(\764, \765)
\788 = NAND(\766, \767)
\791 = NAND(\768, \769)
\794 = NAND(\642, \770)
\797 = NAND(\645, \773)
\800 = NAND(\648, \776)
\803 = NAND(\651, \779)
\806 = NAND(\654, \782)
\809 = NAND(\657, \785)
\812 = NAND(\660, \788)
\815 = NAND(\663, \791)
\818 = NAND(\642, \794)
\819 = NAND(\770, \794)
\820 = NAND(\645, \797)
\821 = NAND(\773, \797)
\822 = NAND(\648, \800)
\823 = NAND(\776, \800)
\824 = NAND(\651, \803)
\825 = NAND(\779, \803)
\826 = NAND(\654, \806)
\827 = NAND(\782, \806)
\828 = NAND(\657, \809)
\829 = NAND(\785, \809)
\830 = NAND(\660, \812)
\831 = NAND(\788, \812)
\832 = NAND(\663, \815)
\833 = NAND(\791, \815)
\834 = NAND(\818, \819)
\847 = NAND(\820, \821)
\860 = NAND(\822, \823)
\873 = NAND(\824, \825)
\886 = NAND(\828, \829)
\899 = NAND(\832, \833)
\912 = NAND(\830, \831)
\925 = NAND(\826, \827)
\938 = NOT(\834)
\939 = NOT(\847)
\940 = NOT(\860)
\941 = NOT(\834)
\942 = NOT(\847)
\943 = NOT(\873)
\944 = NOT(\834)
\945 = NOT(\860)
\946 = NOT(\873)
\947 = NOT(\847)
\948 = NOT(\860)
\949 = NOT(\873)
\950 = NOT(\886)
\951 = NOT(\899)
\952 = NOT(\886)
\953 = NOT(\912)
\954 = NOT(\925)
\955 = NOT(\899)
\956 = NOT(\925)
\957 = NOT(\912)
\958 = NOT(\925)
\959 = NOT(\886)
\960 = NOT(\912)
\961 = NOT(\925)
\962 = NOT(\886)
\963 = NOT(\899)
\964 = NOT(\925)
\965 = NOT(\912)
\966 = NOT(\899)
\967 = NOT(\886)
\968 = NOT(\912)
\969 = NOT(\899)
\970 = NOT(\847)
\971 = NOT(\873)
\972 = NOT(\847)
\973 = NOT(\860)
\974 = NOT(\834)
\975 = NOT(\873)
\976 = NOT(\834)
\977 = NOT(\860)
\978 = AND(\938, \939, \940, \873)
\979 = AND(\941, \942, \860, \943)
\980 = AND(\944, \847, \945, \946)
\981 = AND(\834, \947, \948, \949)
\982 = AND(\958, \959, \960, \899)
\983 = AND(\961, \962, \912, \963)
\984 = AND(\964, \886, \965, \966)
\985 = AND(\925, \967, \968, \969)
\986 = OR(\978, \979, \980, \981)
\991 = OR(\982, \983, \984, \985)
\996 = AND(\925, \950, \912, \951, \986)
\1001 = AND(\925, \952, \953, \899, \986)
\1006 = AND(\954, \886, \912, \955, \986)
\1011 = AND(\956, \886, \957, \899, \986)
\1016 = AND(\834, \970, \860, \971, \991)
\1021 = AND(\834, \972, \973, \873, \991)
\1026 = AND(\974, \847, \860, \975, \991)
\1031 = AND(\976, \847, \977, \873, \991)
\1036 = AND(\834, \996)
\1039 = AND(\847, \996)
\1042 = AND(\860, \996)
\1045 = AND(\873, \996)
\1048 = AND(\834, \1001)
\1051 = AND(\847, \1001)
\1054 = AND(\860, \1001)
\1057 = AND(\873, \1001)
\1060 = AND(\834, \1006)
\1063 = AND(\847, \1006)
\1066 = AND(\860, \1006)
\1069 = AND(\873, \1006)
\1072 = AND(\834, \1011)
\1075 = AND(\847, \1011)
\1078 = AND(\860, \1011)
\1081 = AND(\873, \1011)
\1084 = AND(\925, \1016)
\1087 = AND(\886, \1016)
\1090 = AND(\912, \1016)
\1093 = AND(\899, \1016)
\1096 = AND(\925, \1021)
\1099 = AND(\886, \1021)
\1102 = AND(\912, \1021)
\1105 = AND(\899, \1021)
\1108 = AND(\925, \1026)
\1111 = AND(\886, \1026)
\1114 = AND(\912, \1026)
\1117 = AND(\899, \1026)
\1120 = AND(\925, \1031)
\1123 = AND(\886, \1031)
\1126 = AND(\912, \1031)
\1129 = AND(\899, \1031)
\1132 = NAND(\1, \1036)
\1135 = NAND(\8, \1039)
\1138 = NAND(\15, \1042)
\1141 = NAND(\22, \1045)
\1144 = NAND(\29, \1048)
\1147 = NAND(\36, \1051)
\1150 = NAND(\43, \1054)
\1153 = NAND(\50, \1057)
\1156 = NAND(\57, \1060)
\1159 = NAND(\64, \1063)
\1162 = NAND(\71, \1066)
\1165 = NAND(\78, \1069)
\1168 = NAND(\85, \1072)
\1171 = NAND(\92, \1075)
\1174 = NAND(\99, \1078)
\1177 = NAND(\106, \1081)
\1180 = NAND(\113, \1084)
\1183 = NAND(\120, \1087)
\1186 = NAND(\127, \1090)
\1189 = NAND(\134, \1093)
\1192 = NAND(\141, \1096)
\1195 = NAND(\148, \1099)
\1198 = NAND(\155, \1102)
\1201 = NAND(\162, \1105)
\1204 = NAND(\169, \1108)
\1207 = NAND(\176, \1111)
\1210 = NAND(\183, \1114)
\1213 = NAND(\190, \1117)
\1216 = NAND(\197, \1120)
\1219 = NAND(\204, \1123)
\1222 = NAND(\211, \1126)
\1225 = NAND(\218, \1129)
\1228 = NAND(\1, \1132)
\1229 = NAND(\1036, \1132)
\1230 = NAND(\8, \1135)
\1231 = NAND(\1039, \1135)
\1232 = NAND(\15, \1138)
\1233 = NAND(\1042, \1138)
\1234 = NAND(\22, \1141)
\1235 = NAND(\1045, \1141)
\1236 = NAND(\29, \1144)
\1237 = NAND(\1048, \1144)
\1238 = NAND(\36, \1147)
\1239 = NAND(\1051, \1147)
\1240 = NAND(\43, \1150)
\1241 = NAND(\1054, \1150)
\1242 = NAND(\50, \1153)
\1243 = NAND(\1057, \1153)
\1244 = NAND(\57, \1156)
\1245 = NAND(\1060, \1156)
\1246 = NAND(\64, \1159)
\1247 = NAND(\1063, \1159)
\1248 = NAND(\71, \1162)
\1249 = NAND(\1066, \1162)
\1250 = NAND(\78, \1165)
\1251 = NAND(\1069, \1165)
\1252 = NAND(\85, \1168)
\1253 = NAND(\1072, \1168)
\1254 = NAND(\92, \1171)
\1255 = NAND(\1075, \1171)
\1256 = NAND(\99, \1174)
\1257 = NAND(\1078, \1174)
\1258 = NAND(\106, \1177)
\1259 = NAND(\1081, \1177)
\1260 = NAND(\113, \1180)
\1261 = NAND(\1084, \1180)
\1262 = NAND(\120, \1183)
\1263 = NAND(\1087, \1183)
\1264 = NAND(\127, \1186)
\1265 = NAND(\1090, \1186)
\1266 = NAND(\134, \1189)
\1267 = NAND(\1093, \1189)
\1268 = NAND(\141, \1192)
\1269 = NAND(\1096, \1192)
\1270 = NAND(\148, \1195)
\1271 = NAND(\1099, \1195)
\1272 = NAND(\155, \1198)
\1273 = NAND(\1102, \1198)
\1274 = NAND(\162, \1201)
\1275 = NAND(\1105, \1201)
\1276 = NAND(\169, \1204)
\1277 = NAND(\1108, \1204)
\1278 = NAND(\176, \1207)
\1279 = NAND(\1111, \1207)
\1280 = NAND(\183, \1210)
\1281 = NAND(\1114, \1210)
\1282 = NAND(\190, \1213)
\1283 = NAND(\1117, \1213)
\1284 = NAND(\197, \1216)
\1285 = NAND(\1120, \1216)
\1286 = NAND(\204, \1219)
\1287 = NAND(\1123, \1219)
\1288 = NAND(\211, \1222)
\1289 = NAND(\1126, \1222)
\1290 = NAND(\218, \1225)
\1291 = NAND(\1129, \1225)
\1292 = NAND(\1228, \1229)
\1293 = NAND(\1230, \1231)
\1294 = NAND(\1232, \1233)
\1295 = NAND(\1234, \1235)
\1296 = NAND(\1236, \1237)
\1297 = NAND(\1238, \1239)
\1298 = NAND(\1240, \1241)
\1299 = NAND(\1242, \1243)
\1300 = NAND(\1244, \1245)
\1301 = NAND(\1246, \1247)
\1302 = NAND(\1248, \1249)
\1303 = NAND(\1250, \1251)
\1304 = NAND(\1252, \1253)
\1305 = NAND(\1254, \1255)
\1306 = NAND(\1256, \1257)
\1307 = NAND(\1258, \1259)
\1308 = NAND(\1260, \1261)
\1309 = NAND(\1262, \1263)
\1310 = NAND(\1264, \1265)
\1311 = NAND(\1266, \1267)
\1312 = NAND(\1268, \1269)
\1313 = NAND(\1270, \1271)
\1314 = NAND(\1272, \1273)
\1315 = NAND(\1274, \1275)
\1316 = NAND(\1276, \1277)
\1317 = NAND(\1278, \1279)
\1318 = NAND(\1280, \1281)
\1319 = NAND(\1282, \1283)
\1320 = NAND(\1284, \1285)
\1321 = NAND(\1286, \1287)
\1322 = NAND(\1288, \1289)
\1323 = NAND(\1290, \1291)
\1324 = BUFF(\1292)
\1325 = BUFF(\1293)
\1326 = BUFF(\1294)
\1327 = BUFF(\1295)
\1328 = BUFF(\1296)
\1329 = BUFF(\1297)
\1330 = BUFF(\1298)
\1331 = BUFF(\1299)
\1332 = BUFF(\1300)
\1333 = BUFF(\1301)
\1334 = BUFF(\1302)
\1335 = BUFF(\1303)
\1336 = BUFF(\1304)
\1337 = BUFF(\1305)
\1338 = BUFF(\1306)
\1339 = BUFF(\1307)
\1340 = BUFF(\1308)
\1341 = BUFF(\1309)
\1342 = BUFF(\1310)
\1343 = BUFF(\1311)
\1344 = BUFF(\1312)
\1345 = BUFF(\1313)
\1346 = BUFF(\1314)
\1347 = BUFF(\1315)
\1348 = BUFF(\1316)
\1349 = BUFF(\1317)
\1350 = BUFF(\1318)
\1351 = BUFF(\1319)
\1352 = BUFF(\1320)
\1353 = BUFF(\1321)
\1354 = BUFF(\1322)
\1355 = BUFF(\1323)

17
ISCAS85/new/c17.bench
View File

@ -1,17 +0,0 @@
# c\17
INPUT(\1)
INPUT(\2)
INPUT(\3)
INPUT(\6)
INPUT(\7)
OUTPUT(\22)
OUTPUT(\23)
\10 = NAND(\1, \3)
\11 = NAND(\3, \6)
\16 = NAND(\2, \11)
\19 = NAND(\11, \7)
\22 = NAND(\10, \16)
\23 = NAND(\16, \19)

16
ISCAS85/new/c17.test
View File

@ -1,16 +0,0 @@
* Name of circuit: c17.bench
* Primary inputs :
\1 \2 \3 \6 \7
* Primary outputs:
\22 \23
* Test patterns and fault free responses:
1: 01100 11
2: 10000 00
3: 00001 01
4: 00111 00
5: 01110 00
6: 01010 11
7: 10100 10

8
ISCAS85/new/c17.vec
View File

@ -1,8 +0,0 @@
01100
10000
00001
00111
01110
01010
10100
END

942
ISCAS85/new/c1908.bench
View File

@ -1,942 +0,0 @@
# c\1908
INPUT(\1)
INPUT(\4)
INPUT(\7)
INPUT(\10)
INPUT(\13)
INPUT(\16)
INPUT(\19)
INPUT(\22)
INPUT(\25)
INPUT(\28)
INPUT(\31)
INPUT(\34)
INPUT(\37)
INPUT(\40)
INPUT(\43)
INPUT(\46)
INPUT(\49)
INPUT(\53)
INPUT(\56)
INPUT(\60)
INPUT(\63)
INPUT(\66)
INPUT(\69)
INPUT(\72)
INPUT(\76)
INPUT(\79)
INPUT(\82)
INPUT(\85)
INPUT(\88)
INPUT(\91)
INPUT(\94)
INPUT(\99)
INPUT(\104)
OUTPUT(\2753)
OUTPUT(\2754)
OUTPUT(\2755)
OUTPUT(\2756)
OUTPUT(\2762)
OUTPUT(\2767)
OUTPUT(\2768)
OUTPUT(\2779)
OUTPUT(\2780)
OUTPUT(\2781)
OUTPUT(\2782)
OUTPUT(\2783)
OUTPUT(\2784)
OUTPUT(\2785)
OUTPUT(\2786)
OUTPUT(\2787)
OUTPUT(\2811)
OUTPUT(\2886)
OUTPUT(\2887)
OUTPUT(\2888)
OUTPUT(\2889)
OUTPUT(\2890)
OUTPUT(\2891)
OUTPUT(\2892)
OUTPUT(\2899)
\190 = NOT(\1)
\194 = NOT(\4)
\197 = NOT(\7)
\201 = NOT(\10)
\206 = NOT(\13)
\209 = NOT(\16)
\212 = NOT(\19)
\216 = NOT(\22)
\220 = NOT(\25)
\225 = NOT(\28)
\229 = NOT(\31)
\232 = NOT(\34)
\235 = NOT(\37)
\239 = NOT(\40)
\243 = NOT(\43)
\247 = NOT(\46)
\251 = NAND(\63, \88)
\252 = NAND(\66, \91)
\253 = NOT(\72)
\256 = NOT(\72)
\257 = BUFF(\69)
\260 = BUFF(\69)
\263 = NOT(\76)
\266 = NOT(\79)
\269 = NOT(\82)
\272 = NOT(\85)
\275 = NOT(\104)
\276 = NOT(\104)
\277 = NOT(\88)
\280 = NOT(\91)
\283 = BUFF(\94)
\290 = NOT(\94)
\297 = BUFF(\94)
\300 = NOT(\94)
\303 = BUFF(\99)
\306 = NOT(\99)
\313 = NOT(\99)
\316 = BUFF(\104)
\319 = NOT(\104)
\326 = BUFF(\104)
\331 = BUFF(\104)
\338 = NOT(\104)
\343 = BUFF(\1)
\346 = BUFF(\4)
\349 = BUFF(\7)
\352 = BUFF(\10)
\355 = BUFF(\13)
\358 = BUFF(\16)
\361 = BUFF(\19)
\364 = BUFF(\22)
\367 = BUFF(\25)
\370 = BUFF(\28)
\373 = BUFF(\31)
\376 = BUFF(\34)
\379 = BUFF(\37)
\382 = BUFF(\40)
\385 = BUFF(\43)
\388 = BUFF(\46)
\534 = NOT(\343)
\535 = NOT(\346)
\536 = NOT(\349)
\537 = NOT(\352)
\538 = NOT(\355)
\539 = NOT(\358)
\540 = NOT(\361)
\541 = NOT(\364)
\542 = NOT(\367)
\543 = NOT(\370)
\544 = NOT(\373)
\545 = NOT(\376)
\546 = NOT(\379)
\547 = NOT(\382)
\548 = NOT(\385)
\549 = NOT(\388)
\550 = NAND(\306, \331)
\551 = NAND(\306, \331)
\552 = NAND(\306, \331)
\553 = NAND(\306, \331)
\554 = NAND(\306, \331)
\555 = NAND(\306, \331)
\556 = BUFF(\190)
\559 = BUFF(\194)
\562 = BUFF(\206)
\565 = BUFF(\209)
\568 = BUFF(\225)
\571 = BUFF(\243)
\574 = AND(\63, \319)
\577 = BUFF(\220)
\580 = BUFF(\229)
\583 = BUFF(\232)
\586 = AND(\66, \319)
\589 = BUFF(\239)
\592 = AND(\49, \253, \319)
\595 = BUFF(\247)
\598 = BUFF(\239)
\601 = NAND(\326, \277)
\602 = NAND(\326, \280)
\603 = NAND(\260, \72)
\608 = NAND(\260, \300)
\612 = NAND(\256, \300)
\616 = BUFF(\201)
\619 = BUFF(\216)
\622 = BUFF(\220)
\625 = BUFF(\239)
\628 = BUFF(\190)
\631 = BUFF(\190)
\634 = BUFF(\194)
\637 = BUFF(\229)
\640 = BUFF(\197)
\643 = AND(\56, \257, \319)
\646 = BUFF(\232)
\649 = BUFF(\201)
\652 = BUFF(\235)
\655 = AND(\60, \257, \319)
\658 = BUFF(\263)
\661 = BUFF(\263)
\664 = BUFF(\266)
\667 = BUFF(\266)
\670 = BUFF(\269)
\673 = BUFF(\269)
\676 = BUFF(\272)
\679 = BUFF(\272)
\682 = AND(\251, \316)
\685 = AND(\252, \316)
\688 = BUFF(\197)
\691 = BUFF(\197)
\694 = BUFF(\212)
\697 = BUFF(\212)
\700 = BUFF(\247)
\703 = BUFF(\247)
\706 = BUFF(\235)
\709 = BUFF(\235)
\712 = BUFF(\201)
\715 = BUFF(\201)
\718 = BUFF(\206)
\721 = BUFF(\216)
\724 = AND(\53, \253, \319)
\727 = BUFF(\243)
\730 = BUFF(\220)
\733 = BUFF(\220)
\736 = BUFF(\209)
\739 = BUFF(\216)
\742 = BUFF(\225)
\745 = BUFF(\243)
\748 = BUFF(\212)
\751 = BUFF(\225)
\886 = NOT(\682)
\887 = NOT(\685)
\888 = NOT(\616)
\889 = NOT(\619)
\890 = NOT(\622)
\891 = NOT(\625)
\892 = NOT(\631)
\893 = NOT(\643)
\894 = NOT(\649)
\895 = NOT(\652)
\896 = NOT(\655)
\897 = AND(\49, \612)
\898 = AND(\56, \608)
\899 = NAND(\53, \612)
\903 = NAND(\60, \608)
\907 = NAND(\49, \612)
\910 = NAND(\56, \608)
\913 = NOT(\661)
\914 = NOT(\658)
\915 = NOT(\667)
\916 = NOT(\664)
\917 = NOT(\673)
\918 = NOT(\670)
\919 = NOT(\679)
\920 = NOT(\676)
\921 = NAND(\277, \297, \326, \603)
\922 = NAND(\280, \297, \326, \603)
\923 = NAND(\303, \338, \603)
\926 = AND(\303, \338, \603)
\935 = BUFF(\556)
\938 = NOT(\688)
\939 = BUFF(\556)
\942 = NOT(\691)
\943 = BUFF(\562)
\946 = NOT(\694)
\947 = BUFF(\562)
\950 = NOT(\697)
\951 = BUFF(\568)
\954 = NOT(\700)
\955 = BUFF(\568)
\958 = NOT(\703)
\959 = BUFF(\574)
\962 = BUFF(\574)
\965 = BUFF(\580)
\968 = NOT(\706)
\969 = BUFF(\580)
\972 = NOT(\709)
\973 = BUFF(\586)
\976 = NOT(\712)
\977 = BUFF(\586)
\980 = NOT(\715)
\981 = BUFF(\592)
\984 = NOT(\628)
\985 = BUFF(\592)
\988 = NOT(\718)
\989 = NOT(\721)
\990 = NOT(\634)
\991 = NOT(\724)
\992 = NOT(\727)
\993 = NOT(\637)
\994 = BUFF(\595)
\997 = NOT(\730)
\998 = BUFF(\595)
\1001 = NOT(\733)
\1002 = NOT(\736)
\1003 = NOT(\739)
\1004 = NOT(\640)
\1005 = NOT(\742)
\1006 = NOT(\745)
\1007 = NOT(\646)
\1008 = NOT(\748)
\1009 = NOT(\751)
\1010 = BUFF(\559)
\1013 = BUFF(\559)
\1016 = BUFF(\565)
\1019 = BUFF(\565)
\1022 = BUFF(\571)
\1025 = BUFF(\571)
\1028 = BUFF(\577)
\1031 = BUFF(\577)
\1034 = BUFF(\583)
\1037 = BUFF(\583)
\1040 = BUFF(\589)
\1043 = BUFF(\589)
\1046 = BUFF(\598)
\1049 = BUFF(\598)
\1054 = NAND(\619, \888)
\1055 = NAND(\616, \889)
\1063 = NAND(\625, \890)
\1064 = NAND(\622, \891)
\1067 = NAND(\655, \895)
\1068 = NAND(\652, \896)
\1119 = NAND(\721, \988)
\1120 = NAND(\718, \989)
\1121 = NAND(\727, \991)
\1122 = NAND(\724, \992)
\1128 = NAND(\739, \1002)
\1129 = NAND(\736, \1003)
\1130 = NAND(\745, \1005)
\1131 = NAND(\742, \1006)
\1132 = NAND(\751, \1008)
\1133 = NAND(\748, \1009)
\1148 = NOT(\939)
\1149 = NOT(\935)
\1150 = NAND(\1054, \1055)
\1151 = NOT(\943)
\1152 = NOT(\947)
\1153 = NOT(\955)
\1154 = NOT(\951)
\1155 = NOT(\962)
\1156 = NOT(\969)
\1157 = NOT(\977)
\1158 = NAND(\1063, \1064)
\1159 = NOT(\985)
\1160 = NAND(\985, \892)
\1161 = NOT(\998)
\1162 = NAND(\1067, \1068)
\1163 = NOT(\899)
\1164 = BUFF(\899)
\1167 = NOT(\903)
\1168 = BUFF(\903)
\1171 = NAND(\921, \923)
\1188 = NAND(\922, \923)
\1205 = NOT(\1010)
\1206 = NAND(\1010, \938)
\1207 = NOT(\1013)
\1208 = NAND(\1013, \942)
\1209 = NOT(\1016)
\1210 = NAND(\1016, \946)
\1211 = NOT(\1019)
\1212 = NAND(\1019, \950)
\1213 = NOT(\1022)
\1214 = NAND(\1022, \954)
\1215 = NOT(\1025)
\1216 = NAND(\1025, \958)
\1217 = NOT(\1028)
\1218 = NOT(\959)
\1219 = NOT(\1031)
\1220 = NOT(\1034)
\1221 = NAND(\1034, \968)
\1222 = NOT(\965)
\1223 = NOT(\1037)
\1224 = NAND(\1037, \972)
\1225 = NOT(\1040)
\1226 = NAND(\1040, \976)
\1227 = NOT(\973)
\1228 = NOT(\1043)
\1229 = NAND(\1043, \980)
\1230 = NOT(\981)
\1231 = NAND(\981, \984)
\1232 = NAND(\1119, \1120)
\1235 = NAND(\1121, \1122)
\1238 = NOT(\1046)
\1239 = NAND(\1046, \997)
\1240 = NOT(\994)
\1241 = NOT(\1049)
\1242 = NAND(\1049, \1001)
\1243 = NAND(\1128, \1129)
\1246 = NAND(\1130, \1131)
\1249 = NAND(\1132, \1133)
\1252 = BUFF(\907)
\1255 = BUFF(\907)
\1258 = BUFF(\910)
\1261 = BUFF(\910)
\1264 = NOT(\1150)
\1267 = NAND(\631, \1159)
\1309 = NAND(\688, \1205)
\1310 = NAND(\691, \1207)
\1311 = NAND(\694, \1209)
\1312 = NAND(\697, \1211)
\1313 = NAND(\700, \1213)
\1314 = NAND(\703, \1215)
\1315 = NAND(\706, \1220)
\1316 = NAND(\709, \1223)
\1317 = NAND(\712, \1225)
\1318 = NAND(\715, \1228)
\1319 = NOT(\1158)
\1322 = NAND(\628, \1230)
\1327 = NAND(\730, \1238)
\1328 = NAND(\733, \1241)
\1334 = NOT(\1162)
\1344 = NAND(\1267, \1160)
\1345 = NAND(\1249, \894)
\1346 = NOT(\1249)
\1348 = NOT(\1255)
\1349 = NOT(\1252)
\1350 = NOT(\1261)
\1351 = NOT(\1258)
\1352 = NAND(\1309, \1206)
\1355 = NAND(\1310, \1208)
\1358 = NAND(\1311, \1210)
\1361 = NAND(\1312, \1212)
\1364 = NAND(\1313, \1214)
\1367 = NAND(\1314, \1216)
\1370 = NAND(\1315, \1221)
\1373 = NAND(\1316, \1224)
\1376 = NAND(\1317, \1226)
\1379 = NAND(\1318, \1229)
\1383 = NAND(\1322, \1231)
\1386 = NOT(\1232)
\1387 = NAND(\1232, \990)
\1388 = NOT(\1235)
\1389 = NAND(\1235, \993)
\1390 = NAND(\1327, \1239)
\1393 = NAND(\1328, \1242)
\1396 = NOT(\1243)
\1397 = NAND(\1243, \1004)
\1398 = NOT(\1246)
\1399 = NAND(\1246, \1007)
\1409 = NOT(\1319)
\1412 = NAND(\649, \1346)
\1413 = NOT(\1334)
\1416 = BUFF(\1264)
\1419 = BUFF(\1264)
\1433 = NAND(\634, \1386)
\1434 = NAND(\637, \1388)
\1438 = NAND(\640, \1396)
\1439 = NAND(\646, \1398)
\1440 = NOT(\1344)
\1443 = NAND(\1355, \1148)
\1444 = NOT(\1355)
\1445 = NAND(\1352, \1149)
\1446 = NOT(\1352)
\1447 = NAND(\1358, \1151)
\1448 = NOT(\1358)
\1451 = NAND(\1361, \1152)
\1452 = NOT(\1361)
\1453 = NAND(\1367, \1153)
\1454 = NOT(\1367)
\1455 = NAND(\1364, \1154)
\1456 = NOT(\1364)
\1457 = NAND(\1373, \1156)
\1458 = NOT(\1373)
\1459 = NAND(\1379, \1157)
\1460 = NOT(\1379)
\1461 = NOT(\1383)
\1462 = NAND(\1393, \1161)
\1463 = NOT(\1393)
\1464 = NAND(\1345, \1412)
\1468 = NOT(\1370)
\1469 = NAND(\1370, \1222)
\1470 = NOT(\1376)
\1471 = NAND(\1376, \1227)
\1472 = NAND(\1387, \1433)
\1475 = NOT(\1390)
\1476 = NAND(\1390, \1240)
\1478 = NAND(\1389, \1434)
\1481 = NAND(\1399, \1439)
\1484 = NAND(\1397, \1438)
\1487 = NAND(\939, \1444)
\1488 = NAND(\935, \1446)
\1489 = NAND(\943, \1448)
\1490 = NOT(\1419)
\1491 = NOT(\1416)
\1492 = NAND(\947, \1452)
\1493 = NAND(\955, \1454)
\1494 = NAND(\951, \1456)
\1495 = NAND(\969, \1458)
\1496 = NAND(\977, \1460)
\1498 = NAND(\998, \1463)
\1499 = NOT(\1440)
\1500 = NAND(\965, \1468)
\1501 = NAND(\973, \1470)
\1504 = NAND(\994, \1475)
\1510 = NOT(\1464)
\1513 = NAND(\1443, \1487)
\1514 = NAND(\1445, \1488)
\1517 = NAND(\1447, \1489)
\1520 = NAND(\1451, \1492)
\1521 = NAND(\1453, \1493)
\1522 = NAND(\1455, \1494)
\1526 = NAND(\1457, \1495)
\1527 = NAND(\1459, \1496)
\1528 = NOT(\1472)
\1529 = NAND(\1462, \1498)
\1530 = NOT(\1478)
\1531 = NOT(\1481)
\1532 = NOT(\1484)
\1534 = NAND(\1471, \1501)
\1537 = NAND(\1469, \1500)
\1540 = NAND(\1476, \1504)
\1546 = NOT(\1513)
\1554 = NOT(\1521)
\1557 = NOT(\1526)
\1561 = NOT(\1520)
\1567 = NAND(\1484, \1531)
\1568 = NAND(\1481, \1532)
\1569 = NOT(\1510)
\1571 = NOT(\1527)
\1576 = NOT(\1529)
\1588 = BUFF(\1522)
\1591 = NOT(\1534)
\1593 = NOT(\1537)
\1594 = NAND(\1540, \1530)
\1595 = NOT(\1540)
\1596 = NAND(\1567, \1568)
\1600 = BUFF(\1517)
\1603 = BUFF(\1517)
\1606 = BUFF(\1522)
\1609 = BUFF(\1522)
\1612 = BUFF(\1514)
\1615 = BUFF(\1514)
\1620 = BUFF(\1557)
\1623 = BUFF(\1554)
\1635 = NOT(\1571)
\1636 = NAND(\1478, \1595)
\1638 = NAND(\1576, \1569)
\1639 = NOT(\1576)
\1640 = BUFF(\1561)
\1643 = BUFF(\1561)
\1647 = BUFF(\1546)
\1651 = BUFF(\1546)
\1658 = BUFF(\1554)
\1661 = BUFF(\1557)
\1664 = BUFF(\1557)
\1671 = NAND(\1596, \893)
\1672 = NOT(\1596)
\1675 = NOT(\1600)
\1677 = NOT(\1603)
\1678 = NAND(\1606, \1217)
\1679 = NOT(\1606)
\1680 = NAND(\1609, \1219)
\1681 = NOT(\1609)
\1682 = NOT(\1612)
\1683 = NOT(\1615)
\1685 = NAND(\1594, \1636)
\1688 = NAND(\1510, \1639)
\1697 = BUFF(\1588)
\1701 = BUFF(\1588)
\1706 = NAND(\643, \1672)
\1707 = NOT(\1643)
\1708 = NAND(\1647, \1675)
\1709 = NOT(\1647)
\1710 = NAND(\1651, \1677)
\1711 = NOT(\1651)
\1712 = NAND(\1028, \1679)
\1713 = NAND(\1031, \1681)
\1714 = BUFF(\1620)
\1717 = BUFF(\1620)
\1720 = NAND(\1658, \1593)
\1721 = NOT(\1658)
\1723 = NAND(\1638, \1688)
\1727 = NOT(\1661)
\1728 = NOT(\1640)
\1730 = NOT(\1664)
\1731 = BUFF(\1623)
\1734 = BUFF(\1623)
\1740 = NAND(\1685, \1528)
\1741 = NOT(\1685)
\1742 = NAND(\1671, \1706)
\1746 = NAND(\1600, \1709)
\1747 = NAND(\1603, \1711)
\1748 = NAND(\1678, \1712)
\1751 = NAND(\1680, \1713)
\1759 = NAND(\1537, \1721)
\1761 = NOT(\1697)
\1762 = NAND(\1697, \1727)
\1763 = NOT(\1701)
\1764 = NAND(\1701, \1730)
\1768 = NOT(\1717)
\1769 = NAND(\1472, \1741)
\1772 = NAND(\1723, \1413)
\1773 = NOT(\1723)
\1774 = NAND(\1708, \1746)
\1777 = NAND(\1710, \1747)
\1783 = NOT(\1731)
\1784 = NAND(\1731, \1682)
\1785 = NOT(\1714)
\1786 = NOT(\1734)
\1787 = NAND(\1734, \1683)
\1788 = NAND(\1720, \1759)
\1791 = NAND(\1661, \1761)
\1792 = NAND(\1664, \1763)
\1795 = NAND(\1751, \1155)
\1796 = NOT(\1751)
\1798 = NAND(\1740, \1769)
\1801 = NAND(\1334, \1773)
\1802 = NAND(\1742, \290)
\1807 = NOT(\1748)
\1808 = NAND(\1748, \1218)
\1809 = NAND(\1612, \1783)
\1810 = NAND(\1615, \1786)
\1812 = NAND(\1791, \1762)
\1815 = NAND(\1792, \1764)
\1818 = BUFF(\1742)
\1821 = NAND(\1777, \1490)
\1822 = NOT(\1777)
\1823 = NAND(\1774, \1491)
\1824 = NOT(\1774)
\1825 = NAND(\962, \1796)
\1826 = NAND(\1788, \1409)
\1827 = NOT(\1788)
\1830 = NAND(\1772, \1801)
\1837 = NAND(\959, \1807)
\1838 = NAND(\1809, \1784)
\1841 = NAND(\1810, \1787)
\1848 = NAND(\1419, \1822)
\1849 = NAND(\1416, \1824)
\1850 = NAND(\1795, \1825)
\1852 = NAND(\1319, \1827)
\1855 = NAND(\1815, \1707)
\1856 = NOT(\1815)
\1857 = NOT(\1818)
\1858 = NAND(\1798, \290)
\1864 = NOT(\1812)
\1865 = NAND(\1812, \1728)
\1866 = BUFF(\1798)
\1869 = BUFF(\1802)
\1872 = BUFF(\1802)
\1875 = NAND(\1808, \1837)
\1878 = NAND(\1821, \1848)
\1879 = NAND(\1823, \1849)
\1882 = NAND(\1841, \1768)
\1883 = NOT(\1841)
\1884 = NAND(\1826, \1852)
\1885 = NAND(\1643, \1856)
\1889 = NAND(\1830, \290)
\1895 = NOT(\1838)
\1896 = NAND(\1838, \1785)
\1897 = NAND(\1640, \1864)
\1898 = NOT(\1850)
\1902 = BUFF(\1830)
\1910 = NOT(\1878)
\1911 = NAND(\1717, \1883)
\1912 = NOT(\1884)
\1913 = NAND(\1855, \1885)
\1915 = NOT(\1866)
\1919 = NAND(\1872, \919)
\1920 = NOT(\1872)
\1921 = NAND(\1869, \920)
\1922 = NOT(\1869)
\1923 = NOT(\1875)
\1924 = NAND(\1714, \1895)
\1927 = BUFF(\1858)
\1930 = BUFF(\1858)
\1933 = NAND(\1865, \1897)
\1936 = NAND(\1882, \1911)
\1937 = NOT(\1898)
\1938 = NOT(\1902)
\1941 = NAND(\679, \1920)
\1942 = NAND(\676, \1922)
\1944 = BUFF(\1879)
\1947 = NOT(\1913)
\1950 = BUFF(\1889)
\1953 = BUFF(\1889)
\1958 = BUFF(\1879)
\1961 = NAND(\1896, \1924)
\1965 = AND(\1910, \601)
\1968 = AND(\602, \1912)
\1975 = NAND(\1930, \917)
\1976 = NOT(\1930)
\1977 = NAND(\1927, \918)
\1978 = NOT(\1927)
\1979 = NAND(\1919, \1941)
\1980 = NAND(\1921, \1942)
\1985 = NOT(\1933)
\1987 = NOT(\1936)
\1999 = NOT(\1944)
\2000 = NAND(\1944, \1937)
\2002 = NOT(\1947)
\2003 = NAND(\1947, \1499)
\2004 = NAND(\1953, \1350)
\2005 = NOT(\1953)
\2006 = NAND(\1950, \1351)
\2007 = NOT(\1950)
\2008 = NAND(\673, \1976)
\2009 = NAND(\670, \1978)
\2012 = NOT(\1979)
\2013 = NOT(\1958)
\2014 = NAND(\1958, \1923)
\2015 = NOT(\1961)
\2016 = NAND(\1961, \1635)
\2018 = NOT(\1965)
\2019 = NOT(\1968)
\2020 = NAND(\1898, \1999)
\2021 = NOT(\1987)
\2022 = NAND(\1987, \1591)
\2023 = NAND(\1440, \2002)
\2024 = NAND(\1261, \2005)
\2025 = NAND(\1258, \2007)
\2026 = NAND(\1975, \2008)
\2027 = NAND(\1977, \2009)
\2030 = NOT(\1980)
\2033 = BUFF(\1980)
\2036 = NAND(\1875, \2013)
\2037 = NAND(\1571, \2015)
\2038 = NAND(\2020, \2000)
\2039 = NAND(\1534, \2021)
\2040 = NAND(\2023, \2003)
\2041 = NAND(\2004, \2024)
\2042 = NAND(\2006, \2025)
\2047 = NOT(\2026)
\2052 = NAND(\2036, \2014)
\2055 = NAND(\2037, \2016)
\2060 = NOT(\2038)
\2061 = NAND(\2039, \2022)
\2062 = NAND(\2040, \290)
\2067 = NOT(\2041)
\2068 = NOT(\2027)
\2071 = BUFF(\2027)
\2076 = NOT(\2052)
\2077 = NOT(\2055)
\2078 = NAND(\2060, \290)
\2081 = NAND(\2061, \290)
\2086 = NOT(\2042)
\2089 = BUFF(\2042)
\2104 = AND(\2030, \2068)
\2119 = AND(\2033, \2068)
\2129 = AND(\2030, \2071)
\2143 = AND(\2033, \2071)
\2148 = BUFF(\2062)
\2151 = BUFF(\2062)
\2196 = BUFF(\2078)
\2199 = BUFF(\2078)
\2202 = BUFF(\2081)
\2205 = BUFF(\2081)
\2214 = NAND(\2151, \915)
\2215 = NOT(\2151)
\2216 = NAND(\2148, \916)
\2217 = NOT(\2148)
\2222 = NAND(\2199, \1348)
\2223 = NOT(\2199)
\2224 = NAND(\2196, \1349)
\2225 = NOT(\2196)
\2226 = NAND(\2205, \913)
\2227 = NOT(\2205)
\2228 = NAND(\2202, \914)
\2229 = NOT(\2202)
\2230 = NAND(\667, \2215)
\2231 = NAND(\664, \2217)
\2232 = NAND(\1255, \2223)
\2233 = NAND(\1252, \2225)
\2234 = NAND(\661, \2227)
\2235 = NAND(\658, \2229)
\2236 = NAND(\2214, \2230)
\2237 = NAND(\2216, \2231)
\2240 = NAND(\2222, \2232)
\2241 = NAND(\2224, \2233)
\2244 = NAND(\2226, \2234)
\2245 = NAND(\2228, \2235)
\2250 = NOT(\2236)
\2253 = NOT(\2240)
\2256 = NOT(\2244)
\2257 = NOT(\2237)
\2260 = BUFF(\2237)
\2263 = NOT(\2241)
\2266 = AND(\1164, \2241)
\2269 = NOT(\2245)
\2272 = AND(\1168, \2245)
\2279 = NAND(\2067, \2012, \2047, \2250, \899, \2256, \2253, \903)
\2286 = BUFF(\2266)
\2297 = BUFF(\2266)
\2315 = BUFF(\2272)
\2326 = BUFF(\2272)
\2340 = AND(\2086, \2257)
\2353 = AND(\2089, \2257)
\2361 = AND(\2086, \2260)
\2375 = AND(\2089, \2260)
\2384 = AND(\338, \2279, \313, \313)
\2385 = AND(\1163, \2263)
\2386 = AND(\1164, \2263)
\2426 = AND(\1167, \2269)
\2427 = AND(\1168, \2269)
\2537 = NAND(\2286, \2315, \2361, \2104, \1171)
\2540 = NAND(\2286, \2315, \2340, \2129, \1171)
\2543 = NAND(\2286, \2315, \2340, \2119, \1171)
\2546 = NAND(\2286, \2315, \2353, \2104, \1171)
\2549 = NAND(\2297, \2315, \2375, \2119, \1188)
\2552 = NAND(\2297, \2326, \2361, \2143, \1188)
\2555 = NAND(\2297, \2326, \2375, \2129, \1188)
\2558 = AND(\2286, \2315, \2361, \2104, \1171)
\2561 = AND(\2286, \2315, \2340, \2129, \1171)
\2564 = AND(\2286, \2315, \2340, \2119, \1171)
\2567 = AND(\2286, \2315, \2353, \2104, \1171)
\2570 = AND(\2297, \2315, \2375, \2119, \1188)
\2573 = AND(\2297, \2326, \2361, \2143, \1188)
\2576 = AND(\2297, \2326, \2375, \2129, \1188)
\2594 = NAND(\2286, \2427, \2361, \2129, \1171)
\2597 = NAND(\2297, \2427, \2361, \2119, \1171)
\2600 = NAND(\2297, \2427, \2375, \2104, \1171)
\2603 = NAND(\2297, \2427, \2340, \2143, \1171)
\2606 = NAND(\2297, \2427, \2353, \2129, \1188)
\2611 = NAND(\2386, \2326, \2361, \2129, \1188)
\2614 = NAND(\2386, \2326, \2361, \2119, \1188)
\2617 = NAND(\2386, \2326, \2375, \2104, \1188)
\2620 = NAND(\2386, \2326, \2353, \2129, \1188)
\2627 = NAND(\2297, \2427, \2340, \2104, \926)
\2628 = NAND(\2386, \2326, \2340, \2104, \926)
\2629 = NAND(\2386, \2427, \2361, \2104, \926)
\2630 = NAND(\2386, \2427, \2340, \2129, \926)
\2631 = NAND(\2386, \2427, \2340, \2119, \926)
\2632 = NAND(\2386, \2427, \2353, \2104, \926)
\2633 = NAND(\2386, \2426, \2340, \2104, \926)
\2634 = NAND(\2385, \2427, \2340, \2104, \926)
\2639 = AND(\2286, \2427, \2361, \2129, \1171)
\2642 = AND(\2297, \2427, \2361, \2119, \1171)
\2645 = AND(\2297, \2427, \2375, \2104, \1171)
\2648 = AND(\2297, \2427, \2340, \2143, \1171)
\2651 = AND(\2297, \2427, \2353, \2129, \1188)
\2655 = AND(\2386, \2326, \2361, \2129, \1188)
\2658 = AND(\2386, \2326, \2361, \2119, \1188)
\2661 = AND(\2386, \2326, \2375, \2104, \1188)
\2664 = AND(\2386, \2326, \2353, \2129, \1188)
\2669 = NAND(\2558, \534)
\2670 = NOT(\2558)
\2671 = NAND(\2561, \535)
\2672 = NOT(\2561)
\2673 = NAND(\2564, \536)
\2674 = NOT(\2564)
\2675 = NAND(\2567, \537)
\2676 = NOT(\2567)
\2682 = NAND(\2570, \543)
\2683 = NOT(\2570)
\2688 = NAND(\2573, \548)
\2689 = NOT(\2573)
\2690 = NAND(\2576, \549)
\2691 = NOT(\2576)
\2710 = AND(\2627, \2628, \2629, \2630, \2631, \2632, \2633, \2634)
\2720 = NAND(\343, \2670)
\2721 = NAND(\346, \2672)
\2722 = NAND(\349, \2674)
\2723 = NAND(\352, \2676)
\2724 = NAND(\2639, \538)
\2725 = NOT(\2639)
\2726 = NAND(\2642, \539)
\2727 = NOT(\2642)
\2728 = NAND(\2645, \540)
\2729 = NOT(\2645)
\2730 = NAND(\2648, \541)
\2731 = NOT(\2648)
\2732 = NAND(\2651, \542)
\2733 = NOT(\2651)
\2734 = NAND(\370, \2683)
\2735 = NAND(\2655, \544)
\2736 = NOT(\2655)
\2737 = NAND(\2658, \545)
\2738 = NOT(\2658)
\2739 = NAND(\2661, \546)
\2740 = NOT(\2661)
\2741 = NAND(\2664, \547)
\2742 = NOT(\2664)
\2743 = NAND(\385, \2689)
\2744 = NAND(\388, \2691)
\2745 = NAND(\2537, \2540, \2543, \2546, \2594, \2597, \2600, \2603)
\2746 = NAND(\2606, \2549, \2611, \2614, \2617, \2620, \2552, \2555)
\2747 = AND(\2537, \2540, \2543, \2546, \2594, \2597, \2600, \2603)
\2750 = AND(\2606, \2549, \2611, \2614, \2617, \2620, \2552, \2555)
\2753 = NAND(\2669, \2720)
\2754 = NAND(\2671, \2721)
\2755 = NAND(\2673, \2722)
\2756 = NAND(\2675, \2723)
\2757 = NAND(\355, \2725)
\2758 = NAND(\358, \2727)
\2759 = NAND(\361, \2729)
\2760 = NAND(\364, \2731)
\2761 = NAND(\367, \2733)
\2762 = NAND(\2682, \2734)
\2763 = NAND(\373, \2736)
\2764 = NAND(\376, \2738)
\2765 = NAND(\379, \2740)
\2766 = NAND(\382, \2742)
\2767 = NAND(\2688, \2743)
\2768 = NAND(\2690, \2744)
\2773 = AND(\2745, \275)
\2776 = AND(\2746, \276)
\2779 = NAND(\2724, \2757)
\2780 = NAND(\2726, \2758)
\2781 = NAND(\2728, \2759)
\2782 = NAND(\2730, \2760)
\2783 = NAND(\2732, \2761)
\2784 = NAND(\2735, \2763)
\2785 = NAND(\2737, \2764)
\2786 = NAND(\2739, \2765)
\2787 = NAND(\2741, \2766)
\2788 = AND(\2747, \2750, \2710)
\2789 = NAND(\2747, \2750)
\2800 = AND(\338, \2279, \99, \2788)
\2807 = NAND(\2773, \2018)
\2808 = NOT(\2773)
\2809 = NAND(\2776, \2019)
\2810 = NOT(\2776)
\2811 = NOR(\2384, \2800)
\2812 = AND(\897, \283, \2789)
\2815 = AND(\76, \283, \2789)
\2818 = AND(\82, \283, \2789)
\2821 = AND(\85, \283, \2789)
\2824 = AND(\898, \283, \2789)
\2827 = NAND(\1965, \2808)
\2828 = NAND(\1968, \2810)
\2829 = AND(\79, \283, \2789)
\2843 = NAND(\2807, \2827)
\2846 = NAND(\2809, \2828)
\2850 = NAND(\2812, \2076)
\2851 = NAND(\2815, \2077)
\2852 = NAND(\2818, \1915)
\2853 = NAND(\2821, \1857)
\2854 = NAND(\2824, \1938)
\2857 = NOT(\2812)
\2858 = NOT(\2815)
\2859 = NOT(\2818)
\2860 = NOT(\2821)
\2861 = NOT(\2824)
\2862 = NOT(\2829)
\2863 = NAND(\2829, \1985)
\2866 = NAND(\2052, \2857)
\2867 = NAND(\2055, \2858)
\2868 = NAND(\1866, \2859)
\2869 = NAND(\1818, \2860)
\2870 = NAND(\1902, \2861)
\2871 = NAND(\2843, \886)
\2872 = NOT(\2843)
\2873 = NAND(\2846, \887)
\2874 = NOT(\2846)
\2875 = NAND(\1933, \2862)
\2876 = NAND(\2866, \2850)
\2877 = NAND(\2867, \2851)
\2878 = NAND(\2868, \2852)
\2879 = NAND(\2869, \2853)
\2880 = NAND(\2870, \2854)
\2881 = NAND(\682, \2872)
\2882 = NAND(\685, \2874)
\2883 = NAND(\2875, \2863)
\2886 = AND(\2876, \550)
\2887 = AND(\551, \2877)
\2888 = AND(\553, \2878)
\2889 = AND(\2879, \554)
\2890 = AND(\555, \2880)
\2891 = NAND(\2871, \2881)
\2892 = NAND(\2873, \2882)
\2895 = NAND(\2883, \1461)
\2896 = NOT(\2883)
\2897 = NAND(\1383, \2896)
\2898 = NAND(\2895, \2897)
\2899 = AND(\2898, \552)

1570
ISCAS85/new/c2670.bench
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1745
ISCAS85/new/c3540.bench
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207
ISCAS85/new/c432.bench
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@ -1,207 +0,0 @@
# c\432
INPUT(\1)
INPUT(\4)
INPUT(\8)
INPUT(\11)
INPUT(\14)
INPUT(\17)
INPUT(\21)
INPUT(\24)
INPUT(\27)
INPUT(\30)
INPUT(\34)
INPUT(\37)
INPUT(\40)
INPUT(\43)
INPUT(\47)
INPUT(\50)
INPUT(\53)
INPUT(\56)
INPUT(\60)
INPUT(\63)
INPUT(\66)
INPUT(\69)
INPUT(\73)
INPUT(\76)
INPUT(\79)
INPUT(\82)
INPUT(\86)
INPUT(\89)
INPUT(\92)
INPUT(\95)
INPUT(\99)
INPUT(\102)
INPUT(\105)
INPUT(\108)
INPUT(\112)
INPUT(\115)
OUTPUT(\223)
OUTPUT(\329)
OUTPUT(\370)
OUTPUT(\421)
OUTPUT(\430)
OUTPUT(\431)
OUTPUT(\432)
\118 = NOT(\1)
\119 = NOT(\4)
\122 = NOT(\11)
\123 = NOT(\17)
\126 = NOT(\24)
\127 = NOT(\30)
\130 = NOT(\37)
\131 = NOT(\43)
\134 = NOT(\50)
\135 = NOT(\56)
\138 = NOT(\63)
\139 = NOT(\69)
\142 = NOT(\76)
\143 = NOT(\82)
\146 = NOT(\89)
\147 = NOT(\95)
\150 = NOT(\102)
\151 = NOT(\108)
\154 = NAND(\118, \4)
\157 = NOR(\8, \119)
\158 = NOR(\14, \119)
\159 = NAND(\122, \17)
\162 = NAND(\126, \30)
\165 = NAND(\130, \43)
\168 = NAND(\134, \56)
\171 = NAND(\138, \69)
\174 = NAND(\142, \82)
\177 = NAND(\146, \95)
\180 = NAND(\150, \108)
\183 = NOR(\21, \123)
\184 = NOR(\27, \123)
\185 = NOR(\34, \127)
\186 = NOR(\40, \127)
\187 = NOR(\47, \131)
\188 = NOR(\53, \131)
\189 = NOR(\60, \135)
\190 = NOR(\66, \135)
\191 = NOR(\73, \139)
\192 = NOR(\79, \139)
\193 = NOR(\86, \143)
\194 = NOR(\92, \143)
\195 = NOR(\99, \147)
\196 = NOR(\105, \147)
\197 = NOR(\112, \151)
\198 = NOR(\115, \151)
\199 = AND(\154, \159, \162, \165, \168, \171, \174, \177, \180)
\203 = NOT(\199)
\213 = NOT(\199)
\223 = NOT(\199)
\224 = XOR(\203, \154)
\227 = XOR(\203, \159)
\230 = XOR(\203, \162)
\233 = XOR(\203, \165)
\236 = XOR(\203, \168)
\239 = XOR(\203, \171)
\242 = NAND(\1, \213)
\243 = XOR(\203, \174)
\246 = NAND(\213, \11)
\247 = XOR(\203, \177)
\250 = NAND(\213, \24)
\251 = XOR(\203, \180)
\254 = NAND(\213, \37)
\255 = NAND(\213, \50)
\256 = NAND(\213, \63)
\257 = NAND(\213, \76)
\258 = NAND(\213, \89)
\259 = NAND(\213, \102)
\260 = NAND(\224, \157)
\263 = NAND(\224, \158)
\264 = NAND(\227, \183)
\267 = NAND(\230, \185)
\270 = NAND(\233, \187)
\273 = NAND(\236, \189)
\276 = NAND(\239, \191)
\279 = NAND(\243, \193)
\282 = NAND(\247, \195)
\285 = NAND(\251, \197)
\288 = NAND(\227, \184)
\289 = NAND(\230, \186)
\290 = NAND(\233, \188)
\291 = NAND(\236, \190)
\292 = NAND(\239, \192)
\293 = NAND(\243, \194)
\294 = NAND(\247, \196)
\295 = NAND(\251, \198)
\296 = AND(\260, \264, \267, \270, \273, \276, \279, \282, \285)
\300 = NOT(\263)
\301 = NOT(\288)
\302 = NOT(\289)
\303 = NOT(\290)
\304 = NOT(\291)
\305 = NOT(\292)
\306 = NOT(\293)
\307 = NOT(\294)
\308 = NOT(\295)
\309 = NOT(\296)
\319 = NOT(\296)
\329 = NOT(\296)
\330 = XOR(\309, \260)
\331 = XOR(\309, \264)
\332 = XOR(\309, \267)
\333 = XOR(\309, \270)
\334 = NAND(\8, \319)
\335 = XOR(\309, \273)
\336 = NAND(\319, \21)
\337 = XOR(\309, \276)
\338 = NAND(\319, \34)
\339 = XOR(\309, \279)
\340 = NAND(\319, \47)
\341 = XOR(\309, \282)
\342 = NAND(\319, \60)
\343 = XOR(\309, \285)
\344 = NAND(\319, \73)
\345 = NAND(\319, \86)
\346 = NAND(\319, \99)
\347 = NAND(\319, \112)
\348 = NAND(\330, \300)
\349 = NAND(\331, \301)
\350 = NAND(\332, \302)
\351 = NAND(\333, \303)
\352 = NAND(\335, \304)
\353 = NAND(\337, \305)
\354 = NAND(\339, \306)
\355 = NAND(\341, \307)
\356 = NAND(\343, \308)
\357 = AND(\348, \349, \350, \351, \352, \353, \354, \355, \356)
\360 = NOT(\357)
\370 = NOT(\357)
\371 = NAND(\14, \360)
\372 = NAND(\360, \27)
\373 = NAND(\360, \40)
\374 = NAND(\360, \53)
\375 = NAND(\360, \66)
\376 = NAND(\360, \79)
\377 = NAND(\360, \92)
\378 = NAND(\360, \105)
\379 = NAND(\360, \115)
\380 = NAND(\4, \242, \334, \371)
\381 = NAND(\246, \336, \372, \17)
\386 = NAND(\250, \338, \373, \30)
\393 = NAND(\254, \340, \374, \43)
\399 = NAND(\255, \342, \375, \56)
\404 = NAND(\256, \344, \376, \69)
\407 = NAND(\257, \345, \377, \82)
\411 = NAND(\258, \346, \378, \95)
\414 = NAND(\259, \347, \379, \108)
\415 = NOT(\380)
\416 = AND(\381, \386, \393, \399, \404, \407, \411, \414)
\417 = NOT(\393)
\418 = NOT(\404)
\419 = NOT(\407)
\420 = NOT(\411)
\421 = NOR(\415, \416)
\422 = NAND(\386, \417)
\425 = NAND(\386, \393, \418, \399)
\428 = NAND(\399, \393, \419)
\429 = NAND(\386, \393, \407, \420)
\430 = NAND(\381, \386, \422, \399)
\431 = NAND(\381, \386, \425, \428)
\432 = NAND(\381, \422, \425, \429)

279
ISCAS85/new/c499.bench
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@ -1,279 +0,0 @@
# c\499
INPUT(\1)
INPUT(\5)
INPUT(\9)
INPUT(\13)
INPUT(\17)
INPUT(\21)
INPUT(\25)
INPUT(\29)
INPUT(\33)
INPUT(\37)
INPUT(\41)
INPUT(\45)
INPUT(\49)
INPUT(\53)
INPUT(\57)
INPUT(\61)
INPUT(\65)
INPUT(\69)
INPUT(\73)
INPUT(\77)
INPUT(\81)
INPUT(\85)
INPUT(\89)
INPUT(\93)
INPUT(\97)
INPUT(\101)
INPUT(\105)
INPUT(\109)
INPUT(\113)
INPUT(\117)
INPUT(\121)
INPUT(\125)
INPUT(\129)
INPUT(\130)
INPUT(\131)
INPUT(\132)
INPUT(\133)
INPUT(\134)
INPUT(\135)
INPUT(\136)
INPUT(\137)
OUTPUT(\724)
OUTPUT(\725)
OUTPUT(\726)
OUTPUT(\727)
OUTPUT(\728)
OUTPUT(\729)
OUTPUT(\730)
OUTPUT(\731)
OUTPUT(\732)
OUTPUT(\733)
OUTPUT(\734)
OUTPUT(\735)
OUTPUT(\736)
OUTPUT(\737)
OUTPUT(\738)
OUTPUT(\739)
OUTPUT(\740)
OUTPUT(\741)
OUTPUT(\742)
OUTPUT(\743)
OUTPUT(\744)
OUTPUT(\745)
OUTPUT(\746)
OUTPUT(\747)
OUTPUT(\748)
OUTPUT(\749)
OUTPUT(\750)
OUTPUT(\751)
OUTPUT(\752)
OUTPUT(\753)
OUTPUT(\754)
OUTPUT(\755)
\250 = XOR(\1, \5)
\251 = XOR(\9, \13)
\252 = XOR(\17, \21)
\253 = XOR(\25, \29)
\254 = XOR(\33, \37)
\255 = XOR(\41, \45)
\256 = XOR(\49, \53)
\257 = XOR(\57, \61)
\258 = XOR(\65, \69)
\259 = XOR(\73, \77)
\260 = XOR(\81, \85)
\261 = XOR(\89, \93)
\262 = XOR(\97, \101)
\263 = XOR(\105, \109)
\264 = XOR(\113, \117)
\265 = XOR(\121, \125)
\266 = AND(\129, \137)
\267 = AND(\130, \137)
\268 = AND(\131, \137)
\269 = AND(\132, \137)
\270 = AND(\133, \137)
\271 = AND(\134, \137)
\272 = AND(\135, \137)
\273 = AND(\136, \137)
\274 = XOR(\1, \17)
\275 = XOR(\33, \49)
\276 = XOR(\5, \21)
\277 = XOR(\37, \53)
\278 = XOR(\9, \25)
\279 = XOR(\41, \57)
\280 = XOR(\13, \29)
\281 = XOR(\45, \61)
\282 = XOR(\65, \81)
\283 = XOR(\97, \113)
\284 = XOR(\69, \85)
\285 = XOR(\101, \117)
\286 = XOR(\73, \89)
\287 = XOR(\105, \121)
\288 = XOR(\77, \93)
\289 = XOR(\109, \125)
\290 = XOR(\250, \251)
\293 = XOR(\252, \253)
\296 = XOR(\254, \255)
\299 = XOR(\256, \257)
\302 = XOR(\258, \259)
\305 = XOR(\260, \261)
\308 = XOR(\262, \263)
\311 = XOR(\264, \265)
\314 = XOR(\274, \275)
\315 = XOR(\276, \277)
\316 = XOR(\278, \279)
\317 = XOR(\280, \281)
\318 = XOR(\282, \283)
\319 = XOR(\284, \285)
\320 = XOR(\286, \287)
\321 = XOR(\288, \289)
\338 = XOR(\290, \293)
\339 = XOR(\296, \299)
\340 = XOR(\290, \296)
\341 = XOR(\293, \299)
\342 = XOR(\302, \305)
\343 = XOR(\308, \311)
\344 = XOR(\302, \308)
\345 = XOR(\305, \311)
\346 = XOR(\266, \342)
\347 = XOR(\267, \343)
\348 = XOR(\268, \344)
\349 = XOR(\269, \345)
\350 = XOR(\270, \338)
\351 = XOR(\271, \339)
\352 = XOR(\272, \340)
\353 = XOR(\273, \341)
\354 = XOR(\314, \346)
\367 = XOR(\315, \347)
\380 = XOR(\316, \348)
\393 = XOR(\317, \349)
\406 = XOR(\318, \350)
\419 = XOR(\319, \351)
\432 = XOR(\320, \352)
\445 = XOR(\321, \353)
\554 = NOT(\354)
\555 = NOT(\367)
\556 = NOT(\380)
\557 = NOT(\354)
\558 = NOT(\367)
\559 = NOT(\393)
\560 = NOT(\354)
\561 = NOT(\380)
\562 = NOT(\393)
\563 = NOT(\367)
\564 = NOT(\380)
\565 = NOT(\393)
\566 = NOT(\419)
\567 = NOT(\445)
\568 = NOT(\419)
\569 = NOT(\432)
\570 = NOT(\406)
\571 = NOT(\445)
\572 = NOT(\406)
\573 = NOT(\432)
\574 = NOT(\406)
\575 = NOT(\419)
\576 = NOT(\432)
\577 = NOT(\406)
\578 = NOT(\419)
\579 = NOT(\445)
\580 = NOT(\406)
\581 = NOT(\432)
\582 = NOT(\445)
\583 = NOT(\419)
\584 = NOT(\432)
\585 = NOT(\445)
\586 = NOT(\367)
\587 = NOT(\393)
\588 = NOT(\367)
\589 = NOT(\380)
\590 = NOT(\354)
\591 = NOT(\393)
\592 = NOT(\354)
\593 = NOT(\380)
\594 = AND(\554, \555, \556, \393)
\595 = AND(\557, \558, \380, \559)
\596 = AND(\560, \367, \561, \562)
\597 = AND(\354, \563, \564, \565)
\598 = AND(\574, \575, \576, \445)
\599 = AND(\577, \578, \432, \579)
\600 = AND(\580, \419, \581, \582)
\601 = AND(\406, \583, \584, \585)
\602 = OR(\594, \595, \596, \597)
\607 = OR(\598, \599, \600, \601)
\620 = AND(\406, \566, \432, \567, \602)
\625 = AND(\406, \568, \569, \445, \602)
\630 = AND(\570, \419, \432, \571, \602)
\635 = AND(\572, \419, \573, \445, \602)
\640 = AND(\354, \586, \380, \587, \607)
\645 = AND(\354, \588, \589, \393, \607)
\650 = AND(\590, \367, \380, \591, \607)
\655 = AND(\592, \367, \593, \393, \607)
\692 = AND(\354, \620)
\693 = AND(\367, \620)
\694 = AND(\380, \620)
\695 = AND(\393, \620)
\696 = AND(\354, \625)
\697 = AND(\367, \625)
\698 = AND(\380, \625)
\699 = AND(\393, \625)
\700 = AND(\354, \630)
\701 = AND(\367, \630)
\702 = AND(\380, \630)
\703 = AND(\393, \630)
\704 = AND(\354, \635)
\705 = AND(\367, \635)
\706 = AND(\380, \635)
\707 = AND(\393, \635)
\708 = AND(\406, \640)
\709 = AND(\419, \640)
\710 = AND(\432, \640)
\711 = AND(\445, \640)
\712 = AND(\406, \645)
\713 = AND(\419, \645)
\714 = AND(\432, \645)
\715 = AND(\445, \645)
\716 = AND(\406, \650)
\717 = AND(\419, \650)
\718 = AND(\432, \650)
\719 = AND(\445, \650)
\720 = AND(\406, \655)
\721 = AND(\419, \655)
\722 = AND(\432, \655)
\723 = AND(\445, \655)
\724 = XOR(\1, \692)
\725 = XOR(\5, \693)
\726 = XOR(\9, \694)
\727 = XOR(\13, \695)
\728 = XOR(\17, \696)
\729 = XOR(\21, \697)
\730 = XOR(\25, \698)
\731 = XOR(\29, \699)
\732 = XOR(\33, \700)
\733 = XOR(\37, \701)
\734 = XOR(\41, \702)
\735 = XOR(\45, \703)
\736 = XOR(\49, \704)
\737 = XOR(\53, \705)
\738 = XOR(\57, \706)
\739 = XOR(\61, \707)
\740 = XOR(\65, \708)
\741 = XOR(\69, \709)
\742 = XOR(\73, \710)
\743 = XOR(\77, \711)
\744 = XOR(\81, \712)
\745 = XOR(\85, \713)
\746 = XOR(\89, \714)
\747 = XOR(\93, \715)
\748 = XOR(\97, \716)
\749 = XOR(\101, \717)
\750 = XOR(\105, \718)
\751 = XOR(\109, \719)
\752 = XOR(\113, \720)
\753 = XOR(\117, \721)
\754 = XOR(\121, \722)
\755 = XOR(\125, \723)

2612
ISCAS85/new/c5315.bench
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2484
ISCAS85/new/c6288.bench
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3831
ISCAS85/new/c7552.bench
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473
ISCAS85/new/c880.bench
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@ -1,473 +0,0 @@
# c\880
INPUT(\1)
INPUT(\8)
INPUT(\13)
INPUT(\17)
INPUT(\26)
INPUT(\29)
INPUT(\36)
INPUT(\42)
INPUT(\51)
INPUT(\55)
INPUT(\59)
INPUT(\68)
INPUT(\72)
INPUT(\73)
INPUT(\74)
INPUT(\75)
INPUT(\80)
INPUT(\85)
INPUT(\86)
INPUT(\87)
INPUT(\88)
INPUT(\89)
INPUT(\90)
INPUT(\91)
INPUT(\96)
INPUT(\101)
INPUT(\106)
INPUT(\111)
INPUT(\116)
INPUT(\121)
INPUT(\126)
INPUT(\130)
INPUT(\135)
INPUT(\138)
INPUT(\143)
INPUT(\146)
INPUT(\149)
INPUT(\152)
INPUT(\153)
INPUT(\156)
INPUT(\159)
INPUT(\165)
INPUT(\171)
INPUT(\177)
INPUT(\183)
INPUT(\189)
INPUT(\195)
INPUT(\201)
INPUT(\207)
INPUT(\210)
INPUT(\219)
INPUT(\228)
INPUT(\237)
INPUT(\246)
INPUT(\255)
INPUT(\259)
INPUT(\260)
INPUT(\261)
INPUT(\267)
INPUT(\268)
OUTPUT(\388)
OUTPUT(\389)
OUTPUT(\390)
OUTPUT(\391)
OUTPUT(\418)
OUTPUT(\419)
OUTPUT(\420)
OUTPUT(\421)
OUTPUT(\422)
OUTPUT(\423)
OUTPUT(\446)
OUTPUT(\447)
OUTPUT(\448)
OUTPUT(\449)
OUTPUT(\450)
OUTPUT(\767)
OUTPUT(\768)
OUTPUT(\850)
OUTPUT(\863)
OUTPUT(\864)
OUTPUT(\865)
OUTPUT(\866)
OUTPUT(\874)
OUTPUT(\878)
OUTPUT(\879)
OUTPUT(\880)
\269 = NAND(\1, \8, \13, \17)
\270 = NAND(\1, \26, \13, \17)
\273 = AND(\29, \36, \42)
\276 = AND(\1, \26, \51)
\279 = NAND(\1, \8, \51, \17)
\280 = NAND(\1, \8, \13, \55)
\284 = NAND(\59, \42, \68, \72)
\285 = NAND(\29, \68)
\286 = NAND(\59, \68, \74)
\287 = AND(\29, \75, \80)
\290 = AND(\29, \75, \42)
\291 = AND(\29, \36, \80)
\292 = AND(\29, \36, \42)
\293 = AND(\59, \75, \80)
\294 = AND(\59, \75, \42)
\295 = AND(\59, \36, \80)
\296 = AND(\59, \36, \42)
\297 = AND(\85, \86)
\298 = OR(\87, \88)
\301 = NAND(\91, \96)
\302 = OR(\91, \96)
\303 = NAND(\101, \106)
\304 = OR(\101, \106)
\305 = NAND(\111, \116)
\306 = OR(\111, \116)
\307 = NAND(\121, \126)
\308 = OR(\121, \126)
\309 = AND(\8, \138)
\310 = NOT(\268)
\316 = AND(\51, \138)
\317 = AND(\17, \138)
\318 = AND(\152, \138)
\319 = NAND(\59, \156)
\322 = NOR(\17, \42)
\323 = AND(\17, \42)
\324 = NAND(\159, \165)
\325 = OR(\159, \165)
\326 = NAND(\171, \177)
\327 = OR(\171, \177)
\328 = NAND(\183, \189)
\329 = OR(\183, \189)
\330 = NAND(\195, \201)
\331 = OR(\195, \201)
\332 = AND(\210, \91)
\333 = AND(\210, \96)
\334 = AND(\210, \101)
\335 = AND(\210, \106)
\336 = AND(\210, \111)
\337 = AND(\255, \259)
\338 = AND(\210, \116)
\339 = AND(\255, \260)
\340 = AND(\210, \121)
\341 = AND(\255, \267)
\342 = NOT(\269)
\343 = NOT(\273)
\344 = OR(\270, \273)
\345 = NOT(\276)
\346 = NOT(\276)
\347 = NOT(\279)
\348 = NOR(\280, \284)
\349 = OR(\280, \285)
\350 = OR(\280, \286)
\351 = NOT(\293)
\352 = NOT(\294)
\353 = NOT(\295)
\354 = NOT(\296)
\355 = NAND(\89, \298)
\356 = AND(\90, \298)
\357 = NAND(\301, \302)
\360 = NAND(\303, \304)
\363 = NAND(\305, \306)
\366 = NAND(\307, \308)
\369 = NOT(\310)
\375 = NOR(\322, \323)
\376 = NAND(\324, \325)
\379 = NAND(\326, \327)
\382 = NAND(\328, \329)
\385 = NAND(\330, \331)
\388 = BUFF(\290)
\389 = BUFF(\291)
\390 = BUFF(\292)
\391 = BUFF(\297)
\392 = OR(\270, \343)
\393 = NOT(\345)
\399 = NOT(\346)
\400 = AND(\348, \73)
\401 = NOT(\349)
\402 = NOT(\350)
\403 = NOT(\355)
\404 = NOT(\357)
\405 = NOT(\360)
\406 = AND(\357, \360)
\407 = NOT(\363)
\408 = NOT(\366)
\409 = AND(\363, \366)
\410 = NAND(\347, \352)
\411 = NOT(\376)
\412 = NOT(\379)
\413 = AND(\376, \379)
\414 = NOT(\382)
\415 = NOT(\385)
\416 = AND(\382, \385)
\417 = AND(\210, \369)
\418 = BUFF(\342)
\419 = BUFF(\344)
\420 = BUFF(\351)
\421 = BUFF(\353)
\422 = BUFF(\354)
\423 = BUFF(\356)
\424 = NOT(\400)
\425 = AND(\404, \405)
\426 = AND(\407, \408)
\427 = AND(\319, \393, \55)
\432 = AND(\393, \17, \287)
\437 = NAND(\393, \287, \55)
\442 = NAND(\375, \59, \156, \393)
\443 = NAND(\393, \319, \17)
\444 = AND(\411, \412)
\445 = AND(\414, \415)
\446 = BUFF(\392)
\447 = BUFF(\399)
\448 = BUFF(\401)
\449 = BUFF(\402)
\450 = BUFF(\403)
\451 = NOT(\424)
\460 = NOR(\406, \425)
\463 = NOR(\409, \426)
\466 = NAND(\442, \410)
\475 = AND(\143, \427)
\476 = AND(\310, \432)
\477 = AND(\146, \427)
\478 = AND(\310, \432)
\479 = AND(\149, \427)
\480 = AND(\310, \432)
\481 = AND(\153, \427)
\482 = AND(\310, \432)
\483 = NAND(\443, \1)
\488 = OR(\369, \437)
\489 = OR(\369, \437)
\490 = OR(\369, \437)
\491 = OR(\369, \437)
\492 = NOR(\413, \444)
\495 = NOR(\416, \445)
\498 = NAND(\130, \460)
\499 = OR(\130, \460)
\500 = NAND(\463, \135)
\501 = OR(\463, \135)
\502 = AND(\91, \466)
\503 = NOR(\475, \476)
\504 = AND(\96, \466)
\505 = NOR(\477, \478)
\506 = AND(\101, \466)
\507 = NOR(\479, \480)
\508 = AND(\106, \466)
\509 = NOR(\481, \482)
\510 = AND(\143, \483)
\511 = AND(\111, \466)
\512 = AND(\146, \483)
\513 = AND(\116, \466)
\514 = AND(\149, \483)
\515 = AND(\121, \466)
\516 = AND(\153, \483)
\517 = AND(\126, \466)
\518 = NAND(\130, \492)
\519 = OR(\130, \492)
\520 = NAND(\495, \207)
\521 = OR(\495, \207)
\522 = AND(\451, \159)
\523 = AND(\451, \165)
\524 = AND(\451, \171)
\525 = AND(\451, \177)
\526 = AND(\451, \183)
\527 = NAND(\451, \189)
\528 = NAND(\451, \195)
\529 = NAND(\451, \201)
\530 = NAND(\498, \499)
\533 = NAND(\500, \501)
\536 = NOR(\309, \502)
\537 = NOR(\316, \504)
\538 = NOR(\317, \506)
\539 = NOR(\318, \508)
\540 = NOR(\510, \511)
\541 = NOR(\512, \513)
\542 = NOR(\514, \515)
\543 = NOR(\516, \517)
\544 = NAND(\518, \519)
\547 = NAND(\520, \521)
\550 = NOT(\530)
\551 = NOT(\533)
\552 = AND(\530, \533)
\553 = NAND(\536, \503)
\557 = NAND(\537, \505)
\561 = NAND(\538, \507)
\565 = NAND(\539, \509)
\569 = NAND(\488, \540)
\573 = NAND(\489, \541)
\577 = NAND(\490, \542)
\581 = NAND(\491, \543)
\585 = NOT(\544)
\586 = NOT(\547)
\587 = AND(\544, \547)
\588 = AND(\550, \551)
\589 = AND(\585, \586)
\590 = NAND(\553, \159)
\593 = OR(\553, \159)
\596 = AND(\246, \553)
\597 = NAND(\557, \165)
\600 = OR(\557, \165)
\605 = AND(\246, \557)
\606 = NAND(\561, \171)
\609 = OR(\561, \171)
\615 = AND(\246, \561)
\616 = NAND(\565, \177)
\619 = OR(\565, \177)
\624 = AND(\246, \565)
\625 = NAND(\569, \183)
\628 = OR(\569, \183)
\631 = AND(\246, \569)
\632 = NAND(\573, \189)
\635 = OR(\573, \189)
\640 = AND(\246, \573)
\641 = NAND(\577, \195)
\644 = OR(\577, \195)
\650 = AND(\246, \577)
\651 = NAND(\581, \201)
\654 = OR(\581, \201)
\659 = AND(\246, \581)
\660 = NOR(\552, \588)
\661 = NOR(\587, \589)
\662 = NOT(\590)
\665 = AND(\593, \590)
\669 = NOR(\596, \522)
\670 = NOT(\597)
\673 = AND(\600, \597)
\677 = NOR(\605, \523)
\678 = NOT(\606)
\682 = AND(\609, \606)
\686 = NOR(\615, \524)
\687 = NOT(\616)
\692 = AND(\619, \616)
\696 = NOR(\624, \525)
\697 = NOT(\625)
\700 = AND(\628, \625)
\704 = NOR(\631, \526)
\705 = NOT(\632)
\708 = AND(\635, \632)
\712 = NOR(\337, \640)
\713 = NOT(\641)
\717 = AND(\644, \641)
\721 = NOR(\339, \650)
\722 = NOT(\651)
\727 = AND(\654, \651)
\731 = NOR(\341, \659)
\732 = NAND(\654, \261)
\733 = NAND(\644, \654, \261)
\734 = NAND(\635, \644, \654, \261)
\735 = NOT(\662)
\736 = AND(\228, \665)
\737 = AND(\237, \662)
\738 = NOT(\670)
\739 = AND(\228, \673)
\740 = AND(\237, \670)
\741 = NOT(\678)
\742 = AND(\228, \682)
\743 = AND(\237, \678)
\744 = NOT(\687)
\745 = AND(\228, \692)
\746 = AND(\237, \687)
\747 = NOT(\697)
\748 = AND(\228, \700)
\749 = AND(\237, \697)
\750 = NOT(\705)
\751 = AND(\228, \708)
\752 = AND(\237, \705)
\753 = NOT(\713)
\754 = AND(\228, \717)
\755 = AND(\237, \713)
\756 = NOT(\722)
\757 = NOR(\727, \261)
\758 = AND(\727, \261)
\759 = AND(\228, \727)
\760 = AND(\237, \722)
\761 = NAND(\644, \722)
\762 = NAND(\635, \713)
\763 = NAND(\635, \644, \722)
\764 = NAND(\609, \687)
\765 = NAND(\600, \678)
\766 = NAND(\600, \609, \687)
\767 = BUFF(\660)
\768 = BUFF(\661)
\769 = NOR(\736, \737)
\770 = NOR(\739, \740)
\771 = NOR(\742, \743)
\772 = NOR(\745, \746)
\773 = NAND(\750, \762, \763, \734)
\777 = NOR(\748, \749)
\778 = NAND(\753, \761, \733)
\781 = NOR(\751, \752)
\782 = NAND(\756, \732)
\785 = NOR(\754, \755)
\786 = NOR(\757, \758)
\787 = NOR(\759, \760)
\788 = NOR(\700, \773)
\789 = AND(\700, \773)
\790 = NOR(\708, \778)
\791 = AND(\708, \778)
\792 = NOR(\717, \782)
\793 = AND(\717, \782)
\794 = AND(\219, \786)
\795 = NAND(\628, \773)
\796 = NAND(\795, \747)
\802 = NOR(\788, \789)
\803 = NOR(\790, \791)
\804 = NOR(\792, \793)
\805 = NOR(\340, \794)
\806 = NOR(\692, \796)
\807 = AND(\692, \796)
\808 = AND(\219, \802)
\809 = AND(\219, \803)
\810 = AND(\219, \804)
\811 = NAND(\805, \787, \731, \529)
\812 = NAND(\619, \796)
\813 = NAND(\609, \619, \796)
\814 = NAND(\600, \609, \619, \796)
\815 = NAND(\738, \765, \766, \814)
\819 = NAND(\741, \764, \813)
\822 = NAND(\744, \812)
\825 = NOR(\806, \807)
\826 = NOR(\335, \808)
\827 = NOR(\336, \809)
\828 = NOR(\338, \810)
\829 = NOT(\811)
\830 = NOR(\665, \815)
\831 = AND(\665, \815)
\832 = NOR(\673, \819)
\833 = AND(\673, \819)
\834 = NOR(\682, \822)
\835 = AND(\682, \822)
\836 = AND(\219, \825)
\837 = NAND(\826, \777, \704)
\838 = NAND(\827, \781, \712, \527)
\839 = NAND(\828, \785, \721, \528)
\840 = NOT(\829)
\841 = NAND(\815, \593)
\842 = NOR(\830, \831)
\843 = NOR(\832, \833)
\844 = NOR(\834, \835)
\845 = NOR(\334, \836)
\846 = NOT(\837)
\847 = NOT(\838)
\848 = NOT(\839)
\849 = AND(\735, \841)
\850 = BUFF(\840)
\851 = AND(\219, \842)
\852 = AND(\219, \843)
\853 = AND(\219, \844)
\854 = NAND(\845, \772, \696)
\855 = NOT(\846)
\856 = NOT(\847)
\857 = NOT(\848)
\858 = NOT(\849)
\859 = NOR(\417, \851)
\860 = NOR(\332, \852)
\861 = NOR(\333, \853)
\862 = NOT(\854)
\863 = BUFF(\855)
\864 = BUFF(\856)
\865 = BUFF(\857)
\866 = BUFF(\858)
\867 = NAND(\859, \769, \669)
\868 = NAND(\860, \770, \677)
\869 = NAND(\861, \771, \686)
\870 = NOT(\862)
\871 = NOT(\867)
\872 = NOT(\868)
\873 = NOT(\869)
\874 = BUFF(\870)
\875 = NOT(\871)
\876 = NOT(\872)
\877 = NOT(\873)
\878 = BUFF(\875)
\879 = BUFF(\876)
\880 = BUFF(\877)

604
ISCAS85/test.v
View File

@ -1,604 +0,0 @@
// Benchmark "c2670" written by ABC on Sun Jan 8 23:46:44 2023
module c2670 (
\1 , \2 , \3 , \4 , \5 , \6 , \7 , \8 , \11 , \14 , \15 , \16 , \19 ,
\20 , \21 , \22 , \23 , \24 , \25 , \26 , \27 , \28 , \29 , \32 , \33 ,
\34 , \35 , \36 , \37 , \40 , \43 , \44 , \47 , \48 , \49 , \50 , \51 ,
\52 , \53 , \54 , \55 , \56 , \57 , \60 , \61 , \62 , \63 , \64 , \65 ,
\66 , \67 , \68 , \69 , \72 , \73 , \74 , \75 , \76 , \77 , \78 , \79 ,
\80 , \81 , \82 , \85 , \86 , \87 , \88 , \89 , \90 , \91 , \92 , \93 ,
\94 , \95 , \96 , \99 , \100 , \101 , \102 , \103 , \104 , \105 ,
\106 , \107 , \108 , \111 , \112 , \113 , \114 , \115 , \116 , \117 ,
\118 , \119 , \120 , \123 , \124 , \125 , \126 , \127 , \128 , \129 ,
\130 , \131 , \132 , \135 , \136 , \137 , \138 , \139 , \140 , \141 ,
\142 , \143 , \144 , \145 , \146 , \147 , \148 , \149 , \150 , \151 ,
\152 , \153 , \154 , \155 , \156 , \157 , \158 , \159 , \160 , \161 ,
\162 , \163 , \164 , \165 , \166 , \167 , \168 , \169 , \170 , \171 ,
\172 , \173 , \174 , \175 , \176 , \177 , \178 , \179 , \180 , \181 ,
\182 , \183 , \184 , \185 , \186 , \187 , \188 , \189 , \190 , \191 ,
\192 , \193 , \194 , \195 , \196 , \197 , \198 , \199 , \200 , \201 ,
\202 , \203 , \204 , \205 , \206 , \207 , \208 , \209 , \210 , \211 ,
\212 , \213 , \214 , \215 , \216 , \217 , \218 , \219 , \224 , \227 ,
\230 , \231 , \234 , \237 , \241 , \246 , \253 , \256 , \259 , \262 ,
\263 , \266 , \269 , \272 , \275 , \278 , \281 , \284 , \287 , \290 ,
\294 , \297 , \301 , \305 , \309 , \313 , \316 , \319 , \322 , \325 ,
\328 , \331 , \334 , \337 , \340 , \343 , \346 , \349 , \352 , \355 ,
\398 , \400 , \401 , \419 , \420 , \456 , \457 , \458 , \487 , \488 ,
\489 , \490 , \491 , \492 , \493 , \494 , \792 , \799 , \805 , \1026 ,
\1028 , \1029 , \1269 , \1277 , \1448 , \1726 , \1816 , \1817 , \1818 ,
\1819 , \1820 , \1821 , \1969 , \1970 , \1971 , \2010 , \2012 , \2014 ,
\2016 , \2018 , \2020 , \2022 , \2387 , \2388 , \2389 , \2390 , \2496 ,
\2643 , \2644 , \2891 , \2925 , \2970 , \2971 , \3038 , \3079 , \3546 ,
\3671 , \3803 , \3804 , \3809 , \3851 , \3875 , \3881 , \3882 );
input \1 , \2 , \3 , \4 , \5 , \6 , \7 , \8 , \11 , \14 , \15 , \16 ,
\19 , \20 , \21 , \22 , \23 , \24 , \25 , \26 , \27 , \28 , \29 , \32 ,
\33 , \34 , \35 , \36 , \37 , \40 , \43 , \44 , \47 , \48 , \49 , \50 ,
\51 , \52 , \53 , \54 , \55 , \56 , \57 , \60 , \61 , \62 , \63 , \64 ,
\65 , \66 , \67 , \68 , \69 , \72 , \73 , \74 , \75 , \76 , \77 , \78 ,
\79 , \80 , \81 , \82 , \85 , \86 , \87 , \88 , \89 , \90 , \91 , \92 ,
\93 , \94 , \95 , \96 , \99 , \100 , \101 , \102 , \103 , \104 , \105 ,
\106 , \107 , \108 , \111 , \112 , \113 , \114 , \115 , \116 , \117 ,
\118 , \119 , \120 , \123 , \124 , \125 , \126 , \127 , \128 , \129 ,
\130 , \131 , \132 , \135 , \136 , \137 , \138 , \139 , \140 , \141 ,
\142 , \143 , \144 , \145 , \146 , \147 , \148 , \149 , \150 , \151 ,
\152 , \153 , \154 , \155 , \156 , \157 , \158 , \159 , \160 , \161 ,
\162 , \163 , \164 , \165 , \166 , \167 , \168 , \169 , \170 , \171 ,
\172 , \173 , \174 , \175 , \176 , \177 , \178 , \179 , \180 , \181 ,
\182 , \183 , \184 , \185 , \186 , \187 , \188 , \189 , \190 , \191 ,
\192 , \193 , \194 , \195 , \196 , \197 , \198 , \199 , \200 , \201 ,
\202 , \203 , \204 , \205 , \206 , \207 , \208 , \209 , \210 , \211 ,
\212 , \213 , \214 , \215 , \216 , \217 , \218 , \219 , \224 , \227 ,
\230 , \231 , \234 , \237 , \241 , \246 , \253 , \256 , \259 , \262 ,
\263 , \266 , \269 , \272 , \275 , \278 , \281 , \284 , \287 , \290 ,
\294 , \297 , \301 , \305 , \309 , \313 , \316 , \319 , \322 , \325 ,
\328 , \331 , \334 , \337 , \340 , \343 , \346 , \349 , \352 , \355 ;
output \398 , \400 , \401 , \419 , \420 , \456 , \457 , \458 , \487 , \488 ,
\489 , \490 , \491 , \492 , \493 , \494 , \792 , \799 , \805 , \1026 ,
\1028 , \1029 , \1269 , \1277 , \1448 , \1726 , \1816 , \1817 , \1818 ,
\1819 , \1820 , \1821 , \1969 , \1970 , \1971 , \2010 , \2012 , \2014 ,
\2016 , \2018 , \2020 , \2022 , \2387 , \2388 , \2389 , \2390 , \2496 ,
\2643 , \2644 , \2891 , \2925 , \2970 , \2971 , \3038 , \3079 , \3546 ,
\3671 , \3803 , \3804 , \3809 , \3851 , \3875 , \3881 , \3882 ;
wire new_n388_, new_n389_, new_n392_, new_n393_, new_n394_, new_n396_,
new_n397_, new_n398_, new_n399_, new_n400_, new_n401_, new_n403_,
new_n404_, new_n405_, new_n406_, new_n407_, new_n409_, new_n410_,
new_n411_, new_n412_, new_n413_, new_n415_, new_n416_, new_n417_,
new_n418_, new_n419_, new_n420_, new_n423_, new_n424_, new_n425_,
new_n426_, new_n429_, new_n430_, new_n431_, new_n432_, new_n435_,
new_n436_, new_n437_, new_n438_, new_n439_, new_n440_, new_n443_,
new_n445_, new_n446_, new_n447_, new_n448_, new_n450_, new_n451_,
new_n452_, new_n453_, new_n455_, new_n456_, new_n457_, new_n458_,
new_n460_, new_n461_, new_n462_, new_n463_, new_n465_, new_n466_,
new_n467_, new_n468_, new_n469_, new_n470_, new_n471_, new_n472_,
new_n474_, new_n475_, new_n477_, new_n478_, new_n479_, new_n481_,
new_n482_, new_n484_, new_n485_, new_n486_, new_n487_, new_n488_,
new_n489_, new_n490_, new_n491_, new_n492_, new_n493_, new_n494_,
new_n495_, new_n496_, new_n497_, new_n499_, new_n500_, new_n501_,
new_n502_, new_n503_, new_n504_, new_n505_, new_n506_, new_n507_,
new_n508_, new_n509_, new_n510_, new_n511_, new_n512_, new_n513_,
new_n514_, new_n515_, new_n517_, new_n518_, new_n519_, new_n520_,
new_n521_, new_n522_, new_n523_, new_n524_, new_n525_, new_n526_,
new_n527_, new_n528_, new_n530_, new_n531_, new_n532_, new_n533_,
new_n534_, new_n535_, new_n536_, new_n537_, new_n538_, new_n539_,
new_n540_, new_n541_, new_n542_, new_n543_, new_n545_, new_n546_,
new_n547_, new_n548_, new_n549_, new_n550_, new_n551_, new_n552_,
new_n553_, new_n554_, new_n555_, new_n556_, new_n557_, new_n558_,
new_n559_, new_n560_, new_n561_, new_n562_, new_n563_, new_n564_,
new_n565_, new_n566_, new_n567_, new_n568_, new_n569_, new_n570_,
new_n571_, new_n572_, new_n573_, new_n574_, new_n575_, new_n576_,
new_n577_, new_n578_, new_n579_, new_n580_, new_n581_, new_n582_,
new_n583_, new_n584_, new_n585_, new_n586_, new_n587_, new_n588_,
new_n589_, new_n590_, new_n591_, new_n592_, new_n593_, new_n594_,
new_n595_, new_n596_, new_n597_, new_n598_, new_n599_, new_n600_,
new_n601_, new_n602_, new_n603_, new_n604_, new_n605_, new_n606_,
new_n607_, new_n608_, new_n609_, new_n610_, new_n611_, new_n612_,
new_n613_, new_n614_, new_n615_, new_n616_, new_n617_, new_n618_,
new_n619_, new_n620_, new_n621_, new_n622_, new_n623_, new_n624_,
new_n625_, new_n626_, new_n627_, new_n628_, new_n629_, new_n630_,
new_n631_, new_n632_, new_n633_, new_n634_, new_n635_, new_n636_,
new_n637_, new_n638_, new_n639_, new_n640_, new_n641_, new_n642_,
new_n643_, new_n644_, new_n645_, new_n646_, new_n647_, new_n648_,
new_n649_, new_n650_, new_n651_, new_n652_, new_n653_, new_n654_,
new_n655_, new_n656_, new_n657_, new_n658_, new_n659_, new_n660_,
new_n661_, new_n662_, new_n663_, new_n664_, new_n665_, new_n666_,
new_n667_, new_n668_, new_n669_, new_n670_, new_n671_, new_n672_,
new_n673_, new_n674_, new_n675_, new_n676_, new_n677_, new_n678_,
new_n679_, new_n682_, new_n683_, new_n684_, new_n685_, new_n686_,
new_n687_, new_n688_, new_n689_, new_n690_, new_n691_, new_n693_,
new_n694_, new_n695_, new_n696_, new_n697_, new_n698_, new_n699_,
new_n700_, new_n701_, new_n702_, new_n703_, new_n704_, new_n705_,
new_n706_, new_n707_, new_n708_, new_n709_, new_n710_, new_n711_,
new_n712_, new_n713_, new_n714_, new_n715_, new_n717_, new_n718_,
new_n719_, new_n720_, new_n721_, new_n722_, new_n723_, new_n724_,
new_n725_, new_n726_, new_n727_, new_n728_, new_n729_, new_n730_,
new_n731_, new_n732_, new_n734_, new_n735_, new_n736_, new_n737_,
new_n738_, new_n739_, new_n740_, new_n741_, new_n742_, new_n743_,
new_n745_, new_n746_, new_n747_, new_n748_, new_n749_, new_n750_,
new_n751_, new_n752_, new_n753_, new_n754_, new_n755_, new_n756_,
new_n757_, new_n758_, new_n759_, new_n760_, new_n761_, new_n762_,
new_n763_, new_n764_, new_n765_, new_n766_, new_n767_, new_n768_,
new_n769_, new_n770_, new_n771_, new_n772_, new_n773_, new_n774_,
new_n775_, new_n776_, new_n777_, new_n778_, new_n779_, new_n780_,
new_n781_, new_n782_, new_n783_, new_n784_, new_n785_, new_n786_,
new_n787_, new_n788_, new_n789_, new_n790_, new_n791_, new_n792_,
new_n793_, new_n794_, new_n795_, new_n796_, new_n797_, new_n798_,
new_n799_, new_n800_, new_n801_, new_n802_, new_n803_, new_n804_,
new_n805_, new_n806_, new_n807_, new_n808_, new_n809_, new_n810_,
new_n811_, new_n812_, new_n813_, new_n814_, new_n815_, new_n816_,
new_n817_, new_n818_, new_n819_, new_n820_, new_n821_, new_n822_,
new_n823_, new_n824_, new_n825_, new_n826_, new_n827_, new_n830_;
NOT g000(.A(\44 ), .Y(\487 ));
NOT g001(.A(\132 ), .Y(\488 ));
NOT g002(.A(\82 ), .Y(\489 ));
NOT g003(.A(\96 ), .Y(\490 ));
NOT g004(.A(\69 ), .Y(\491 ));
NOT g005(.A(\120 ), .Y(\492 ));
NOT g006(.A(\57 ), .Y(\493 ));
NOT g007(.A(\108 ), .Y(\494 ));
NAND4 g008(.A(\309 ), .B(\305 ), .C(\301 ), .D(\297 ), .Y(\792 ));
NAND3 g009(.A(\237 ), .B(\15 ), .C(\2 ), .Y(\799 ));
AND2 g010(.A(\219 ), .B(\94 ), .Y(\1026 ));
NAND2 g011(.A(\237 ), .B(\7 ), .Y(\1028 ));
NAND3 g012(.A(\237 ), .B(\231 ), .C(\7 ), .Y(\1029 ));
NAND3 g013(.A(\325 ), .B(\237 ), .C(\7 ), .Y(\1269 ));
NAND4 g014(.A(\120 ), .B(\108 ), .C(\69 ), .D(\57 ), .Y(new_n388_));
NAND4 g015(.A(\132 ), .B(\96 ), .C(\82 ), .D(\44 ), .Y(new_n389_));
NOR2 g016(.A(new_n389_), .B(new_n388_), .Y(\1277 ));
NOT g017(.A(\1277 ), .Y(\1448 ));
NAND2 g018(.A(new_n389_), .B(\325 ), .Y(new_n392_));
NAND2 g019(.A(new_n388_), .B(\231 ), .Y(new_n393_));
NAND2 g020(.A(new_n393_), .B(new_n392_), .Y(new_n394_));
NOT g021(.A(new_n394_), .Y(\1726 ));
NAND3 g022(.A(\322 ), .B(\319 ), .C(\113 ), .Y(new_n396_));
NOT g023(.A(\319 ), .Y(new_n397_));
NAND3 g024(.A(\322 ), .B(new_n397_), .C(\125 ), .Y(new_n398_));
NOT g025(.A(\322 ), .Y(new_n399_));
NAND3 g026(.A(new_n399_), .B(new_n397_), .C(\137 ), .Y(new_n400_));
NAND3 g027(.A(new_n399_), .B(\319 ), .C(\101 ), .Y(new_n401_));
AND4 g028(.A(new_n401_), .B(new_n400_), .C(new_n398_), .D(new_n396_), .Y(\1816 ));
NAND3 g029(.A(\322 ), .B(\319 ), .C(\112 ), .Y(new_n403_));
NAND3 g030(.A(\322 ), .B(new_n397_), .C(\124 ), .Y(new_n404_));
NAND3 g031(.A(new_n399_), .B(new_n397_), .C(\136 ), .Y(new_n405_));
NAND3 g032(.A(new_n399_), .B(\319 ), .C(\100 ), .Y(new_n406_));
NAND4 g033(.A(new_n406_), .B(new_n405_), .C(new_n404_), .D(new_n403_), .Y(new_n407_));
NOT g034(.A(new_n407_), .Y(\1817 ));
NAND3 g035(.A(\322 ), .B(\319 ), .C(\114 ), .Y(new_n409_));
NAND3 g036(.A(\322 ), .B(new_n397_), .C(\126 ), .Y(new_n410_));
NAND3 g037(.A(new_n399_), .B(new_n397_), .C(\138 ), .Y(new_n411_));
NAND3 g038(.A(new_n399_), .B(\319 ), .C(\102 ), .Y(new_n412_));
NAND4 g039(.A(new_n412_), .B(new_n411_), .C(new_n410_), .D(new_n409_), .Y(new_n413_));
NOT g040(.A(new_n413_), .Y(\1818 ));
NAND3 g041(.A(\234 ), .B(\227 ), .C(\75 ), .Y(new_n415_));
NOT g042(.A(\227 ), .Y(new_n416_));
NAND3 g043(.A(\234 ), .B(new_n416_), .C(\62 ), .Y(new_n417_));
NOT g044(.A(\234 ), .Y(new_n418_));
NAND3 g045(.A(new_n418_), .B(new_n416_), .C(\88 ), .Y(new_n419_));
NAND3 g046(.A(new_n418_), .B(\227 ), .C(\50 ), .Y(new_n420_));
NAND4 g047(.A(new_n420_), .B(new_n419_), .C(new_n417_), .D(new_n415_), .Y(\2016 ));
NOT g048(.A(\2016 ), .Y(\1819 ));
NAND3 g049(.A(\234 ), .B(\227 ), .C(\76 ), .Y(new_n423_));
NAND3 g050(.A(\234 ), .B(new_n416_), .C(\63 ), .Y(new_n424_));
NAND3 g051(.A(new_n418_), .B(new_n416_), .C(\89 ), .Y(new_n425_));
NAND3 g052(.A(new_n418_), .B(\227 ), .C(\51 ), .Y(new_n426_));
NAND4 g053(.A(new_n426_), .B(new_n425_), .C(new_n424_), .D(new_n423_), .Y(\2014 ));
NOT g054(.A(\2014 ), .Y(\1820 ));
NAND3 g055(.A(\234 ), .B(\227 ), .C(\77 ), .Y(new_n429_));
NAND3 g056(.A(\234 ), .B(new_n416_), .C(\64 ), .Y(new_n430_));
NAND3 g057(.A(new_n418_), .B(new_n416_), .C(\90 ), .Y(new_n431_));
NAND3 g058(.A(new_n418_), .B(\227 ), .C(\52 ), .Y(new_n432_));
NAND4 g059(.A(new_n432_), .B(new_n431_), .C(new_n430_), .D(new_n429_), .Y(\2012 ));
NOT g060(.A(\2012 ), .Y(\1821 ));
NAND3 g061(.A(\234 ), .B(\227 ), .C(\68 ), .Y(new_n435_));
NAND3 g062(.A(\234 ), .B(new_n416_), .C(\56 ), .Y(new_n436_));
NAND3 g063(.A(new_n418_), .B(new_n416_), .C(\81 ), .Y(new_n437_));
NAND3 g064(.A(new_n418_), .B(\227 ), .C(\43 ), .Y(new_n438_));
NAND4 g065(.A(new_n438_), .B(new_n437_), .C(new_n436_), .D(new_n435_), .Y(new_n439_));
NOT g066(.A(new_n439_), .Y(new_n440_));
NAND2 g067(.A(new_n440_), .B(\241 ), .Y(\1969 ));
NAND4 g068(.A(\1726 ), .B(\237 ), .C(\224 ), .D(\36 ), .Y(\1970 ));
NAND2 g069(.A(\3 ), .B(\1 ), .Y(new_n443_));
NAND4 g070(.A(new_n443_), .B(\1726 ), .C(\237 ), .D(\224 ), .Y(\1971 ));
NAND3 g071(.A(\234 ), .B(\227 ), .C(\78 ), .Y(new_n445_));
NAND3 g072(.A(\234 ), .B(new_n416_), .C(\65 ), .Y(new_n446_));
NAND3 g073(.A(new_n418_), .B(new_n416_), .C(\91 ), .Y(new_n447_));
NAND3 g074(.A(new_n418_), .B(\227 ), .C(\53 ), .Y(new_n448_));
NAND4 g075(.A(new_n448_), .B(new_n447_), .C(new_n446_), .D(new_n445_), .Y(\2010 ));
NAND3 g076(.A(\234 ), .B(\227 ), .C(\74 ), .Y(new_n450_));
OR2 g077(.A(new_n418_), .B(\227 ), .Y(new_n451_));
NAND3 g078(.A(new_n418_), .B(new_n416_), .C(\87 ), .Y(new_n452_));
NAND3 g079(.A(new_n418_), .B(\227 ), .C(\49 ), .Y(new_n453_));
NAND4 g080(.A(new_n453_), .B(new_n452_), .C(new_n451_), .D(new_n450_), .Y(\2018 ));
NAND3 g081(.A(\234 ), .B(\227 ), .C(\73 ), .Y(new_n455_));
NAND3 g082(.A(\234 ), .B(new_n416_), .C(\61 ), .Y(new_n456_));
NAND3 g083(.A(new_n418_), .B(new_n416_), .C(\86 ), .Y(new_n457_));
NAND3 g084(.A(new_n418_), .B(\227 ), .C(\48 ), .Y(new_n458_));
NAND4 g085(.A(new_n458_), .B(new_n457_), .C(new_n456_), .D(new_n455_), .Y(\2020 ));
NAND3 g086(.A(\234 ), .B(\227 ), .C(\72 ), .Y(new_n460_));
NAND3 g087(.A(\234 ), .B(new_n416_), .C(\60 ), .Y(new_n461_));
NAND3 g088(.A(new_n418_), .B(new_n416_), .C(\85 ), .Y(new_n462_));
NAND3 g089(.A(new_n418_), .B(\227 ), .C(\47 ), .Y(new_n463_));
NAND4 g090(.A(new_n463_), .B(new_n462_), .C(new_n461_), .D(new_n460_), .Y(\2022 ));
NOT g091(.A(\246 ), .Y(new_n465_));
NAND3 g092(.A(\234 ), .B(\227 ), .C(\79 ), .Y(new_n466_));
NAND3 g093(.A(\234 ), .B(new_n416_), .C(\66 ), .Y(new_n467_));
NAND3 g094(.A(new_n418_), .B(new_n416_), .C(\92 ), .Y(new_n468_));
NAND3 g095(.A(new_n418_), .B(\227 ), .C(\54 ), .Y(new_n469_));
NAND4 g096(.A(new_n469_), .B(new_n468_), .C(new_n467_), .D(new_n466_), .Y(new_n470_));
NAND2 g097(.A(new_n470_), .B(new_n465_), .Y(new_n471_));
NAND2 g098(.A(\2012 ), .B(\246 ), .Y(new_n472_));
NAND2 g099(.A(new_n472_), .B(new_n471_), .Y(\2387 ));
NAND2 g100(.A(\2010 ), .B(new_n465_), .Y(new_n474_));
NAND2 g101(.A(\2014 ), .B(\246 ), .Y(new_n475_));
NAND2 g102(.A(new_n475_), .B(new_n474_), .Y(\2389 ));
NOR2 g103(.A(new_n470_), .B(\230 ), .Y(new_n477_));
OR2 g104(.A(new_n477_), .B(\241 ), .Y(new_n478_));
NAND2 g105(.A(new_n470_), .B(\241 ), .Y(new_n479_));
NAND2 g106(.A(new_n479_), .B(new_n478_), .Y(\2496 ));
NAND2 g107(.A(new_n439_), .B(new_n465_), .Y(new_n481_));
OR2 g108(.A(new_n477_), .B(new_n465_), .Y(new_n482_));
NAND2 g109(.A(new_n482_), .B(new_n481_), .Y(\2643 ));
NAND3 g110(.A(\322 ), .B(\319 ), .C(\111 ), .Y(new_n484_));
NAND3 g111(.A(\322 ), .B(new_n397_), .C(\123 ), .Y(new_n485_));
NAND3 g112(.A(new_n399_), .B(new_n397_), .C(\135 ), .Y(new_n486_));
NAND3 g113(.A(new_n399_), .B(\319 ), .C(\99 ), .Y(new_n487_));
NAND4 g114(.A(new_n487_), .B(new_n486_), .C(new_n485_), .D(new_n484_), .Y(new_n488_));
NAND2 g115(.A(new_n488_), .B(\313 ), .Y(new_n489_));
OR2 g116(.A(new_n488_), .B(\313 ), .Y(new_n490_));
NAND2 g117(.A(\322 ), .B(\319 ), .Y(new_n491_));
OR2 g118(.A(new_n399_), .B(\319 ), .Y(new_n492_));
OR2 g119(.A(\322 ), .B(\319 ), .Y(new_n493_));
OR2 g120(.A(\322 ), .B(new_n397_), .Y(new_n494_));
NAND4 g121(.A(new_n494_), .B(new_n493_), .C(new_n492_), .D(new_n491_), .Y(new_n495_));
OR2 g122(.A(new_n495_), .B(\316 ), .Y(new_n496_));
NAND2 g123(.A(new_n495_), .B(\316 ), .Y(new_n497_));
NAND4 g124(.A(new_n497_), .B(new_n496_), .C(new_n490_), .D(new_n489_), .Y(\2891 ));
XOR2 g125(.A(\349 ), .B(\346 ), .Y(new_n499_));
XNOR2 g126(.A(\259 ), .B(\256 ), .Y(new_n500_));
XOR2 g127(.A(new_n500_), .B(new_n499_), .Y(new_n501_));
XNOR2 g128(.A(\337 ), .B(\334 ), .Y(new_n502_));
XNOR2 g129(.A(\343 ), .B(\340 ), .Y(new_n503_));
XNOR2 g130(.A(\331 ), .B(\328 ), .Y(new_n504_));
NOT g131(.A(new_n504_), .Y(new_n505_));
NAND3 g132(.A(new_n505_), .B(new_n503_), .C(new_n502_), .Y(new_n506_));
NOT g133(.A(new_n503_), .Y(new_n507_));
NAND3 g134(.A(new_n504_), .B(new_n507_), .C(new_n502_), .Y(new_n508_));
NOT g135(.A(new_n502_), .Y(new_n509_));
NAND3 g136(.A(new_n504_), .B(new_n503_), .C(new_n509_), .Y(new_n510_));
NAND3 g137(.A(new_n505_), .B(new_n507_), .C(new_n509_), .Y(new_n511_));
NAND4 g138(.A(new_n511_), .B(new_n510_), .C(new_n508_), .D(new_n506_), .Y(new_n512_));
NAND2 g139(.A(new_n512_), .B(new_n501_), .Y(new_n513_));
OR2 g140(.A(new_n512_), .B(new_n501_), .Y(new_n514_));
NAND3 g141(.A(new_n514_), .B(new_n513_), .C(\14 ), .Y(new_n515_));
NOT g142(.A(new_n515_), .Y(\2925 ));
XNOR2 g143(.A(\316 ), .B(\313 ), .Y(new_n517_));
XNOR2 g144(.A(\301 ), .B(\297 ), .Y(new_n518_));
XNOR2 g145(.A(\309 ), .B(\305 ), .Y(new_n519_));
XNOR2 g146(.A(\355 ), .B(\294 ), .Y(new_n520_));
NOT g147(.A(new_n520_), .Y(new_n521_));
NAND3 g148(.A(new_n521_), .B(new_n519_), .C(new_n518_), .Y(new_n522_));
NOT g149(.A(new_n519_), .Y(new_n523_));
NAND3 g150(.A(new_n520_), .B(new_n523_), .C(new_n518_), .Y(new_n524_));
NOT g151(.A(new_n518_), .Y(new_n525_));
NAND3 g152(.A(new_n520_), .B(new_n519_), .C(new_n525_), .Y(new_n526_));
NAND3 g153(.A(new_n521_), .B(new_n523_), .C(new_n525_), .Y(new_n527_));
NAND4 g154(.A(new_n527_), .B(new_n526_), .C(new_n524_), .D(new_n522_), .Y(new_n528_));
XOR2 g155(.A(new_n528_), .B(new_n517_), .Y(\2970 ));
XOR2 g156(.A(\281 ), .B(\278 ), .Y(new_n530_));
XNOR2 g157(.A(\287 ), .B(\284 ), .Y(new_n531_));
XOR2 g158(.A(new_n531_), .B(new_n530_), .Y(new_n532_));
XNOR2 g159(.A(\269 ), .B(\266 ), .Y(new_n533_));
XNOR2 g160(.A(\275 ), .B(\272 ), .Y(new_n534_));
XNOR2 g161(.A(\352 ), .B(\263 ), .Y(new_n535_));
NOT g162(.A(new_n535_), .Y(new_n536_));
NAND3 g163(.A(new_n536_), .B(new_n534_), .C(new_n533_), .Y(new_n537_));
NOT g164(.A(new_n534_), .Y(new_n538_));
NAND3 g165(.A(new_n535_), .B(new_n538_), .C(new_n533_), .Y(new_n539_));
NOT g166(.A(new_n533_), .Y(new_n540_));
NAND3 g167(.A(new_n535_), .B(new_n534_), .C(new_n540_), .Y(new_n541_));
NAND3 g168(.A(new_n536_), .B(new_n538_), .C(new_n540_), .Y(new_n542_));
NAND4 g169(.A(new_n542_), .B(new_n541_), .C(new_n539_), .D(new_n537_), .Y(new_n543_));
XOR2 g170(.A(new_n543_), .B(new_n532_), .Y(\2971 ));
NOT g171(.A(\27 ), .Y(new_n545_));
OR2 g172(.A(\29 ), .B(new_n545_), .Y(new_n546_));
NAND2 g173(.A(new_n413_), .B(\29 ), .Y(new_n547_));
NAND2 g174(.A(new_n547_), .B(new_n546_), .Y(new_n548_));
OR2 g175(.A(new_n548_), .B(\301 ), .Y(new_n549_));
NOT g176(.A(\34 ), .Y(new_n550_));
OR2 g177(.A(new_n550_), .B(\29 ), .Y(new_n551_));
NAND4 g178(.A(new_n401_), .B(new_n400_), .C(new_n398_), .D(new_n396_), .Y(new_n552_));
NAND2 g179(.A(new_n552_), .B(\29 ), .Y(new_n553_));
NAND2 g180(.A(new_n553_), .B(new_n551_), .Y(new_n554_));
OR2 g181(.A(new_n554_), .B(\305 ), .Y(new_n555_));
NAND2 g182(.A(new_n548_), .B(\301 ), .Y(new_n556_));
NOT g183(.A(\26 ), .Y(new_n557_));
OR2 g184(.A(\29 ), .B(new_n557_), .Y(new_n558_));
NAND3 g185(.A(\322 ), .B(\319 ), .C(\116 ), .Y(new_n559_));
NAND3 g186(.A(\322 ), .B(new_n397_), .C(\128 ), .Y(new_n560_));
NAND3 g187(.A(new_n399_), .B(new_n397_), .C(\140 ), .Y(new_n561_));
NAND3 g188(.A(new_n399_), .B(\319 ), .C(\104 ), .Y(new_n562_));
NAND4 g189(.A(new_n562_), .B(new_n561_), .C(new_n560_), .D(new_n559_), .Y(new_n563_));
NAND2 g190(.A(new_n563_), .B(\29 ), .Y(new_n564_));
NAND2 g191(.A(new_n564_), .B(new_n558_), .Y(new_n565_));
OR2 g192(.A(new_n565_), .B(\294 ), .Y(new_n566_));
NOT g193(.A(\33 ), .Y(new_n567_));
OR2 g194(.A(new_n567_), .B(\29 ), .Y(new_n568_));
NAND3 g195(.A(\322 ), .B(\319 ), .C(\115 ), .Y(new_n569_));
NAND3 g196(.A(\322 ), .B(new_n397_), .C(\127 ), .Y(new_n570_));
NAND3 g197(.A(new_n399_), .B(new_n397_), .C(\139 ), .Y(new_n571_));
NAND3 g198(.A(new_n399_), .B(\319 ), .C(\103 ), .Y(new_n572_));
NAND4 g199(.A(new_n572_), .B(new_n571_), .C(new_n570_), .D(new_n569_), .Y(new_n573_));
NAND2 g200(.A(new_n573_), .B(\29 ), .Y(new_n574_));
NAND2 g201(.A(new_n574_), .B(new_n568_), .Y(new_n575_));
NAND2 g202(.A(new_n575_), .B(\297 ), .Y(new_n576_));
OR2 g203(.A(new_n575_), .B(\297 ), .Y(new_n577_));
NAND2 g204(.A(new_n554_), .B(\305 ), .Y(new_n578_));
NAND4 g205(.A(new_n578_), .B(new_n577_), .C(new_n576_), .D(new_n566_), .Y(new_n579_));
NOT g206(.A(\35 ), .Y(new_n580_));
OR2 g207(.A(new_n580_), .B(\29 ), .Y(new_n581_));
NAND2 g208(.A(new_n407_), .B(\29 ), .Y(new_n582_));
NAND2 g209(.A(new_n582_), .B(new_n581_), .Y(new_n583_));
OR2 g210(.A(new_n583_), .B(\309 ), .Y(new_n584_));
NOT g211(.A(\32 ), .Y(new_n585_));
OR2 g212(.A(new_n585_), .B(\29 ), .Y(new_n586_));
NAND3 g213(.A(\322 ), .B(\319 ), .C(\117 ), .Y(new_n587_));
NAND3 g214(.A(\322 ), .B(new_n397_), .C(\129 ), .Y(new_n588_));
NAND3 g215(.A(new_n399_), .B(new_n397_), .C(\141 ), .Y(new_n589_));
NAND3 g216(.A(new_n399_), .B(\319 ), .C(\105 ), .Y(new_n590_));
NAND4 g217(.A(new_n590_), .B(new_n589_), .C(new_n588_), .D(new_n587_), .Y(new_n591_));
NAND2 g218(.A(new_n591_), .B(\29 ), .Y(new_n592_));
NAND2 g219(.A(new_n592_), .B(new_n586_), .Y(new_n593_));
NAND2 g220(.A(new_n593_), .B(\287 ), .Y(new_n594_));
OR2 g221(.A(new_n593_), .B(\287 ), .Y(new_n595_));
NAND2 g222(.A(new_n565_), .B(\294 ), .Y(new_n596_));
NAND4 g223(.A(new_n596_), .B(new_n595_), .C(new_n594_), .D(new_n584_), .Y(new_n597_));
NOR2 g224(.A(new_n597_), .B(new_n579_), .Y(new_n598_));
NAND4 g225(.A(new_n598_), .B(new_n556_), .C(new_n555_), .D(new_n549_), .Y(new_n599_));
NOT g226(.A(\22 ), .Y(new_n600_));
OR2 g227(.A(new_n600_), .B(\16 ), .Y(new_n601_));
NAND2 g228(.A(\2016 ), .B(\16 ), .Y(new_n602_));
NAND2 g229(.A(new_n602_), .B(new_n601_), .Y(new_n603_));
NAND2 g230(.A(new_n603_), .B(\272 ), .Y(new_n604_));
NAND2 g231(.A(new_n465_), .B(\11 ), .Y(new_n605_));
NAND2 g232(.A(\246 ), .B(\11 ), .Y(new_n606_));
NAND2 g233(.A(new_n606_), .B(new_n605_), .Y(new_n607_));
NOT g234(.A(\28 ), .Y(new_n608_));
OR2 g235(.A(\29 ), .B(new_n608_), .Y(new_n609_));
NAND2 g236(.A(new_n488_), .B(\29 ), .Y(new_n610_));
NAND2 g237(.A(new_n610_), .B(new_n609_), .Y(new_n611_));
NAND3 g238(.A(new_n611_), .B(new_n607_), .C(new_n604_), .Y(new_n612_));
OR2 g239(.A(new_n603_), .B(\272 ), .Y(new_n613_));
NOT g240(.A(\23 ), .Y(new_n614_));
OR2 g241(.A(new_n614_), .B(\16 ), .Y(new_n615_));
NAND2 g242(.A(\2018 ), .B(\16 ), .Y(new_n616_));
NAND2 g243(.A(new_n616_), .B(new_n615_), .Y(new_n617_));
NAND2 g244(.A(new_n617_), .B(\275 ), .Y(new_n618_));
OR2 g245(.A(new_n617_), .B(\275 ), .Y(new_n619_));
NOT g246(.A(\6 ), .Y(new_n620_));
OR2 g247(.A(\16 ), .B(new_n620_), .Y(new_n621_));
NAND2 g248(.A(\2020 ), .B(\16 ), .Y(new_n622_));
NAND2 g249(.A(new_n622_), .B(new_n621_), .Y(new_n623_));
NAND2 g250(.A(new_n623_), .B(\278 ), .Y(new_n624_));
NAND4 g251(.A(new_n624_), .B(new_n619_), .C(new_n618_), .D(new_n613_), .Y(new_n625_));
NOT g252(.A(\24 ), .Y(new_n626_));
OR2 g253(.A(new_n626_), .B(\16 ), .Y(new_n627_));
NAND2 g254(.A(\2022 ), .B(\16 ), .Y(new_n628_));
NAND2 g255(.A(new_n628_), .B(new_n627_), .Y(new_n629_));
OR2 g256(.A(new_n629_), .B(\281 ), .Y(new_n630_));
NOT g257(.A(\19 ), .Y(new_n631_));
OR2 g258(.A(new_n631_), .B(\16 ), .Y(new_n632_));
NAND2 g259(.A(new_n439_), .B(\16 ), .Y(new_n633_));
NAND2 g260(.A(new_n633_), .B(new_n632_), .Y(new_n634_));
NAND2 g261(.A(new_n634_), .B(\256 ), .Y(new_n635_));
OR2 g262(.A(new_n634_), .B(\256 ), .Y(new_n636_));
NOT g263(.A(\4 ), .Y(new_n637_));
OR2 g264(.A(\16 ), .B(new_n637_), .Y(new_n638_));
NAND2 g265(.A(new_n470_), .B(\16 ), .Y(new_n639_));
NAND2 g266(.A(new_n639_), .B(new_n638_), .Y(new_n640_));
NAND2 g267(.A(new_n640_), .B(\259 ), .Y(new_n641_));
NAND4 g268(.A(new_n641_), .B(new_n636_), .C(new_n635_), .D(new_n630_), .Y(new_n642_));
OR2 g269(.A(new_n623_), .B(\278 ), .Y(new_n643_));
NOT g270(.A(\25 ), .Y(new_n644_));
OR2 g271(.A(\29 ), .B(new_n644_), .Y(new_n645_));
NAND3 g272(.A(\322 ), .B(\319 ), .C(\107 ), .Y(new_n646_));
NAND3 g273(.A(\322 ), .B(new_n397_), .C(\119 ), .Y(new_n647_));
NAND3 g274(.A(new_n399_), .B(new_n397_), .C(\131 ), .Y(new_n648_));
NAND3 g275(.A(new_n399_), .B(\319 ), .C(\95 ), .Y(new_n649_));
NAND4 g276(.A(new_n649_), .B(new_n648_), .C(new_n647_), .D(new_n646_), .Y(new_n650_));
NAND2 g277(.A(new_n650_), .B(\29 ), .Y(new_n651_));
NAND2 g278(.A(new_n651_), .B(new_n645_), .Y(new_n652_));
NAND2 g279(.A(new_n652_), .B(\284 ), .Y(new_n653_));
OR2 g280(.A(new_n652_), .B(\284 ), .Y(new_n654_));
NAND2 g281(.A(new_n629_), .B(\281 ), .Y(new_n655_));
NAND4 g282(.A(new_n655_), .B(new_n654_), .C(new_n653_), .D(new_n643_), .Y(new_n656_));
NOT g283(.A(\21 ), .Y(new_n657_));
OR2 g284(.A(new_n657_), .B(\16 ), .Y(new_n658_));
NAND2 g285(.A(\2014 ), .B(\16 ), .Y(new_n659_));
NAND2 g286(.A(new_n659_), .B(new_n658_), .Y(new_n660_));
OR2 g287(.A(new_n660_), .B(\269 ), .Y(new_n661_));
NOT g288(.A(\5 ), .Y(new_n662_));
OR2 g289(.A(\16 ), .B(new_n662_), .Y(new_n663_));
NAND2 g290(.A(\2012 ), .B(\16 ), .Y(new_n664_));
NAND2 g291(.A(new_n664_), .B(new_n663_), .Y(new_n665_));
NAND2 g292(.A(new_n665_), .B(\266 ), .Y(new_n666_));
OR2 g293(.A(new_n665_), .B(\266 ), .Y(new_n667_));
NAND2 g294(.A(new_n583_), .B(\309 ), .Y(new_n668_));
NAND4 g295(.A(new_n668_), .B(new_n667_), .C(new_n666_), .D(new_n661_), .Y(new_n669_));
OR2 g296(.A(new_n640_), .B(\259 ), .Y(new_n670_));
NOT g297(.A(\20 ), .Y(new_n671_));
OR2 g298(.A(new_n671_), .B(\16 ), .Y(new_n672_));
NAND2 g299(.A(\2010 ), .B(\16 ), .Y(new_n673_));
NAND2 g300(.A(new_n673_), .B(new_n672_), .Y(new_n674_));
NAND2 g301(.A(new_n674_), .B(\263 ), .Y(new_n675_));
OR2 g302(.A(new_n674_), .B(\263 ), .Y(new_n676_));
NAND2 g303(.A(new_n660_), .B(\269 ), .Y(new_n677_));
NAND4 g304(.A(new_n677_), .B(new_n676_), .C(new_n675_), .D(new_n670_), .Y(new_n678_));
OR4 g305(.A(new_n678_), .B(new_n669_), .C(new_n656_), .D(new_n642_), .Y(new_n679_));
NOR4 g306(.A(new_n679_), .B(new_n625_), .C(new_n612_), .D(new_n599_), .Y(\3038 ));
NOT g307(.A(\3038 ), .Y(\3079 ));
XNOR2 g308(.A(new_n470_), .B(new_n439_), .Y(new_n682_));
XOR2 g309(.A(new_n682_), .B(new_n477_), .Y(new_n683_));
NAND3 g310(.A(\234 ), .B(\227 ), .C(\80 ), .Y(new_n684_));
NAND3 g311(.A(\234 ), .B(new_n416_), .C(\67 ), .Y(new_n685_));
NAND3 g312(.A(new_n418_), .B(new_n416_), .C(\93 ), .Y(new_n686_));
NAND3 g313(.A(new_n418_), .B(\227 ), .C(\55 ), .Y(new_n687_));
NAND4 g314(.A(new_n687_), .B(new_n686_), .C(new_n685_), .D(new_n684_), .Y(new_n688_));
XOR2 g315(.A(new_n688_), .B(new_n683_), .Y(new_n689_));
OR2 g316(.A(new_n689_), .B(\241 ), .Y(new_n690_));
NAND2 g317(.A(new_n688_), .B(\241 ), .Y(new_n691_));
NAND2 g318(.A(new_n691_), .B(new_n690_), .Y(\3546 ));
NOT g319(.A(\37 ), .Y(new_n693_));
XOR2 g320(.A(new_n407_), .B(new_n552_), .Y(new_n694_));
XNOR2 g321(.A(new_n495_), .B(new_n488_), .Y(new_n695_));
XOR2 g322(.A(new_n695_), .B(new_n694_), .Y(new_n696_));
XNOR2 g323(.A(new_n591_), .B(new_n563_), .Y(new_n697_));
XNOR2 g324(.A(new_n573_), .B(new_n413_), .Y(new_n698_));
NAND3 g325(.A(\322 ), .B(\319 ), .C(\118 ), .Y(new_n699_));
NAND3 g326(.A(\322 ), .B(new_n397_), .C(\130 ), .Y(new_n700_));
NAND3 g327(.A(new_n399_), .B(new_n397_), .C(\142 ), .Y(new_n701_));
NAND3 g328(.A(new_n399_), .B(\319 ), .C(\106 ), .Y(new_n702_));
NAND4 g329(.A(new_n702_), .B(new_n701_), .C(new_n700_), .D(new_n699_), .Y(new_n703_));
XNOR2 g330(.A(new_n703_), .B(new_n650_), .Y(new_n704_));
NOT g331(.A(new_n704_), .Y(new_n705_));
NAND3 g332(.A(new_n705_), .B(new_n698_), .C(new_n697_), .Y(new_n706_));
NOT g333(.A(new_n698_), .Y(new_n707_));
NAND3 g334(.A(new_n704_), .B(new_n707_), .C(new_n697_), .Y(new_n708_));
NOT g335(.A(new_n697_), .Y(new_n709_));
NAND3 g336(.A(new_n704_), .B(new_n698_), .C(new_n709_), .Y(new_n710_));
NAND3 g337(.A(new_n705_), .B(new_n707_), .C(new_n709_), .Y(new_n711_));
NAND4 g338(.A(new_n711_), .B(new_n710_), .C(new_n708_), .D(new_n706_), .Y(new_n712_));
NAND2 g339(.A(new_n712_), .B(new_n696_), .Y(new_n713_));
OR2 g340(.A(new_n712_), .B(new_n696_), .Y(new_n714_));
NAND3 g341(.A(new_n714_), .B(new_n713_), .C(new_n693_), .Y(new_n715_));
NOT g342(.A(new_n715_), .Y(\3671 ));
NAND2 g343(.A(new_n688_), .B(new_n465_), .Y(new_n717_));
XOR2 g344(.A(\2018 ), .B(\2016 ), .Y(new_n718_));
XNOR2 g345(.A(\2022 ), .B(\2020 ), .Y(new_n719_));
XOR2 g346(.A(new_n719_), .B(new_n718_), .Y(new_n720_));
NOT g347(.A(new_n477_), .Y(new_n721_));
XNOR2 g348(.A(new_n688_), .B(new_n439_), .Y(new_n722_));
XNOR2 g349(.A(new_n470_), .B(\2010 ), .Y(new_n723_));
NAND3 g350(.A(new_n723_), .B(new_n722_), .C(new_n721_), .Y(new_n724_));
NOT g351(.A(new_n723_), .Y(new_n725_));
NAND3 g352(.A(new_n725_), .B(new_n722_), .C(new_n477_), .Y(new_n726_));
NOT g353(.A(new_n722_), .Y(new_n727_));
NAND3 g354(.A(new_n723_), .B(new_n727_), .C(new_n477_), .Y(new_n728_));
NAND3 g355(.A(new_n725_), .B(new_n727_), .C(new_n721_), .Y(new_n729_));
NAND4 g356(.A(new_n729_), .B(new_n728_), .C(new_n726_), .D(new_n724_), .Y(new_n730_));
XOR2 g357(.A(new_n730_), .B(new_n720_), .Y(new_n731_));
OR2 g358(.A(new_n731_), .B(new_n465_), .Y(new_n732_));
NAND2 g359(.A(new_n732_), .B(new_n717_), .Y(\3803 ));
XNOR2 g360(.A(\2012 ), .B(\2014 ), .Y(new_n734_));
NAND3 g361(.A(new_n734_), .B(new_n723_), .C(new_n727_), .Y(new_n735_));
NOT g362(.A(new_n734_), .Y(new_n736_));
NAND3 g363(.A(new_n736_), .B(new_n723_), .C(new_n722_), .Y(new_n737_));
NAND3 g364(.A(new_n734_), .B(new_n725_), .C(new_n722_), .Y(new_n738_));
NAND3 g365(.A(new_n736_), .B(new_n725_), .C(new_n727_), .Y(new_n739_));
NAND4 g366(.A(new_n739_), .B(new_n738_), .C(new_n737_), .D(new_n735_), .Y(new_n740_));
NAND2 g367(.A(new_n740_), .B(new_n720_), .Y(new_n741_));
OR2 g368(.A(new_n740_), .B(new_n720_), .Y(new_n742_));
NAND3 g369(.A(new_n742_), .B(new_n741_), .C(new_n693_), .Y(new_n743_));
NOT g370(.A(new_n743_), .Y(\3809 ));
NOT g371(.A(\40 ), .Y(new_n745_));
NOT g372(.A(\262 ), .Y(new_n746_));
NAND2 g373(.A(new_n413_), .B(new_n746_), .Y(new_n747_));
NOR3 g374(.A(new_n747_), .B(new_n552_), .C(new_n745_), .Y(new_n748_));
NOR2 g375(.A(new_n552_), .B(new_n745_), .Y(new_n749_));
NAND2 g376(.A(new_n749_), .B(new_n747_), .Y(new_n750_));
NOR3 g377(.A(new_n750_), .B(new_n748_), .C(\294 ), .Y(new_n751_));
NAND3 g378(.A(new_n749_), .B(new_n747_), .C(new_n563_), .Y(new_n752_));
XOR2 g379(.A(new_n752_), .B(new_n751_), .Y(new_n753_));
NOR3 g380(.A(new_n750_), .B(new_n748_), .C(\287 ), .Y(new_n754_));
NAND3 g381(.A(new_n749_), .B(new_n747_), .C(new_n591_), .Y(new_n755_));
XOR2 g382(.A(new_n755_), .B(new_n754_), .Y(new_n756_));
NOR3 g383(.A(new_n750_), .B(new_n748_), .C(\284 ), .Y(new_n757_));
NAND3 g384(.A(new_n749_), .B(new_n747_), .C(new_n650_), .Y(new_n758_));
NAND4 g385(.A(new_n758_), .B(new_n757_), .C(new_n756_), .D(new_n753_), .Y(new_n759_));
NOR4 g386(.A(new_n750_), .B(new_n748_), .C(\2022 ), .D(\281 ), .Y(new_n760_));
XOR2 g387(.A(new_n758_), .B(new_n757_), .Y(new_n761_));
NAND4 g388(.A(new_n761_), .B(new_n760_), .C(new_n756_), .D(new_n753_), .Y(new_n762_));
NAND2 g389(.A(new_n752_), .B(new_n751_), .Y(new_n763_));
NAND3 g390(.A(new_n755_), .B(new_n754_), .C(new_n753_), .Y(new_n764_));
AND4 g391(.A(new_n764_), .B(new_n763_), .C(new_n762_), .D(new_n759_), .Y(new_n765_));
NAND4 g392(.A(new_n413_), .B(\1816 ), .C(new_n746_), .D(\40 ), .Y(new_n766_));
OR2 g393(.A(new_n766_), .B(\294 ), .Y(new_n767_));
NOT g394(.A(\259 ), .Y(new_n768_));
NAND2 g395(.A(new_n766_), .B(new_n768_), .Y(new_n769_));
NAND2 g396(.A(new_n769_), .B(new_n767_), .Y(new_n770_));
XNOR2 g397(.A(new_n770_), .B(new_n470_), .Y(new_n771_));
OR2 g398(.A(new_n766_), .B(\297 ), .Y(new_n772_));
NOT g399(.A(\263 ), .Y(new_n773_));
NAND2 g400(.A(new_n766_), .B(new_n773_), .Y(new_n774_));
AND2 g401(.A(new_n774_), .B(new_n772_), .Y(new_n775_));
XOR2 g402(.A(new_n775_), .B(\2010 ), .Y(new_n776_));
OR2 g403(.A(new_n766_), .B(\287 ), .Y(new_n777_));
OR2 g404(.A(new_n748_), .B(\256 ), .Y(new_n778_));
NAND2 g405(.A(new_n778_), .B(new_n777_), .Y(new_n779_));
NAND4 g406(.A(new_n779_), .B(new_n776_), .C(new_n771_), .D(new_n440_), .Y(new_n780_));
OR2 g407(.A(new_n775_), .B(\2010 ), .Y(new_n781_));
NOT g408(.A(new_n470_), .Y(new_n782_));
NAND3 g409(.A(new_n776_), .B(new_n770_), .C(new_n782_), .Y(new_n783_));
NAND3 g410(.A(new_n783_), .B(new_n781_), .C(new_n780_), .Y(new_n784_));
NOT g411(.A(\8 ), .Y(new_n785_));
NOR2 g412(.A(new_n766_), .B(\305 ), .Y(new_n786_));
NOR2 g413(.A(new_n748_), .B(\269 ), .Y(new_n787_));
NOR2 g414(.A(new_n787_), .B(new_n786_), .Y(new_n788_));
NOR2 g415(.A(new_n788_), .B(new_n785_), .Y(new_n789_));
NAND2 g416(.A(\2014 ), .B(\8 ), .Y(new_n790_));
XOR2 g417(.A(new_n790_), .B(new_n789_), .Y(new_n791_));
NOR2 g418(.A(new_n766_), .B(\309 ), .Y(new_n792_));
NOR2 g419(.A(new_n748_), .B(\272 ), .Y(new_n793_));
NOR2 g420(.A(new_n793_), .B(new_n792_), .Y(new_n794_));
NOR2 g421(.A(new_n794_), .B(new_n785_), .Y(new_n795_));
NAND2 g422(.A(\2016 ), .B(\8 ), .Y(new_n796_));
XOR2 g423(.A(new_n796_), .B(new_n795_), .Y(new_n797_));
NOR3 g424(.A(new_n748_), .B(\275 ), .C(new_n785_), .Y(new_n798_));
NAND3 g425(.A(new_n766_), .B(\2018 ), .C(\8 ), .Y(new_n799_));
XNOR2 g426(.A(new_n799_), .B(new_n798_), .Y(new_n800_));
NOT g427(.A(\278 ), .Y(new_n801_));
NAND3 g428(.A(new_n766_), .B(new_n801_), .C(\8 ), .Y(new_n802_));
NAND3 g429(.A(new_n766_), .B(\2020 ), .C(\8 ), .Y(new_n803_));
XOR2 g430(.A(new_n803_), .B(new_n802_), .Y(new_n804_));
NOR2 g431(.A(new_n804_), .B(new_n800_), .Y(new_n805_));
NOR2 g432(.A(new_n766_), .B(\301 ), .Y(new_n806_));
NOR2 g433(.A(new_n748_), .B(\266 ), .Y(new_n807_));
NOR2 g434(.A(new_n807_), .B(new_n806_), .Y(new_n808_));
XOR2 g435(.A(new_n808_), .B(\2012 ), .Y(new_n809_));
AND2 g436(.A(new_n809_), .B(new_n805_), .Y(new_n810_));
NAND4 g437(.A(new_n810_), .B(new_n797_), .C(new_n791_), .D(new_n784_), .Y(new_n811_));
NOT g438(.A(new_n804_), .Y(new_n812_));
NOR3 g439(.A(new_n808_), .B(new_n800_), .C(\2012 ), .Y(new_n813_));
NAND4 g440(.A(new_n813_), .B(new_n812_), .C(new_n797_), .D(new_n791_), .Y(new_n814_));
NAND4 g441(.A(new_n805_), .B(new_n797_), .C(new_n790_), .D(new_n789_), .Y(new_n815_));
NAND3 g442(.A(new_n805_), .B(new_n796_), .C(new_n795_), .Y(new_n816_));
NAND4 g443(.A(new_n803_), .B(new_n766_), .C(new_n801_), .D(\8 ), .Y(new_n817_));
NAND3 g444(.A(new_n812_), .B(new_n799_), .C(new_n798_), .Y(new_n818_));
AND3 g445(.A(new_n818_), .B(new_n817_), .C(new_n816_), .Y(new_n819_));
NAND4 g446(.A(new_n819_), .B(new_n815_), .C(new_n814_), .D(new_n811_), .Y(new_n820_));
OR2 g447(.A(new_n820_), .B(new_n765_), .Y(new_n821_));
NAND3 g448(.A(new_n749_), .B(new_n747_), .C(\2022 ), .Y(new_n822_));
OR3 g449(.A(new_n750_), .B(new_n748_), .C(\281 ), .Y(new_n823_));
XNOR2 g450(.A(new_n823_), .B(new_n822_), .Y(new_n824_));
NAND4 g451(.A(new_n824_), .B(new_n761_), .C(new_n756_), .D(new_n753_), .Y(new_n825_));
NAND2 g452(.A(new_n825_), .B(new_n765_), .Y(new_n826_));
NAND2 g453(.A(new_n826_), .B(new_n820_), .Y(new_n827_));
NAND2 g454(.A(new_n827_), .B(new_n821_), .Y(\3851 ));
NOR3 g455(.A(\2971 ), .B(\2970 ), .C(new_n394_), .Y(new_n830_));
NAND4 g456(.A(new_n830_), .B(new_n743_), .C(new_n715_), .D(new_n515_), .Y(\3882 ));
NOT g457(.A(\3882 ), .Y(\3881 ));
assign \3875 = 1'b0;
BUF g458(.A(\219 ), .Y(\398 ));
BUF g459(.A(\219 ), .Y(\400 ));
BUF g460(.A(\219 ), .Y(\401 ));
BUF g461(.A(\253 ), .Y(\419 ));
BUF g462(.A(\253 ), .Y(\420 ));
BUF g463(.A(\290 ), .Y(\456 ));
BUF g464(.A(\290 ), .Y(\457 ));
BUF g465(.A(\290 ), .Y(\458 ));
BUF g466(.A(\219 ), .Y(\805 ));
NAND2 g467(.A(new_n472_), .B(new_n471_), .Y(\2388 ));
NAND2 g468(.A(new_n475_), .B(new_n474_), .Y(\2390 ));
NAND2 g469(.A(new_n482_), .B(new_n481_), .Y(\2644 ));
NAND2 g470(.A(new_n732_), .B(new_n717_), .Y(\3804 ));
endmodule

59
ITC99BENCH/b01.bench
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@ -1,59 +0,0 @@
# generated by verilog2bench.py https://gitea.yuhangq.com/YuhangQ/any2bench
INPUT(NET_1)
INPUT(NET_2)
INPUT(NET_3)
INPUT(NET_4)
INPUT(NET_5)
INPUT(NET_6)
INPUT(NET_7)
OUTPUT(NET_112)
OUTPUT(NET_41)
OUTPUT(NET_42)
OUTPUT(NET_45)
OUTPUT(NET_46)
OUTPUT(NET_8)
OUTPUT(NET_9)
new_n15_ = NOT ( NET_3 )
NET_112 = AND ( NET_5, NET_4, new_n15_ )
new_n17_ = NAND ( NET_2, NET_1 )
new_n18_ = OR ( NET_2, NET_1 )
new_n19_ = AND ( new_n18_, new_n17_ )
new_n20_ = NOT ( NET_1 )
new_n21_ = NOT ( NET_2 )
new_n22_ = NOR ( new_n21_, new_n20_ )
new_n23_ = NOR ( new_n22_, NET_4 )
new_n24_ = NAND ( new_n23_, new_n19_, NET_3 )
new_n25_ = NAND ( new_n23_, NET_5, NET_3 )
new_n26_ = NAND ( NET_4, NET_3 )
new_n27_ = NAND ( new_n26_, new_n22_ )
new_n28_ = NOT ( NET_4 )
new_n29_ = NOR ( NET_5, new_n28_ )
new_n30_ = NAND ( new_n29_, new_n15_ )
NET_41 = NAND ( new_n30_, new_n27_, new_n25_, new_n24_ )
new_n32_ = NAND ( new_n18_, new_n17_ )
new_n33_ = NAND ( new_n32_, new_n28_, NET_3 )
new_n34_ = NOR ( new_n29_, new_n15_ )
new_n35_ = OR ( new_n34_, new_n32_ )
new_n36_ = NAND ( new_n32_, NET_5, NET_3 )
NET_42 = NAND ( new_n36_, new_n35_, new_n33_ )
new_n38_ = NAND ( new_n19_, NET_5, NET_3 )
new_n39_ = NAND ( new_n29_, new_n22_ )
new_n40_ = AND ( new_n39_, new_n38_ )
new_n41_ = OR ( new_n33_, new_n22_ )
new_n42_ = NAND ( new_n17_, NET_5, new_n28_ )
new_n43_ = NAND ( new_n22_, NET_5, NET_3 )
new_n44_ = AND ( new_n43_, new_n42_, new_n30_ )
NET_45 = NAND ( new_n44_, new_n41_, new_n40_ )
new_n46_ = NOT ( NET_5 )
new_n47_ = NOR ( new_n46_, NET_4 )
new_n48_ = NOR ( new_n47_, NET_3 )
new_n49_ = OR ( new_n48_, new_n17_ )
new_n50_ = NAND ( new_n17_, new_n46_, new_n28_, new_n15_ )
new_n51_ = NAND ( new_n17_, NET_112 )
new_n52_ = AND ( new_n51_, new_n50_ )
NET_46 = NAND ( new_n52_, new_n49_, new_n40_, new_n24_ )
NET_8 = BUF ( NET_6 )
NET_9 = BUF ( NET_7 )

35
ITC99BENCH/b02.bench
View File

@ -1,35 +0,0 @@
# generated by verilog2bench.py https://gitea.yuhangq.com/YuhangQ/any2bench
INPUT(NET_1)
INPUT(NET_2)
INPUT(NET_3)
INPUT(NET_4)
INPUT(NET_5)
OUTPUT(NET_12)
OUTPUT(NET_23)
OUTPUT(NET_27)
OUTPUT(NET_28)
OUTPUT(NET_6)
new_n11_ = NOT ( NET_3 )
new_n12_ = NOT ( NET_4 )
NET_12 = AND ( new_n12_, new_n11_, NET_2 )
new_n14_ = NOR ( new_n11_, NET_2 )
new_n15_ = NAND ( new_n14_, new_n12_ )
new_n16_ = NOR ( NET_3, NET_1 )
new_n17_ = NOR ( new_n16_, NET_2 )
new_n18_ = OR ( new_n17_, new_n12_ )
NET_23 = NAND ( new_n18_, new_n15_ )
new_n20_ = NOR ( new_n11_, NET_1 )
new_n21_ = OR ( new_n20_, NET_4 )
new_n22_ = NAND ( new_n21_, NET_2 )
new_n23_ = NOT ( NET_1 )
new_n24_ = NOR ( new_n14_, NET_4 )
new_n25_ = OR ( new_n24_, new_n23_ )
new_n26_ = NAND ( NET_4, NET_3 )
NET_27 = NAND ( new_n26_, new_n25_, new_n22_ )
new_n28_ = NOR ( NET_4, NET_2, NET_1 )
new_n29_ = NOR ( NET_2, new_n23_ )
new_n30_ = NOR ( new_n29_, new_n12_ )
new_n31_ = NOR ( new_n30_, NET_3 )
NET_28 = OR ( new_n31_, new_n28_ )
NET_6 = BUF ( NET_5 )
NET_2313123 = DFF ( NET_5 )

187
ITC99BENCH/b03.bench
View File

@ -1,187 +0,0 @@
# generated by verilog2bench.py https://gitea.yuhangq.com/YuhangQ/any2bench
INPUT(NET_1)
INPUT(NET_10)
INPUT(NET_11)
INPUT(NET_12)
INPUT(NET_13)
INPUT(NET_14)
INPUT(NET_15)
INPUT(NET_16)
INPUT(NET_17)
INPUT(NET_18)
INPUT(NET_19)
INPUT(NET_2)
INPUT(NET_20)
INPUT(NET_21)
INPUT(NET_22)
INPUT(NET_23)
INPUT(NET_24)
INPUT(NET_25)
INPUT(NET_26)
INPUT(NET_27)
INPUT(NET_28)
INPUT(NET_29)
INPUT(NET_3)
INPUT(NET_30)
INPUT(NET_31)
INPUT(NET_32)
INPUT(NET_33)
INPUT(NET_34)
INPUT(NET_4)
INPUT(NET_5)
INPUT(NET_6)
INPUT(NET_7)
INPUT(NET_8)
INPUT(NET_9)
OUTPUT(NET_100)
OUTPUT(NET_139)
OUTPUT(NET_140)
OUTPUT(NET_141)
OUTPUT(NET_142)
OUTPUT(NET_143)
OUTPUT(NET_144)
OUTPUT(NET_145)
OUTPUT(NET_146)
OUTPUT(NET_147)
OUTPUT(NET_148)
OUTPUT(NET_149)
OUTPUT(NET_150)
OUTPUT(NET_325)
OUTPUT(NET_35)
OUTPUT(NET_36)
OUTPUT(NET_37)
OUTPUT(NET_38)
OUTPUT(NET_57)
OUTPUT(NET_76)
OUTPUT(NET_77)
OUTPUT(NET_78)
OUTPUT(NET_79)
OUTPUT(NET_80)
OUTPUT(NET_81)
OUTPUT(NET_82)
OUTPUT(NET_83)
OUTPUT(NET_84)
OUTPUT(NET_85)
OUTPUT(NET_86)
OUTPUT(NET_87)
OUTPUT(NET_97)
OUTPUT(NET_98)
OUTPUT(NET_99)
new_n69_ = NOT ( NET_33 )
new_n70_ = NOR ( NET_31, NET_30, NET_27, NET_26 )
new_n71_ = OR ( new_n70_, new_n69_ )
new_n72_ = NOT ( new_n71_ )
new_n73_ = NAND ( new_n72_, NET_7, NET_6, NET_5 )
new_n74_ = NAND ( new_n71_, NET_20 )
NET_100 = NAND ( new_n74_, new_n73_ )
new_n76_ = NOT ( NET_28 )
new_n77_ = NOT ( NET_25 )
new_n78_ = OR ( NET_32, new_n77_ )
new_n79_ = OR ( new_n78_, NET_27 )
new_n80_ = NOT ( NET_32 )
new_n81_ = NOT ( NET_31 )
new_n82_ = NAND ( new_n81_, NET_29, new_n77_ )
new_n83_ = NAND ( new_n82_, new_n80_ )
new_n84_ = NAND ( NET_32, NET_30 )
new_n85_ = NAND ( new_n84_, new_n83_ )
new_n86_ = NAND ( new_n85_, new_n79_ )
new_n87_ = NAND ( new_n86_, NET_34, new_n76_ )
new_n88_ = NAND ( NET_34, NET_28 )
new_n89_ = OR ( new_n88_, NET_26 )
new_n90_ = NAND ( new_n89_, new_n87_, new_n71_ )
new_n91_ = NAND ( new_n90_, NET_8, NET_33 )
new_n92_ = NOT ( NET_5 )
new_n93_ = OR ( new_n90_, new_n92_ )
new_n94_ = NOR ( NET_32, NET_25 )
new_n95_ = OR ( new_n94_, NET_28 )
new_n96_ = NAND ( new_n95_, new_n90_, new_n69_ )
NET_139 = NAND ( new_n96_, new_n93_, new_n91_ )
new_n98_ = NAND ( new_n90_, NET_9, NET_33 )
new_n99_ = NOT ( NET_6 )
new_n100_ = OR ( new_n90_, new_n99_ )
new_n101_ = NAND ( new_n90_, new_n78_, new_n69_, new_n76_ )
NET_140 = NAND ( new_n101_, new_n100_, new_n98_ )
new_n103_ = NAND ( new_n90_, NET_33, NET_10 )
new_n104_ = NOT ( NET_7 )
new_n105_ = OR ( new_n90_, new_n104_ )
new_n106_ = NAND ( new_n90_, new_n69_, new_n80_, new_n76_ )
NET_141 = NAND ( new_n106_, new_n105_, new_n103_ )
new_n108_ = NAND ( new_n90_, NET_5, new_n69_ )
new_n109_ = NAND ( new_n89_, new_n87_, new_n71_, NET_8 )
new_n110_ = NAND ( new_n90_, NET_33, NET_11 )
NET_142 = NAND ( new_n110_, new_n109_, new_n108_ )
new_n112_ = NAND ( new_n90_, NET_6, new_n69_ )
new_n113_ = NAND ( new_n89_, new_n87_, new_n71_, NET_9 )
new_n114_ = NAND ( new_n90_, NET_33, NET_12 )
NET_143 = NAND ( new_n114_, new_n113_, new_n112_ )
new_n116_ = NAND ( new_n90_, NET_7, new_n69_ )
new_n117_ = NAND ( new_n89_, new_n87_, new_n71_, NET_10 )
new_n118_ = NAND ( new_n90_, NET_33, NET_13 )
NET_144 = NAND ( new_n118_, new_n117_, new_n116_ )
new_n120_ = NAND ( new_n90_, NET_8, new_n69_ )
new_n121_ = NAND ( new_n89_, new_n87_, new_n71_, NET_11 )
new_n122_ = NAND ( new_n90_, NET_33, NET_14 )
NET_145 = NAND ( new_n122_, new_n121_, new_n120_ )
new_n124_ = NAND ( new_n90_, NET_9, new_n69_ )
new_n125_ = NAND ( new_n89_, new_n87_, new_n71_, NET_12 )
new_n126_ = NAND ( new_n90_, NET_33, NET_15 )
NET_146 = NAND ( new_n126_, new_n125_, new_n124_ )
new_n128_ = NAND ( new_n90_, new_n69_, NET_10 )
new_n129_ = NAND ( new_n89_, new_n87_, new_n71_, NET_13 )
new_n130_ = NAND ( new_n90_, NET_33, NET_16 )
NET_147 = NAND ( new_n130_, new_n129_, new_n128_ )
new_n132_ = NAND ( new_n90_, new_n69_, NET_11 )
new_n133_ = NAND ( new_n89_, new_n87_, new_n71_, NET_14 )
NET_148 = NAND ( new_n133_, new_n132_ )
new_n135_ = NAND ( new_n90_, new_n69_, NET_12 )
new_n136_ = NAND ( new_n89_, new_n87_, new_n71_, NET_15 )
NET_149 = NAND ( new_n136_, new_n135_ )
new_n138_ = NAND ( new_n90_, new_n69_, NET_13 )
new_n139_ = NAND ( new_n89_, new_n87_, new_n71_, NET_16 )
NET_150 = NAND ( new_n139_, new_n138_ )
NET_325 = NOT ( NET_34 )
new_n142_ = NAND ( NET_325, NET_26 )
NET_76 = NAND ( new_n142_, new_n88_ )
new_n144_ = NAND ( NET_325, NET_1 )
NET_77 = NAND ( new_n144_, new_n88_ )
new_n146_ = NAND ( NET_325, NET_21 )
new_n147_ = NAND ( NET_34, NET_17 )
NET_78 = NAND ( new_n147_, new_n146_ )
new_n149_ = NAND ( NET_325, NET_22 )
new_n150_ = NAND ( NET_34, NET_18 )
NET_79 = NAND ( new_n150_, new_n149_ )
new_n152_ = NAND ( NET_325, NET_23 )
new_n153_ = NAND ( NET_34, NET_19 )
NET_80 = NAND ( new_n153_, new_n152_ )
new_n155_ = NAND ( NET_325, NET_24 )
new_n156_ = NAND ( NET_34, NET_20 )
NET_81 = NAND ( new_n156_, new_n155_ )
new_n158_ = NAND ( NET_325, NET_3 )
new_n159_ = NAND ( NET_34, NET_25 )
NET_82 = NAND ( new_n159_, new_n158_ )
new_n161_ = NAND ( NET_325, NET_27 )
NET_83 = NAND ( new_n161_, new_n159_ )
new_n163_ = NAND ( NET_4, NET_325 )
new_n164_ = NAND ( NET_34, NET_29 )
NET_84 = NAND ( new_n164_, new_n163_ )
new_n166_ = NAND ( NET_325, NET_30 )
new_n167_ = NAND ( NET_34, NET_32 )
NET_85 = NAND ( new_n167_, new_n166_ )
new_n169_ = OR ( NET_34, new_n81_ )
NET_86 = NAND ( new_n169_, new_n164_ )
new_n171_ = NAND ( NET_325, NET_2 )
NET_87 = NAND ( new_n171_, new_n167_ )
new_n173_ = NAND ( new_n72_, new_n104_, new_n99_, NET_5 )
new_n174_ = NAND ( new_n71_, NET_17 )
NET_97 = NAND ( new_n174_, new_n173_ )
new_n176_ = NAND ( new_n72_, new_n104_, NET_6, new_n92_ )
new_n177_ = NAND ( new_n71_, NET_18 )
NET_98 = NAND ( new_n177_, new_n176_ )
new_n179_ = NAND ( new_n72_, NET_7, new_n99_, new_n92_ )
new_n180_ = NAND ( new_n71_, NET_19 )
NET_99 = NAND ( new_n180_, new_n179_ )
NET_35 = BUF ( NET_21 )
NET_36 = BUF ( NET_22 )
NET_37 = BUF ( NET_23 )
NET_38 = BUF ( NET_24 )
NET_57 = BUF ( NET_34 )

662
ITC99BENCH/b04.bench
View File

@ -1,662 +0,0 @@
# generated by verilog2bench.py https://gitea.yuhangq.com/YuhangQ/any2bench
INPUT(NET_1)
INPUT(NET_10)
INPUT(NET_11)
INPUT(NET_12)
INPUT(NET_13)
INPUT(NET_14)
INPUT(NET_15)
INPUT(NET_16)
INPUT(NET_17)
INPUT(NET_18)
INPUT(NET_19)
INPUT(NET_2)
INPUT(NET_20)
INPUT(NET_21)
INPUT(NET_22)
INPUT(NET_23)
INPUT(NET_24)
INPUT(NET_25)
INPUT(NET_26)
INPUT(NET_27)
INPUT(NET_28)
INPUT(NET_29)
INPUT(NET_3)
INPUT(NET_30)
INPUT(NET_31)
INPUT(NET_32)
INPUT(NET_33)
INPUT(NET_34)
INPUT(NET_35)
INPUT(NET_36)
INPUT(NET_37)
INPUT(NET_38)
INPUT(NET_39)
INPUT(NET_4)
INPUT(NET_40)
INPUT(NET_41)
INPUT(NET_42)
INPUT(NET_43)
INPUT(NET_44)
INPUT(NET_45)
INPUT(NET_46)
INPUT(NET_47)
INPUT(NET_48)
INPUT(NET_49)
INPUT(NET_5)
INPUT(NET_50)
INPUT(NET_51)
INPUT(NET_52)
INPUT(NET_53)
INPUT(NET_54)
INPUT(NET_55)
INPUT(NET_56)
INPUT(NET_57)
INPUT(NET_58)
INPUT(NET_59)
INPUT(NET_6)
INPUT(NET_60)
INPUT(NET_61)
INPUT(NET_62)
INPUT(NET_63)
INPUT(NET_64)
INPUT(NET_65)
INPUT(NET_66)
INPUT(NET_67)
INPUT(NET_68)
INPUT(NET_69)
INPUT(NET_7)
INPUT(NET_70)
INPUT(NET_71)
INPUT(NET_72)
INPUT(NET_73)
INPUT(NET_74)
INPUT(NET_75)
INPUT(NET_76)
INPUT(NET_77)
INPUT(NET_8)
INPUT(NET_9)
OUTPUT(NET_1308)
OUTPUT(NET_1309)
OUTPUT(NET_344)
OUTPUT(NET_345)
OUTPUT(NET_346)
OUTPUT(NET_347)
OUTPUT(NET_348)
OUTPUT(NET_349)
OUTPUT(NET_350)
OUTPUT(NET_351)
OUTPUT(NET_352)
OUTPUT(NET_353)
OUTPUT(NET_354)
OUTPUT(NET_355)
OUTPUT(NET_356)
OUTPUT(NET_357)
OUTPUT(NET_358)
OUTPUT(NET_359)
OUTPUT(NET_360)
OUTPUT(NET_361)
OUTPUT(NET_362)
OUTPUT(NET_363)
OUTPUT(NET_364)
OUTPUT(NET_365)
OUTPUT(NET_366)
OUTPUT(NET_367)
OUTPUT(NET_368)
OUTPUT(NET_369)
OUTPUT(NET_370)
OUTPUT(NET_371)
OUTPUT(NET_372)
OUTPUT(NET_373)
OUTPUT(NET_374)
OUTPUT(NET_375)
OUTPUT(NET_376)
OUTPUT(NET_377)
OUTPUT(NET_378)
OUTPUT(NET_379)
OUTPUT(NET_380)
OUTPUT(NET_381)
OUTPUT(NET_382)
OUTPUT(NET_383)
OUTPUT(NET_489)
OUTPUT(NET_490)
OUTPUT(NET_491)
OUTPUT(NET_492)
OUTPUT(NET_493)
OUTPUT(NET_494)
OUTPUT(NET_495)
OUTPUT(NET_496)
OUTPUT(NET_530)
OUTPUT(NET_531)
OUTPUT(NET_532)
OUTPUT(NET_533)
OUTPUT(NET_534)
OUTPUT(NET_535)
OUTPUT(NET_536)
OUTPUT(NET_537)
OUTPUT(NET_572)
OUTPUT(NET_573)
OUTPUT(NET_574)
OUTPUT(NET_583)
OUTPUT(NET_589)
OUTPUT(NET_593)
OUTPUT(NET_596)
OUTPUT(NET_597)
OUTPUT(NET_78)
OUTPUT(NET_79)
OUTPUT(NET_80)
OUTPUT(NET_81)
OUTPUT(NET_82)
OUTPUT(NET_83)
OUTPUT(NET_84)
OUTPUT(NET_85)
new_n152_ = NOT ( NET_77 )
new_n153_ = NOR ( new_n152_, NET_76 )
new_n154_ = NOT ( NET_76 )
new_n155_ = NOR ( NET_77, new_n154_ )
NET_1308 = OR ( new_n155_, new_n153_ )
NET_1309 = NOR ( NET_77, NET_76 )
new_n158_ = NOT ( NET_4 )
new_n159_ = NOR ( NET_77, NET_3 )
new_n160_ = OR ( new_n159_, new_n154_ )
new_n161_ = OR ( new_n160_, new_n158_ )
new_n162_ = NOT ( NET_28 )
new_n163_ = NOR ( new_n159_, NET_1309 )
new_n164_ = OR ( new_n163_, new_n162_ )
NET_344 = NAND ( new_n164_, new_n161_ )
new_n166_ = NOT ( NET_5 )
new_n167_ = OR ( new_n160_, new_n166_ )
new_n168_ = NOT ( NET_29 )
new_n169_ = OR ( new_n163_, new_n168_ )
NET_345 = NAND ( new_n169_, new_n167_ )
new_n171_ = NOT ( NET_6 )
new_n172_ = OR ( new_n160_, new_n171_ )
new_n173_ = NOT ( NET_30 )
new_n174_ = OR ( new_n163_, new_n173_ )
NET_346 = NAND ( new_n174_, new_n172_ )
new_n176_ = NOT ( NET_7 )
new_n177_ = OR ( new_n160_, new_n176_ )
new_n178_ = NOT ( NET_31 )
new_n179_ = OR ( new_n163_, new_n178_ )
NET_347 = NAND ( new_n179_, new_n177_ )
new_n181_ = NOT ( NET_8 )
new_n182_ = OR ( new_n160_, new_n181_ )
new_n183_ = NOT ( NET_32 )
new_n184_ = OR ( new_n163_, new_n183_ )
NET_348 = NAND ( new_n184_, new_n182_ )
new_n186_ = NOT ( NET_9 )
new_n187_ = OR ( new_n160_, new_n186_ )
new_n188_ = NOT ( NET_33 )
new_n189_ = OR ( new_n163_, new_n188_ )
NET_349 = NAND ( new_n189_, new_n187_ )
new_n191_ = NOT ( NET_10 )
new_n192_ = OR ( new_n160_, new_n191_ )
new_n193_ = NOT ( NET_34 )
new_n194_ = OR ( new_n163_, new_n193_ )
NET_350 = NAND ( new_n194_, new_n192_ )
new_n196_ = NOT ( NET_11 )
new_n197_ = OR ( new_n160_, new_n196_ )
new_n198_ = NOT ( NET_35 )
new_n199_ = OR ( new_n163_, new_n198_ )
NET_351 = NAND ( new_n199_, new_n197_ )
new_n201_ = NAND ( new_n155_, NET_4 )
new_n202_ = NOT ( NET_36 )
new_n203_ = OR ( NET_1308, new_n202_ )
NET_352 = NAND ( new_n203_, new_n201_ )
new_n205_ = NAND ( new_n155_, NET_5 )
new_n206_ = NOT ( NET_37 )
new_n207_ = OR ( NET_1308, new_n206_ )
NET_353 = NAND ( new_n207_, new_n205_ )
new_n209_ = NAND ( new_n155_, NET_6 )
new_n210_ = NOT ( NET_38 )
new_n211_ = OR ( NET_1308, new_n210_ )
NET_354 = NAND ( new_n211_, new_n209_ )
new_n213_ = NAND ( new_n155_, NET_7 )
new_n214_ = NOT ( NET_39 )
new_n215_ = OR ( NET_1308, new_n214_ )
NET_355 = NAND ( new_n215_, new_n213_ )
new_n217_ = NAND ( new_n155_, NET_8 )
new_n218_ = NOT ( NET_40 )
new_n219_ = OR ( NET_1308, new_n218_ )
NET_356 = NAND ( new_n219_, new_n217_ )
new_n221_ = NAND ( new_n155_, NET_9 )
new_n222_ = NOT ( NET_41 )
new_n223_ = OR ( NET_1308, new_n222_ )
NET_357 = NAND ( new_n223_, new_n221_ )
new_n225_ = NAND ( new_n155_, NET_10 )
new_n226_ = NOT ( NET_42 )
new_n227_ = OR ( NET_1308, new_n226_ )
NET_358 = NAND ( new_n227_, new_n225_ )
new_n229_ = NAND ( new_n155_, NET_11 )
new_n230_ = NOT ( NET_43 )
new_n231_ = OR ( NET_1308, new_n230_ )
NET_359 = NAND ( new_n231_, new_n229_ )
new_n233_ = NAND ( new_n155_, NET_36 )
new_n234_ = NOT ( NET_44 )
new_n235_ = OR ( NET_1308, new_n234_ )
NET_360 = NAND ( new_n235_, new_n233_ )
new_n237_ = NAND ( new_n155_, NET_37 )
new_n238_ = NOT ( NET_45 )
new_n239_ = OR ( NET_1308, new_n238_ )
NET_361 = NAND ( new_n239_, new_n237_ )
new_n241_ = NAND ( new_n155_, NET_38 )
new_n242_ = NOT ( NET_46 )
new_n243_ = OR ( NET_1308, new_n242_ )
NET_362 = NAND ( new_n243_, new_n241_ )
new_n245_ = NAND ( new_n155_, NET_39 )
new_n246_ = NOT ( NET_47 )
new_n247_ = OR ( NET_1308, new_n246_ )
NET_363 = NAND ( new_n247_, new_n245_ )
new_n249_ = NAND ( new_n155_, NET_40 )
new_n250_ = NOT ( NET_48 )
new_n251_ = OR ( NET_1308, new_n250_ )
NET_364 = NAND ( new_n251_, new_n249_ )
new_n253_ = NAND ( new_n155_, NET_41 )
new_n254_ = NOT ( NET_49 )
new_n255_ = OR ( NET_1308, new_n254_ )
NET_365 = NAND ( new_n255_, new_n253_ )
new_n257_ = NAND ( new_n155_, NET_42 )
new_n258_ = NOT ( NET_50 )
new_n259_ = OR ( NET_1308, new_n258_ )
NET_366 = NAND ( new_n259_, new_n257_ )
new_n261_ = NAND ( new_n155_, NET_43 )
new_n262_ = NOT ( NET_51 )
new_n263_ = OR ( NET_1308, new_n262_ )
NET_367 = NAND ( new_n263_, new_n261_ )
new_n265_ = NAND ( new_n155_, NET_44 )
new_n266_ = NOT ( NET_52 )
new_n267_ = OR ( NET_1308, new_n266_ )
NET_368 = NAND ( new_n267_, new_n265_ )
new_n269_ = NAND ( new_n155_, NET_45 )
new_n270_ = NOT ( NET_53 )
new_n271_ = OR ( NET_1308, new_n270_ )
NET_369 = NAND ( new_n271_, new_n269_ )
new_n273_ = NAND ( new_n155_, NET_46 )
new_n274_ = NOT ( NET_54 )
new_n275_ = OR ( NET_1308, new_n274_ )
NET_370 = NAND ( new_n275_, new_n273_ )
new_n277_ = NAND ( new_n155_, NET_47 )
new_n278_ = NOT ( NET_55 )
new_n279_ = OR ( NET_1308, new_n278_ )
NET_371 = NAND ( new_n279_, new_n277_ )
new_n281_ = NAND ( new_n155_, NET_48 )
new_n282_ = NOT ( NET_56 )
new_n283_ = OR ( NET_1308, new_n282_ )
NET_372 = NAND ( new_n283_, new_n281_ )
new_n285_ = NAND ( new_n155_, NET_49 )
new_n286_ = NOT ( NET_57 )
new_n287_ = OR ( NET_1308, new_n286_ )
NET_373 = NAND ( new_n287_, new_n285_ )
new_n289_ = NAND ( new_n155_, NET_50 )
new_n290_ = NOT ( NET_58 )
new_n291_ = OR ( NET_1308, new_n290_ )
NET_374 = NAND ( new_n291_, new_n289_ )
new_n293_ = NAND ( new_n155_, NET_51 )
new_n294_ = NOT ( NET_59 )
new_n295_ = OR ( NET_1308, new_n294_ )
NET_375 = NAND ( new_n295_, new_n293_ )
new_n297_ = NAND ( new_n155_, NET_52 )
new_n298_ = NOT ( NET_60 )
new_n299_ = OR ( NET_1308, new_n298_ )
NET_376 = NAND ( new_n299_, new_n297_ )
new_n301_ = NAND ( new_n155_, NET_53 )
new_n302_ = NOT ( NET_61 )
new_n303_ = OR ( NET_1308, new_n302_ )
NET_377 = NAND ( new_n303_, new_n301_ )
new_n305_ = NAND ( new_n155_, NET_54 )
new_n306_ = NOT ( NET_62 )
new_n307_ = OR ( NET_1308, new_n306_ )
NET_378 = NAND ( new_n307_, new_n305_ )
new_n309_ = NAND ( new_n155_, NET_55 )
new_n310_ = NOT ( NET_63 )
new_n311_ = OR ( NET_1308, new_n310_ )
NET_379 = NAND ( new_n311_, new_n309_ )
new_n313_ = NAND ( new_n155_, NET_56 )
new_n314_ = NOT ( NET_64 )
new_n315_ = OR ( NET_1308, new_n314_ )
NET_380 = NAND ( new_n315_, new_n313_ )
new_n317_ = NAND ( new_n155_, NET_57 )
new_n318_ = NOT ( NET_65 )
new_n319_ = OR ( NET_1308, new_n318_ )
NET_381 = NAND ( new_n319_, new_n317_ )
new_n321_ = NAND ( new_n155_, NET_58 )
new_n322_ = NOT ( NET_66 )
new_n323_ = OR ( NET_1308, new_n322_ )
NET_382 = NAND ( new_n323_, new_n321_ )
new_n325_ = NAND ( new_n155_, NET_59 )
new_n326_ = NOT ( NET_67 )
new_n327_ = OR ( NET_1308, new_n326_ )
NET_383 = NAND ( new_n327_, new_n325_ )
new_n329_ = NOT ( NET_1309 )
new_n330_ = NAND ( new_n158_, NET_12 )
new_n331_ = AND ( NET_18, new_n191_ )
new_n332_ = OR ( new_n331_, NET_19, new_n196_ )
new_n333_ = OR ( new_n186_, NET_17 )
new_n334_ = OR ( NET_18, new_n191_ )
new_n335_ = NAND ( new_n334_, new_n333_, new_n332_ )
new_n336_ = NAND ( new_n181_, NET_16 )
new_n337_ = NAND ( new_n186_, NET_17 )
new_n338_ = NAND ( new_n337_, new_n336_, new_n335_ )
new_n339_ = OR ( new_n176_, NET_15 )
new_n340_ = OR ( new_n181_, NET_16 )
new_n341_ = NAND ( new_n340_, new_n339_, new_n338_ )
new_n342_ = NAND ( new_n171_, NET_14 )
new_n343_ = NAND ( new_n176_, NET_15 )
new_n344_ = NAND ( new_n343_, new_n342_, new_n341_ )
new_n345_ = OR ( new_n166_, NET_13 )
new_n346_ = OR ( new_n171_, NET_14 )
new_n347_ = NAND ( new_n346_, new_n345_, new_n344_ )
new_n348_ = OR ( new_n158_, NET_12 )
new_n349_ = NAND ( new_n166_, NET_13 )
new_n350_ = NAND ( new_n349_, new_n348_, new_n347_ )
new_n351_ = AND ( new_n350_, new_n330_ )
new_n352_ = NAND ( new_n351_, new_n152_ )
new_n353_ = NAND ( new_n352_, new_n329_ )
new_n354_ = NAND ( new_n353_, NET_12 )
new_n355_ = OR ( new_n351_, new_n154_ )
new_n356_ = NAND ( new_n355_, new_n152_ )
new_n357_ = NAND ( new_n356_, NET_4 )
NET_489 = NAND ( new_n357_, new_n354_ )
new_n359_ = NAND ( new_n353_, NET_13 )
new_n360_ = NAND ( new_n356_, NET_5 )
NET_490 = NAND ( new_n360_, new_n359_ )
new_n362_ = NAND ( new_n353_, NET_14 )
new_n363_ = NAND ( new_n356_, NET_6 )
NET_491 = NAND ( new_n363_, new_n362_ )
new_n365_ = NAND ( new_n353_, NET_15 )
new_n366_ = NAND ( new_n356_, NET_7 )
NET_492 = NAND ( new_n366_, new_n365_ )
new_n368_ = NAND ( new_n353_, NET_16 )
new_n369_ = NAND ( new_n356_, NET_8 )
NET_493 = NAND ( new_n369_, new_n368_ )
new_n371_ = NAND ( new_n353_, NET_17 )
new_n372_ = NAND ( new_n356_, NET_9 )
NET_494 = NAND ( new_n372_, new_n371_ )
new_n374_ = NAND ( new_n353_, NET_18 )
new_n375_ = NAND ( new_n356_, NET_10 )
NET_495 = NAND ( new_n375_, new_n374_ )
new_n377_ = NAND ( new_n353_, NET_19 )
new_n378_ = NAND ( new_n356_, NET_11 )
NET_496 = NAND ( new_n378_, new_n377_ )
new_n380_ = OR ( new_n158_, NET_20 )
new_n381_ = OR ( NET_26, new_n191_ )
new_n382_ = NAND ( new_n381_, NET_27, new_n196_ )
new_n383_ = NAND ( new_n186_, NET_25 )
new_n384_ = NAND ( NET_26, new_n191_ )
new_n385_ = NAND ( new_n384_, new_n383_, new_n382_ )
new_n386_ = OR ( new_n181_, NET_24 )
new_n387_ = OR ( new_n186_, NET_25 )
new_n388_ = NAND ( new_n387_, new_n386_, new_n385_ )
new_n389_ = NAND ( new_n176_, NET_23 )
new_n390_ = NAND ( new_n181_, NET_24 )
new_n391_ = NAND ( new_n390_, new_n389_, new_n388_ )
new_n392_ = OR ( new_n171_, NET_22 )
new_n393_ = OR ( new_n176_, NET_23 )
new_n394_ = NAND ( new_n393_, new_n392_, new_n391_ )
new_n395_ = NAND ( new_n166_, NET_21 )
new_n396_ = NAND ( new_n171_, NET_22 )
new_n397_ = NAND ( new_n396_, new_n395_, new_n394_ )
new_n398_ = NAND ( new_n158_, NET_20 )
new_n399_ = OR ( new_n166_, NET_21 )
new_n400_ = NAND ( new_n399_, new_n398_, new_n397_ )
new_n401_ = NAND ( new_n400_, new_n380_ )
new_n402_ = NAND ( new_n401_, new_n351_, NET_76 )
new_n403_ = NAND ( new_n402_, new_n152_ )
new_n404_ = NAND ( new_n403_, NET_4 )
new_n405_ = NAND ( new_n401_, new_n351_ )
new_n406_ = NAND ( new_n405_, new_n152_ )
new_n407_ = NAND ( new_n406_, new_n329_ )
new_n408_ = NAND ( new_n407_, NET_20 )
NET_530 = NAND ( new_n408_, new_n404_ )
new_n410_ = NAND ( new_n403_, NET_5 )
new_n411_ = NAND ( new_n407_, NET_21 )
NET_531 = NAND ( new_n411_, new_n410_ )
new_n413_ = NAND ( new_n403_, NET_6 )
new_n414_ = NAND ( new_n407_, NET_22 )
NET_532 = NAND ( new_n414_, new_n413_ )
new_n416_ = NAND ( new_n403_, NET_7 )
new_n417_ = NAND ( new_n407_, NET_23 )
NET_533 = NAND ( new_n417_, new_n416_ )
new_n419_ = NAND ( new_n403_, NET_8 )
new_n420_ = NAND ( new_n407_, NET_24 )
NET_534 = NAND ( new_n420_, new_n419_ )
new_n422_ = NAND ( new_n403_, NET_9 )
new_n423_ = NAND ( new_n407_, NET_25 )
NET_535 = NAND ( new_n423_, new_n422_ )
new_n425_ = NAND ( new_n403_, NET_10 )
new_n426_ = NAND ( new_n407_, NET_26 )
NET_536 = NAND ( new_n426_, new_n425_ )
new_n428_ = NAND ( new_n403_, NET_11 )
new_n429_ = NAND ( new_n407_, NET_27 )
NET_537 = NAND ( new_n429_, new_n428_ )
new_n431_ = OR ( new_n181_, NET_1 )
new_n432_ = NAND ( NET_16, NET_1 )
new_n433_ = NAND ( new_n432_, new_n431_ )
new_n434_ = OR ( new_n314_, NET_1 )
new_n435_ = NAND ( NET_24, NET_1 )
new_n436_ = NAND ( new_n435_, new_n434_ )
new_n437_ = OR ( new_n436_, new_n433_ )
new_n438_ = NAND ( new_n436_, new_n433_ )
new_n439_ = NAND ( new_n438_, new_n437_ )
new_n440_ = OR ( new_n186_, NET_1 )
new_n441_ = NAND ( NET_17, NET_1 )
new_n442_ = NAND ( new_n441_, new_n440_ )
new_n443_ = OR ( new_n318_, NET_1 )
new_n444_ = NAND ( NET_25, NET_1 )
new_n445_ = NAND ( new_n444_, new_n443_ )
new_n446_ = NAND ( new_n445_, new_n442_ )
new_n447_ = OR ( new_n196_, NET_1 )
new_n448_ = NAND ( NET_19, NET_1 )
new_n449_ = NAND ( new_n448_, new_n447_ )
new_n450_ = OR ( new_n326_, NET_1 )
new_n451_ = NAND ( NET_27, NET_1 )
new_n452_ = NAND ( new_n451_, new_n450_ )
new_n453_ = NAND ( new_n452_, new_n449_ )
new_n454_ = NOR ( NET_66, NET_1 )
new_n455_ = NOT ( NET_1 )
new_n456_ = NOR ( NET_26, new_n455_ )
new_n457_ = OR ( new_n456_, new_n454_ )
new_n458_ = OR ( new_n457_, new_n453_ )
new_n459_ = OR ( new_n191_, NET_1 )
new_n460_ = NAND ( NET_18, NET_1 )
new_n461_ = NAND ( new_n460_, new_n459_ )
new_n462_ = NAND ( new_n457_, new_n453_ )
new_n463_ = NAND ( new_n462_, new_n461_ )
new_n464_ = NAND ( new_n463_, new_n458_ )
new_n465_ = OR ( new_n445_, new_n442_ )
new_n466_ = NAND ( new_n465_, new_n464_ )
new_n467_ = NAND ( new_n466_, new_n446_, new_n439_ )
new_n468_ = NAND ( new_n466_, new_n446_ )
new_n469_ = NAND ( new_n468_, new_n438_, new_n437_ )
new_n470_ = NAND ( new_n469_, new_n467_ )
new_n471_ = NOT ( new_n155_ )
new_n472_ = NOT ( NET_3 )
new_n473_ = NOR ( new_n472_, NET_2 )
new_n474_ = NOR ( new_n473_, NET_1 )
new_n475_ = NOR ( new_n474_, new_n471_ )
new_n476_ = NOT ( new_n475_ )
new_n477_ = OR ( new_n158_, NET_1 )
new_n478_ = NAND ( NET_12, NET_1 )
new_n479_ = NAND ( new_n478_, new_n477_ )
new_n480_ = OR ( new_n298_, NET_1 )
new_n481_ = NAND ( NET_20, NET_1 )
new_n482_ = NAND ( new_n481_, new_n480_ )
new_n483_ = OR ( new_n166_, NET_1 )
new_n484_ = NAND ( NET_13, NET_1 )
new_n485_ = NAND ( new_n484_, new_n483_ )
new_n486_ = NOT ( new_n485_ )
new_n487_ = OR ( new_n302_, NET_1 )
new_n488_ = NAND ( NET_21, NET_1 )
new_n489_ = NAND ( new_n488_, new_n487_ )
new_n490_ = NOT ( new_n489_ )
new_n491_ = OR ( new_n322_, NET_1 )
new_n492_ = NAND ( NET_26, NET_1 )
new_n493_ = NAND ( new_n492_, new_n491_ )
new_n494_ = NAND ( new_n493_, new_n461_ )
new_n495_ = NAND ( new_n494_, new_n453_ )
new_n496_ = OR ( new_n493_, new_n461_ )
new_n497_ = NAND ( new_n496_, new_n495_, new_n465_ )
new_n498_ = NAND ( new_n497_, new_n446_, new_n438_ )
new_n499_ = OR ( new_n176_, NET_1 )
new_n500_ = NAND ( NET_15, NET_1 )
new_n501_ = NAND ( new_n500_, new_n499_ )
new_n502_ = OR ( new_n310_, NET_1 )
new_n503_ = NAND ( NET_23, NET_1 )
new_n504_ = NAND ( new_n503_, new_n502_ )
new_n505_ = OR ( new_n504_, new_n501_ )
new_n506_ = NAND ( new_n505_, new_n498_, new_n437_ )
new_n507_ = NAND ( new_n504_, new_n501_ )
new_n508_ = OR ( new_n171_, NET_1 )
new_n509_ = NAND ( NET_14, NET_1 )
new_n510_ = NAND ( new_n509_, new_n508_ )
new_n511_ = OR ( new_n306_, NET_1 )
new_n512_ = NAND ( NET_22, NET_1 )
new_n513_ = NAND ( new_n512_, new_n511_ )
new_n514_ = NAND ( new_n513_, new_n510_ )
new_n515_ = NAND ( new_n514_, new_n507_, new_n506_ )
new_n516_ = OR ( new_n489_, new_n485_ )
new_n517_ = NOR ( new_n513_, new_n510_ )
new_n518_ = NOT ( new_n517_ )
new_n519_ = NAND ( new_n518_, new_n516_, new_n515_ )
new_n521_ = NAND ( new_n482_, new_n479_ )
new_n522_ = OR ( new_n482_, new_n479_ )
new_n523_ = NAND ( new_n489_, new_n485_ )
new_n524_ = NAND ( new_n482_, new_n479_ )
new_n525_ = NAND ( new_n524_, new_n523_, new_n519_, new_n522_ )
new_n526_ = NAND ( new_n525_, new_n521_ )
new_n527_ = OR ( new_n526_, new_n476_ )
new_n528_ = OR ( new_n527_, new_n470_ )
new_n529_ = NAND ( new_n526_, new_n475_ )
new_n530_ = NOT ( new_n529_ )
new_n531_ = XOR ( new_n452_, new_n449_ )
new_n532_ = AND ( new_n452_, new_n449_ )
new_n533_ = OR ( new_n461_, new_n532_ )
new_n534_ = NAND ( new_n461_, new_n532_ )
new_n535_ = NAND ( new_n534_, new_n533_, new_n492_, new_n491_ )
new_n536_ = NOR ( new_n457_, new_n532_ )
new_n537_ = OR ( new_n536_, new_n461_ )
new_n538_ = NAND ( new_n461_, new_n458_ )
new_n539_ = NAND ( new_n538_, new_n537_ )
new_n540_ = NAND ( new_n539_, new_n535_ )
new_n541_ = OR ( new_n540_, new_n531_ )
new_n542_ = NAND ( new_n540_, new_n531_ )
new_n543_ = AND ( new_n542_, new_n541_ )
new_n544_ = NAND ( new_n465_, new_n446_ )
new_n545_ = XNOR ( new_n544_, new_n464_ )
new_n546_ = AND ( new_n545_, new_n541_ )
new_n547_ = NOR ( new_n545_, new_n541_ )
new_n548_ = NOR ( new_n547_, new_n546_ )
new_n549_ = OR ( new_n548_, new_n543_ )
new_n550_ = XOR ( new_n547_, new_n470_ )
new_n551_ = NAND ( new_n550_, new_n549_ )
new_n552_ = OR ( new_n550_, new_n549_ )
new_n553_ = NAND ( new_n552_, new_n551_, new_n530_ )
new_n554_ = AND ( new_n155_, NET_3, new_n455_ )
new_n555_ = NAND ( new_n554_, NET_2 )
new_n556_ = OR ( new_n555_, new_n318_ )
new_n557_ = NOT ( NET_73 )
new_n558_ = NOR ( NET_1308, new_n557_ )
new_n559_ = NAND ( new_n155_, new_n472_, new_n455_ )
new_n560_ = NOR ( new_n559_, new_n188_ )
new_n561_ = NOR ( new_n560_, new_n558_ )
NET_572 = NAND ( new_n561_, new_n556_, new_n553_, new_n528_ )
new_n563_ = NOT ( new_n527_ )
new_n564_ = NAND ( new_n545_, new_n563_ )
new_n565_ = NAND ( new_n548_, new_n543_ )
new_n566_ = NAND ( new_n565_, new_n549_, new_n530_ )
new_n567_ = OR ( new_n555_, new_n322_ )
new_n568_ = NOT ( NET_74 )
new_n569_ = NOR ( NET_1308, new_n568_ )
new_n570_ = NOR ( new_n559_, new_n193_ )
new_n571_ = NOR ( new_n570_, new_n569_ )
NET_573 = NAND ( new_n571_, new_n567_, new_n566_, new_n564_ )
new_n573_ = NAND ( new_n540_, new_n563_ )
new_n574_ = NAND ( new_n543_, new_n530_ )
new_n575_ = OR ( new_n555_, new_n326_ )
new_n576_ = NOT ( NET_75 )
new_n577_ = NOR ( NET_1308, new_n576_ )
new_n578_ = NOR ( new_n559_, new_n198_ )
new_n579_ = NOR ( new_n578_, new_n577_ )
NET_574 = NAND ( new_n579_, new_n575_, new_n574_, new_n573_ )
new_n581_ = NAND ( new_n547_, new_n470_ )
new_n582_ = NAND ( new_n468_, new_n437_ )
new_n583_ = NAND ( new_n582_, new_n438_ )
new_n584_ = XOR ( new_n504_, new_n501_ )
new_n585_ = XOR ( new_n584_, new_n583_ )
new_n586_ = NAND ( new_n585_, new_n581_ )
new_n587_ = OR ( new_n585_, new_n581_ )
new_n588_ = AND ( new_n587_, new_n586_ )
new_n589_ = NAND ( new_n588_, new_n552_ )
new_n590_ = OR ( new_n588_, new_n552_ )
new_n591_ = NAND ( new_n590_, new_n589_, new_n530_ )
new_n592_ = NAND ( new_n585_, new_n563_ )
new_n593_ = OR ( new_n555_, new_n314_ )
new_n594_ = NOT ( NET_72 )
new_n595_ = NOR ( NET_1308, new_n594_ )
new_n596_ = NOR ( new_n559_, new_n183_ )
new_n597_ = NOR ( new_n596_, new_n595_ )
NET_583 = NAND ( new_n597_, new_n593_, new_n592_, new_n591_ )
new_n599_ = NAND ( new_n507_, new_n582_, new_n438_ )
new_n600_ = NAND ( new_n599_, new_n505_ )
new_n601_ = NAND ( new_n518_, new_n514_ )
new_n602_ = XNOR ( new_n601_, new_n600_ )
new_n603_ = XNOR ( new_n602_, new_n587_ )
new_n604_ = NAND ( new_n603_, new_n590_ )
new_n605_ = OR ( new_n603_, new_n590_ )
new_n606_ = NAND ( new_n605_, new_n604_, new_n530_ )
new_n607_ = OR ( new_n602_, new_n527_ )
new_n608_ = OR ( new_n555_, new_n310_ )
new_n609_ = NOT ( NET_71 )
new_n610_ = NOR ( NET_1308, new_n609_ )
new_n611_ = NOR ( new_n559_, new_n178_ )
new_n612_ = NOR ( new_n611_, new_n610_ )
NET_589 = NAND ( new_n612_, new_n608_, new_n607_, new_n606_ )
new_n614_ = OR ( new_n600_, new_n517_ )
new_n615_ = OR ( new_n489_, new_n486_ )
new_n616_ = OR ( new_n490_, new_n485_ )
new_n617_ = NAND ( new_n616_, new_n615_, new_n614_, new_n514_ )
new_n618_ = NAND ( new_n600_, new_n514_ )
new_n619_ = NAND ( new_n616_, new_n615_ )
new_n620_ = NAND ( new_n619_, new_n618_, new_n518_ )
new_n621_ = NAND ( new_n620_, new_n617_ )
new_n622_ = NOR ( new_n585_, new_n581_ )
new_n623_ = AND ( new_n602_, new_n622_ )
new_n624_ = XOR ( new_n623_, new_n621_ )
new_n625_ = XNOR ( new_n624_, new_n605_ )
new_n626_ = NOR ( new_n625_, new_n529_ )
new_n627_ = OR ( new_n621_, new_n527_ )
new_n628_ = OR ( new_n555_, new_n306_ )
new_n629_ = NOT ( NET_70 )
new_n630_ = OR ( NET_1308, new_n629_ )
new_n631_ = OR ( new_n559_, new_n173_ )
new_n632_ = NAND ( new_n631_, new_n630_, new_n628_, new_n627_ )
NET_593 = OR ( new_n632_, new_n626_ )
new_n634_ = NOT ( NET_2 )
new_n635_ = NAND ( new_n554_, new_n634_ )
new_n636_ = NAND ( new_n155_, NET_1 )
new_n637_ = NAND ( new_n636_, new_n635_ )
new_n638_ = AND ( new_n637_, new_n526_ )
new_n639_ = NAND ( new_n638_, new_n623_, new_n621_, new_n605_ )
new_n640_ = OR ( new_n555_, new_n298_ )
new_n641_ = OR ( new_n559_, new_n162_ )
new_n642_ = NOT ( NET_68 )
new_n643_ = OR ( NET_1308, new_n642_ )
NET_596 = NAND ( new_n643_, new_n641_, new_n640_, new_n639_ )
new_n645_ = OR ( new_n624_, new_n605_ )
new_n646_ = NAND ( new_n623_, new_n621_ )
new_n647_ = OR ( new_n646_, new_n645_ )
new_n648_ = NAND ( new_n646_, new_n645_ )
new_n649_ = NAND ( new_n648_, new_n647_, new_n638_ )
new_n650_ = OR ( new_n555_, new_n302_ )
new_n651_ = OR ( new_n559_, new_n168_ )
new_n652_ = NOT ( NET_69 )
new_n653_ = OR ( NET_1308, new_n652_ )
NET_597 = NAND ( new_n653_, new_n651_, new_n650_, new_n649_ )
NET_78 = BUF ( NET_68 )
NET_79 = BUF ( NET_69 )
NET_80 = BUF ( NET_70 )
NET_81 = BUF ( NET_71 )
NET_82 = BUF ( NET_72 )
NET_83 = BUF ( NET_73 )
NET_84 = BUF ( NET_74 )
NET_85 = BUF ( NET_75 )

72
ITC99BENCH/b06.bench
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@ -1,72 +0,0 @@
# generated by verilog2bench.py https://gitea.yuhangq.com/YuhangQ/any2bench
INPUT(NET_1)
INPUT(NET_10)
INPUT(NET_11)
INPUT(NET_2)
INPUT(NET_3)
INPUT(NET_4)
INPUT(NET_5)
INPUT(NET_6)
INPUT(NET_7)
INPUT(NET_8)
INPUT(NET_9)
OUTPUT(NET_12)
OUTPUT(NET_13)
OUTPUT(NET_135)
OUTPUT(NET_136)
OUTPUT(NET_14)
OUTPUT(NET_15)
OUTPUT(NET_16)
OUTPUT(NET_17)
OUTPUT(NET_48)
OUTPUT(NET_49)
OUTPUT(NET_50)
OUTPUT(NET_51)
OUTPUT(NET_52)
OUTPUT(NET_57)
OUTPUT(NET_60)
new_n27_ = OR ( NET_5, NET_3 )
new_n28_ = NOT ( NET_4 )
new_n29_ = OR ( new_n28_, NET_1 )
new_n30_ = OR ( new_n29_, new_n27_ )
new_n31_ = NAND ( NET_5, NET_3 )
new_n32_ = NOR ( new_n31_, new_n28_ )
new_n33_ = OR ( new_n32_, NET_2 )
NET_135 = NAND ( new_n33_, new_n30_ )
new_n35_ = NOR ( new_n28_, NET_1 )
new_n36_ = NOT ( NET_1 )
new_n37_ = NOR ( NET_4, new_n36_ )
new_n38_ = NOR ( new_n37_, new_n35_ )
new_n39_ = NAND ( NET_4, NET_1 )
new_n40_ = NAND ( new_n39_, NET_5 )
NET_48 = AND ( new_n40_, new_n38_, NET_3 )
new_n42_ = NOT ( NET_5 )
new_n43_ = NAND ( new_n42_, new_n28_, NET_3 )
new_n44_ = NOT ( NET_3 )
new_n45_ = NAND ( NET_5, new_n28_, new_n44_, new_n36_ )
new_n46_ = NAND ( NET_3, NET_1 )
NET_49 = NAND ( new_n46_, new_n45_, new_n43_ )
new_n48_ = OR ( new_n43_, NET_1 )
new_n49_ = OR ( new_n27_, new_n28_ )
new_n50_ = NAND ( NET_5, new_n44_, NET_1 )
NET_50 = NAND ( new_n50_, new_n49_, new_n48_, new_n39_ )
new_n52_ = OR ( new_n37_, new_n42_ )
new_n53_ = OR ( new_n27_, NET_4 )
NET_51 = NAND ( new_n53_, new_n52_, new_n29_ )
new_n55_ = OR ( new_n39_, NET_3 )
new_n56_ = AND ( new_n31_, new_n27_ )
NET_52 = NAND ( new_n56_, new_n55_, new_n38_ )
new_n58_ = NAND ( new_n56_, new_n28_ )
new_n59_ = OR ( new_n39_, NET_5 )
NET_57 = NAND ( new_n59_, new_n58_, new_n46_ )
new_n61_ = XOR ( new_n31_, NET_4 )
new_n62_ = OR ( new_n61_, new_n56_ )
new_n63_ = NAND ( new_n62_, new_n58_ )
NET_60 = NAND ( new_n63_, NET_1 )
NET_12 = BUF ( NET_6 )
NET_13 = BUF ( NET_7 )
NET_136 = NAND ( new_n33_, new_n30_ )
NET_14 = BUF ( NET_8 )
NET_15 = BUF ( NET_9 )
NET_16 = BUF ( NET_10 )
NET_17 = BUF ( NET_11 )

477
ITC99BENCH/b07.bench
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@ -1,477 +0,0 @@
# generated by verilog2bench.py https://gitea.yuhangq.com/YuhangQ/any2bench
INPUT(NET_1)
INPUT(NET_10)
INPUT(NET_11)
INPUT(NET_12)
INPUT(NET_13)
INPUT(NET_14)
INPUT(NET_15)
INPUT(NET_16)
INPUT(NET_17)
INPUT(NET_18)
INPUT(NET_19)
INPUT(NET_2)
INPUT(NET_20)
INPUT(NET_21)
INPUT(NET_22)
INPUT(NET_23)
INPUT(NET_24)
INPUT(NET_25)
INPUT(NET_26)
INPUT(NET_27)
INPUT(NET_28)
INPUT(NET_29)
INPUT(NET_3)
INPUT(NET_30)
INPUT(NET_31)
INPUT(NET_32)
INPUT(NET_33)
INPUT(NET_34)
INPUT(NET_35)
INPUT(NET_36)
INPUT(NET_37)
INPUT(NET_38)
INPUT(NET_39)
INPUT(NET_4)
INPUT(NET_40)
INPUT(NET_41)
INPUT(NET_42)
INPUT(NET_43)
INPUT(NET_44)
INPUT(NET_45)
INPUT(NET_46)
INPUT(NET_47)
INPUT(NET_48)
INPUT(NET_49)
INPUT(NET_5)
INPUT(NET_50)
INPUT(NET_6)
INPUT(NET_7)
INPUT(NET_8)
INPUT(NET_9)
OUTPUT(NET_183)
OUTPUT(NET_184)
OUTPUT(NET_185)
OUTPUT(NET_186)
OUTPUT(NET_189)
OUTPUT(NET_206)
OUTPUT(NET_209)
OUTPUT(NET_240)
OUTPUT(NET_241)
OUTPUT(NET_242)
OUTPUT(NET_243)
OUTPUT(NET_244)
OUTPUT(NET_249)
OUTPUT(NET_263)
OUTPUT(NET_289)
OUTPUT(NET_290)
OUTPUT(NET_291)
OUTPUT(NET_292)
OUTPUT(NET_328)
OUTPUT(NET_329)
OUTPUT(NET_330)
OUTPUT(NET_331)
OUTPUT(NET_341)
OUTPUT(NET_342)
OUTPUT(NET_343)
OUTPUT(NET_344)
OUTPUT(NET_353)
OUTPUT(NET_354)
OUTPUT(NET_355)
OUTPUT(NET_356)
OUTPUT(NET_369)
OUTPUT(NET_370)
OUTPUT(NET_371)
OUTPUT(NET_372)
OUTPUT(NET_382)
OUTPUT(NET_383)
OUTPUT(NET_384)
OUTPUT(NET_385)
OUTPUT(NET_395)
OUTPUT(NET_396)
OUTPUT(NET_397)
OUTPUT(NET_398)
OUTPUT(NET_410)
OUTPUT(NET_411)
OUTPUT(NET_412)
OUTPUT(NET_413)
OUTPUT(NET_418)
OUTPUT(NET_419)
OUTPUT(NET_420)
OUTPUT(NET_51)
OUTPUT(NET_52)
OUTPUT(NET_53)
OUTPUT(NET_54)
OUTPUT(NET_55)
OUTPUT(NET_56)
OUTPUT(NET_57)
OUTPUT(NET_58)
new_n108_ = NOT ( NET_23 )
new_n109_ = NOT ( NET_24 )
new_n110_ = NAND ( NET_25, new_n109_, new_n108_ )
new_n111_ = OR ( new_n110_, NET_22 )
new_n112_ = NOT ( NET_25 )
new_n113_ = NAND ( new_n112_, NET_24, new_n108_, NET_22 )
new_n114_ = NAND ( new_n113_, new_n111_ )
new_n115_ = NOT ( NET_48 )
new_n116_ = OR ( NET_50, NET_49 )
new_n117_ = NOR ( new_n116_, new_n115_ )
new_n118_ = NAND ( new_n117_, new_n114_ )
new_n119_ = NOT ( NET_34 )
new_n120_ = OR ( new_n117_, new_n119_ )
NET_183 = NAND ( new_n120_, new_n118_ )
new_n122_ = NOT ( NET_36 )
new_n123_ = OR ( new_n117_, new_n122_ )
NET_184 = NAND ( new_n123_, new_n118_ )
new_n125_ = NOT ( NET_44 )
new_n126_ = OR ( new_n117_, new_n125_ )
NET_185 = NAND ( new_n126_, new_n118_ )
new_n128_ = NOT ( NET_47 )
new_n129_ = OR ( new_n117_, new_n128_ )
NET_186 = NAND ( new_n129_, new_n118_ )
new_n131_ = NOR ( new_n109_, NET_22 )
new_n132_ = OR ( new_n131_, new_n112_, new_n108_ )
new_n133_ = NAND ( new_n132_, new_n113_, new_n110_ )
new_n134_ = NAND ( new_n133_, new_n117_ )
new_n135_ = NOT ( NET_35 )
new_n136_ = OR ( new_n117_, new_n135_ )
NET_189 = NAND ( new_n136_, new_n134_ )
new_n138_ = NAND ( NET_49, NET_48 )
new_n139_ = NOT ( NET_18 )
new_n140_ = NOT ( NET_19 )
new_n141_ = NOR ( new_n112_, new_n109_ )
new_n142_ = AND ( new_n141_, NET_23 )
new_n143_ = NOT ( NET_20 )
new_n144_ = NOT ( NET_21 )
new_n145_ = AND ( NET_22, new_n144_, new_n143_ )
new_n146_ = NAND ( new_n145_, new_n142_, new_n140_, new_n139_ )
new_n147_ = NOR ( new_n146_, new_n138_ )
new_n148_ = NOR ( NET_49, NET_48 )
new_n149_ = NOR ( new_n148_, new_n147_ )
new_n150_ = OR ( new_n149_, NET_1 )
new_n151_ = NOR ( NET_50, NET_48 )
new_n152_ = NOT ( new_n151_ )
NET_206 = NAND ( new_n152_, new_n150_, new_n116_ )
new_n154_ = NOT ( new_n114_ )
new_n155_ = NAND ( new_n141_, new_n108_, NET_22 )
new_n156_ = NAND ( new_n155_, new_n154_ )
new_n157_ = NAND ( new_n156_, new_n117_ )
new_n158_ = NOT ( NET_46 )
new_n159_ = OR ( new_n117_, new_n158_ )
NET_209 = NAND ( new_n159_, new_n157_ )
new_n161_ = NOT ( NET_49 )
new_n162_ = NOT ( NET_1 )
new_n163_ = NOR ( new_n146_, new_n162_ )
new_n164_ = NOR ( new_n163_, new_n161_ )
new_n165_ = OR ( new_n164_, new_n115_ )
new_n166_ = NOT ( NET_50 )
new_n167_ = NOR ( new_n166_, new_n161_ )
new_n168_ = NOT ( new_n167_ )
NET_240 = NAND ( new_n168_, new_n165_ )
new_n170_ = NAND ( new_n146_, NET_49, NET_48 )
new_n171_ = NAND ( NET_50, new_n115_, NET_1 )
new_n172_ = NAND ( new_n171_, new_n170_, new_n168_ )
NET_241 = NOR ( new_n172_, new_n139_ )
NET_242 = NOR ( new_n172_, new_n140_ )
NET_243 = NOR ( new_n172_, new_n143_ )
NET_244 = NOR ( new_n172_, new_n144_ )
new_n177_ = NOT ( NET_22 )
new_n178_ = NAND ( new_n109_, new_n108_, new_n177_ )
new_n179_ = NAND ( new_n178_, new_n155_, new_n154_ )
new_n180_ = NAND ( new_n179_, new_n117_ )
new_n181_ = NOT ( NET_45 )
new_n182_ = OR ( new_n117_, new_n181_ )
NET_249 = NAND ( new_n182_, new_n180_ )
new_n184_ = NOR ( new_n146_, NET_1 )
new_n185_ = NOR ( new_n184_, NET_50 )
new_n186_ = NOR ( new_n185_, new_n151_ )
new_n187_ = OR ( new_n186_, new_n161_ )
new_n188_ = NAND ( NET_50, new_n161_, NET_1 )
new_n189_ = NAND ( NET_50, NET_48 )
NET_263 = NAND ( new_n189_, new_n188_, new_n187_ )
new_n191_ = NOT ( new_n148_ )
new_n192_ = NAND ( new_n172_, new_n191_ )
new_n193_ = NOT ( new_n192_ )
new_n194_ = NAND ( new_n193_, new_n142_, new_n177_ )
new_n195_ = OR ( new_n148_, new_n142_ )
new_n196_ = NAND ( new_n195_, new_n172_ )
new_n197_ = NAND ( new_n196_, NET_22 )
NET_289 = NAND ( new_n197_, new_n194_ )
new_n199_ = NAND ( new_n193_, new_n141_, new_n108_ )
new_n200_ = OR ( new_n148_, new_n141_ )
new_n201_ = NAND ( new_n200_, new_n172_ )
new_n202_ = NAND ( new_n201_, NET_23 )
NET_290 = NAND ( new_n202_, new_n199_ )
new_n204_ = NAND ( new_n193_, NET_25, new_n109_ )
new_n205_ = OR ( new_n148_, NET_25 )
new_n206_ = NAND ( new_n205_, new_n172_ )
new_n207_ = NAND ( new_n206_, NET_24 )
NET_291 = NAND ( new_n207_, new_n204_ )
new_n209_ = OR ( new_n192_, NET_25 )
new_n210_ = OR ( new_n172_, new_n112_ )
NET_292 = NAND ( new_n210_, new_n209_ )
new_n212_ = NOT ( NET_17 )
new_n213_ = NOR ( new_n191_, new_n166_ )
new_n214_ = NOR ( new_n213_, new_n147_ )
new_n215_ = NOR ( new_n214_, NET_1 )
new_n216_ = NOT ( NET_33 )
new_n217_ = NOR ( NET_31, NET_30 )
new_n218_ = NOR ( NET_29, NET_28, NET_27, NET_26 )
new_n219_ = NAND ( new_n218_, new_n217_, new_n216_, NET_32 )
new_n220_ = NAND ( new_n219_, new_n215_, NET_48 )
new_n221_ = OR ( new_n220_, new_n212_ )
new_n222_ = NOT ( NET_9 )
new_n223_ = OR ( new_n215_, new_n222_ )
new_n224_ = NAND ( new_n166_, new_n161_, NET_40 )
new_n225_ = OR ( new_n189_, new_n181_ )
new_n226_ = OR ( NET_48, new_n216_ )
new_n227_ = NAND ( new_n226_, new_n225_, new_n224_, new_n138_ )
new_n228_ = OR ( new_n138_, new_n212_ )
new_n229_ = NAND ( new_n166_, NET_49, NET_48 )
new_n230_ = NAND ( new_n229_, NET_33 )
new_n231_ = NAND ( new_n230_, new_n228_ )
new_n232_ = AND ( new_n231_, new_n227_ )
new_n233_ = NOR ( new_n231_, new_n227_ )
new_n234_ = OR ( new_n233_, new_n232_ )
new_n235_ = NAND ( new_n215_, NET_48 )
new_n236_ = NOR ( new_n219_, new_n235_ )
new_n237_ = NOT ( new_n236_ )
new_n238_ = OR ( new_n237_, new_n234_ )
NET_328 = NAND ( new_n238_, new_n223_, new_n221_ )
new_n240_ = NAND ( new_n148_, NET_50, NET_1 )
new_n241_ = OR ( new_n219_, new_n170_ )
new_n242_ = NAND ( new_n241_, new_n240_ )
new_n243_ = NAND ( new_n242_, NET_48 )
new_n244_ = OR ( new_n243_, new_n234_ )
new_n245_ = OR ( new_n242_, new_n212_ )
NET_329 = NAND ( new_n245_, new_n244_ )
new_n247_ = NOR ( NET_49, new_n115_ )
new_n248_ = NOT ( new_n247_ )
new_n249_ = OR ( new_n248_, new_n234_ )
new_n250_ = NOR ( new_n151_, new_n161_ )
new_n251_ = NOR ( new_n250_, new_n148_ )
new_n252_ = OR ( new_n251_, new_n216_ )
new_n253_ = AND ( new_n251_, new_n115_ )
new_n254_ = NAND ( new_n253_, new_n179_ )
NET_330 = NAND ( new_n254_, new_n252_, new_n249_ )
new_n256_ = NAND ( new_n168_, NET_40 )
new_n257_ = OR ( new_n234_, new_n168_ )
NET_331 = NAND ( new_n257_, new_n256_ )
new_n259_ = NOT ( NET_16 )
new_n260_ = OR ( new_n138_, new_n259_ )
new_n261_ = NAND ( new_n229_, NET_32 )
new_n262_ = NAND ( new_n261_, new_n260_ )
new_n263_ = NOR ( new_n262_, new_n232_ )
new_n264_ = NOT ( new_n232_ )
new_n265_ = NOT ( new_n262_ )
new_n266_ = NOR ( new_n265_, new_n264_ )
new_n267_ = NAND ( new_n166_, new_n161_, NET_39 )
new_n268_ = NOT ( NET_32 )
new_n269_ = OR ( NET_48, new_n268_ )
new_n270_ = OR ( new_n189_, new_n135_ )
new_n271_ = NAND ( new_n270_, new_n269_, new_n267_ )
new_n272_ = OR ( new_n271_, new_n266_, new_n263_ )
new_n273_ = NAND ( new_n271_, new_n264_ )
new_n274_ = NAND ( new_n273_, new_n265_ )
new_n275_ = NAND ( new_n271_, new_n232_ )
new_n276_ = NAND ( new_n275_, new_n262_ )
new_n277_ = NAND ( new_n276_, new_n274_ )
new_n278_ = NAND ( new_n277_, new_n272_ )
new_n279_ = NAND ( new_n278_, new_n236_ )
new_n280_ = NOT ( NET_8 )
new_n281_ = OR ( new_n215_, new_n280_ )
new_n282_ = OR ( new_n220_, new_n259_ )
NET_341 = NAND ( new_n282_, new_n281_, new_n279_ )
new_n284_ = NOT ( new_n243_ )
new_n285_ = NAND ( new_n278_, new_n284_ )
new_n286_ = OR ( new_n242_, new_n259_ )
NET_342 = NAND ( new_n286_, new_n285_ )
new_n288_ = NAND ( new_n278_, new_n247_ )
new_n289_ = NAND ( new_n253_, new_n114_ )
new_n290_ = NOR ( new_n131_, new_n108_ )
new_n291_ = OR ( new_n290_, new_n109_ )
new_n292_ = NAND ( new_n291_, new_n253_, NET_25 )
new_n293_ = OR ( new_n251_, new_n268_ )
NET_343 = NAND ( new_n293_, new_n292_, new_n289_, new_n288_ )
new_n295_ = NAND ( new_n168_, NET_39 )
new_n296_ = NAND ( new_n278_, new_n167_ )
NET_344 = NAND ( new_n296_, new_n295_ )
new_n298_ = NOT ( NET_15 )
new_n299_ = OR ( new_n138_, new_n298_ )
new_n300_ = NAND ( new_n229_, NET_31 )
new_n301_ = NAND ( new_n300_, new_n299_ )
new_n302_ = NAND ( new_n166_, new_n161_, NET_43 )
new_n303_ = NOT ( NET_31 )
new_n304_ = OR ( NET_48, new_n303_ )
new_n305_ = OR ( new_n189_, new_n158_ )
new_n306_ = NAND ( new_n305_, new_n304_, new_n302_ )
new_n307_ = NAND ( new_n306_, new_n301_ )
new_n308_ = OR ( new_n306_, new_n301_ )
new_n309_ = NAND ( new_n308_, new_n307_ )
new_n310_ = OR ( new_n271_, new_n232_ )
new_n311_ = NAND ( new_n310_, new_n262_ )
new_n312_ = NAND ( new_n311_, new_n275_ )
new_n313_ = XOR ( new_n312_, new_n309_ )
new_n314_ = OR ( new_n313_, new_n237_ )
new_n315_ = NOT ( NET_7 )
new_n316_ = OR ( new_n215_, new_n315_ )
new_n317_ = OR ( new_n220_, new_n298_ )
NET_353 = NAND ( new_n317_, new_n316_, new_n314_ )
new_n319_ = OR ( new_n313_, new_n243_ )
new_n320_ = OR ( new_n242_, new_n298_ )
NET_354 = NAND ( new_n320_, new_n319_ )
new_n322_ = OR ( new_n313_, new_n248_ )
new_n323_ = OR ( new_n251_, new_n303_ )
new_n324_ = NAND ( new_n253_, new_n156_ )
NET_355 = NAND ( new_n324_, new_n323_, new_n322_ )
new_n326_ = NAND ( new_n168_, NET_43 )
new_n327_ = OR ( new_n313_, new_n168_ )
NET_356 = NAND ( new_n327_, new_n326_ )
new_n329_ = NOT ( NET_14 )
new_n330_ = OR ( new_n138_, new_n329_ )
new_n331_ = NAND ( new_n229_, NET_30 )
new_n332_ = NAND ( new_n331_, new_n330_ )
new_n333_ = NAND ( new_n166_, new_n161_, NET_37 )
new_n334_ = NOT ( NET_30 )
new_n335_ = OR ( NET_48, new_n334_ )
new_n336_ = OR ( new_n189_, new_n119_ )
new_n337_ = NAND ( new_n336_, new_n335_, new_n333_ )
new_n338_ = NAND ( new_n337_, new_n332_ )
new_n339_ = OR ( new_n337_, new_n332_ )
new_n340_ = NAND ( new_n339_, new_n338_ )
new_n341_ = NAND ( new_n312_, new_n308_ )
new_n342_ = NAND ( new_n341_, new_n340_, new_n307_ )
new_n343_ = NAND ( new_n341_, new_n307_ )
new_n344_ = NAND ( new_n343_, new_n339_, new_n338_ )
new_n345_ = NAND ( new_n344_, new_n342_ )
new_n346_ = OR ( new_n345_, new_n237_ )
new_n347_ = NOT ( NET_6 )
new_n348_ = OR ( new_n215_, new_n347_ )
new_n349_ = OR ( new_n220_, new_n329_ )
NET_369 = NAND ( new_n349_, new_n348_, new_n346_ )
new_n351_ = OR ( new_n345_, new_n243_ )
new_n352_ = OR ( new_n242_, new_n329_ )
NET_370 = NAND ( new_n352_, new_n351_ )
new_n354_ = OR ( new_n345_, new_n248_ )
new_n355_ = OR ( new_n251_, new_n334_ )
NET_371 = NAND ( new_n355_, new_n354_, new_n289_ )
new_n357_ = NAND ( new_n168_, NET_37 )
new_n358_ = OR ( new_n345_, new_n168_ )
NET_372 = NAND ( new_n358_, new_n357_ )
new_n360_ = NAND ( new_n166_, new_n161_, NET_41 )
new_n361_ = NOT ( NET_29 )
new_n362_ = OR ( NET_48, new_n361_ )
new_n363_ = OR ( new_n189_, new_n125_ )
new_n364_ = NAND ( new_n363_, new_n362_, new_n360_ )
new_n365_ = NOT ( NET_13 )
new_n366_ = OR ( new_n138_, new_n365_ )
new_n367_ = NAND ( new_n229_, NET_29 )
new_n368_ = NAND ( new_n367_, new_n366_ )
new_n369_ = NAND ( new_n368_, new_n364_ )
new_n370_ = OR ( new_n368_, new_n364_ )
new_n371_ = NAND ( new_n370_, new_n369_ )
new_n372_ = NAND ( new_n343_, new_n339_ )
new_n373_ = NAND ( new_n372_, new_n338_ )
new_n374_ = XOR ( new_n373_, new_n371_ )
new_n375_ = OR ( new_n374_, new_n237_ )
new_n376_ = NOT ( NET_5 )
new_n377_ = OR ( new_n215_, new_n376_ )
new_n378_ = OR ( new_n220_, new_n365_ )
NET_382 = NAND ( new_n378_, new_n377_, new_n375_ )
new_n380_ = OR ( new_n374_, new_n243_ )
new_n381_ = OR ( new_n242_, new_n365_ )
NET_383 = NAND ( new_n381_, new_n380_ )
new_n383_ = OR ( new_n374_, new_n248_ )
new_n384_ = OR ( new_n251_, new_n361_ )
NET_384 = NAND ( new_n384_, new_n383_, new_n289_ )
new_n386_ = NAND ( new_n168_, NET_41 )
new_n387_ = OR ( new_n374_, new_n168_ )
NET_385 = NAND ( new_n387_, new_n386_ )
new_n389_ = NAND ( new_n166_, new_n161_, NET_38 )
new_n390_ = NOT ( NET_28 )
new_n391_ = OR ( NET_48, new_n390_ )
new_n392_ = OR ( new_n189_, new_n122_ )
new_n393_ = NAND ( new_n392_, new_n391_, new_n389_ )
new_n394_ = NOT ( NET_12 )
new_n395_ = OR ( new_n138_, new_n394_ )
new_n396_ = NAND ( new_n229_, NET_28 )
new_n397_ = NAND ( new_n396_, new_n395_ )
new_n398_ = OR ( new_n397_, new_n393_ )
new_n399_ = NAND ( new_n397_, new_n393_ )
new_n400_ = NAND ( new_n399_, new_n398_ )
new_n401_ = NAND ( new_n369_, new_n372_, new_n338_ )
new_n402_ = NAND ( new_n401_, new_n370_ )
new_n403_ = XNOR ( new_n402_, new_n400_ )
new_n404_ = OR ( new_n403_, new_n237_ )
new_n405_ = NOT ( NET_4 )
new_n406_ = OR ( new_n215_, new_n405_ )
new_n407_ = OR ( new_n220_, new_n394_ )
NET_395 = NAND ( new_n407_, new_n406_, new_n404_ )
new_n409_ = OR ( new_n403_, new_n243_ )
new_n410_ = OR ( new_n242_, new_n394_ )
NET_396 = NAND ( new_n410_, new_n409_ )
new_n412_ = OR ( new_n403_, new_n248_ )
new_n413_ = OR ( new_n251_, new_n390_ )
NET_397 = NAND ( new_n413_, new_n412_, new_n289_ )
new_n415_ = NAND ( new_n168_, NET_38 )
new_n416_ = OR ( new_n403_, new_n168_ )
NET_398 = NAND ( new_n416_, new_n415_ )
new_n418_ = NAND ( new_n166_, new_n161_, NET_42 )
new_n419_ = NOT ( NET_27 )
new_n420_ = OR ( NET_48, new_n419_ )
new_n421_ = OR ( new_n189_, new_n128_ )
new_n422_ = NAND ( new_n421_, new_n420_, new_n418_ )
new_n423_ = NOT ( NET_11 )
new_n424_ = OR ( new_n138_, new_n423_ )
new_n425_ = NAND ( new_n229_, NET_27 )
new_n426_ = NAND ( new_n425_, new_n424_ )
new_n427_ = NAND ( new_n426_, new_n422_ )
new_n428_ = NOR ( new_n426_, new_n422_ )
new_n429_ = NOT ( new_n428_ )
new_n430_ = NAND ( new_n429_, new_n427_ )
new_n431_ = NAND ( new_n402_, new_n399_ )
new_n432_ = NAND ( new_n431_, new_n398_ )
new_n433_ = XNOR ( new_n432_, new_n430_ )
new_n434_ = OR ( new_n433_, new_n237_ )
new_n435_ = NOT ( NET_3 )
new_n436_ = OR ( new_n215_, new_n435_ )
new_n437_ = OR ( new_n220_, new_n423_ )
NET_410 = NAND ( new_n437_, new_n436_, new_n434_ )
new_n439_ = OR ( new_n433_, new_n243_ )
new_n440_ = OR ( new_n242_, new_n423_ )
NET_411 = NAND ( new_n440_, new_n439_ )
new_n442_ = OR ( new_n433_, new_n248_ )
new_n443_ = OR ( new_n251_, new_n419_ )
NET_412 = NAND ( new_n443_, new_n442_, new_n289_ )
new_n445_ = NAND ( new_n168_, NET_42 )
new_n446_ = OR ( new_n433_, new_n168_ )
NET_413 = NAND ( new_n446_, new_n445_ )
new_n448_ = NAND ( new_n432_, new_n427_ )
new_n449_ = AND ( new_n448_, new_n429_ )
new_n450_ = NOT ( NET_10 )
new_n451_ = OR ( new_n138_, new_n450_ )
new_n452_ = OR ( new_n451_, new_n449_ )
new_n453_ = OR ( new_n432_, new_n428_ )
new_n454_ = NAND ( new_n453_, new_n427_ )
new_n455_ = NAND ( new_n454_, new_n451_ )
new_n456_ = NAND ( new_n455_, new_n452_ )
new_n457_ = NAND ( new_n456_, new_n236_ )
new_n458_ = NOT ( NET_2 )
new_n459_ = OR ( new_n215_, new_n458_ )
new_n460_ = OR ( new_n220_, new_n450_ )
NET_418 = NAND ( new_n460_, new_n459_, new_n457_ )
new_n462_ = NAND ( new_n456_, new_n284_ )
new_n463_ = OR ( new_n242_, new_n450_ )
NET_419 = NAND ( new_n463_, new_n462_ )
new_n465_ = NAND ( new_n456_, new_n247_ )
new_n466_ = NOT ( NET_26 )
new_n467_ = OR ( new_n251_, new_n466_ )
NET_420 = NAND ( new_n467_, new_n465_, new_n289_ )
NET_51 = BUF ( NET_2 )
NET_52 = BUF ( NET_3 )
NET_53 = BUF ( NET_4 )
NET_54 = BUF ( NET_5 )
NET_55 = BUF ( NET_6 )
NET_56 = BUF ( NET_7 )
NET_57 = BUF ( NET_8 )
NET_58 = BUF ( NET_9 )

193
ITC99BENCH/b08.bench
View File

@ -1,193 +0,0 @@
# generated by verilog2bench.py https://gitea.yuhangq.com/YuhangQ/any2bench
INPUT(NET_1)
INPUT(NET_10)
INPUT(NET_11)
INPUT(NET_12)
INPUT(NET_13)
INPUT(NET_14)
INPUT(NET_15)
INPUT(NET_16)
INPUT(NET_17)
INPUT(NET_18)
INPUT(NET_19)
INPUT(NET_2)
INPUT(NET_20)
INPUT(NET_21)
INPUT(NET_22)
INPUT(NET_23)
INPUT(NET_24)
INPUT(NET_25)
INPUT(NET_26)
INPUT(NET_27)
INPUT(NET_28)
INPUT(NET_29)
INPUT(NET_3)
INPUT(NET_30)
INPUT(NET_4)
INPUT(NET_5)
INPUT(NET_6)
INPUT(NET_7)
INPUT(NET_8)
INPUT(NET_9)
OUTPUT(NET_103)
OUTPUT(NET_119)
OUTPUT(NET_120)
OUTPUT(NET_123)
OUTPUT(NET_135)
OUTPUT(NET_136)
OUTPUT(NET_137)
OUTPUT(NET_138)
OUTPUT(NET_144)
OUTPUT(NET_162)
OUTPUT(NET_163)
OUTPUT(NET_166)
OUTPUT(NET_167)
OUTPUT(NET_31)
OUTPUT(NET_32)
OUTPUT(NET_33)
OUTPUT(NET_34)
OUTPUT(NET_91)
OUTPUT(NET_92)
OUTPUT(NET_93)
OUTPUT(NET_94)
OUTPUT(NET_95)
OUTPUT(NET_96)
OUTPUT(NET_97)
OUTPUT(NET_98)
new_n56_ = NOT ( NET_11 )
new_n57_ = NOT ( NET_12 )
new_n58_ = NAND ( NET_14, NET_13 )
new_n59_ = OR ( new_n58_, new_n57_ )
new_n60_ = NOR ( new_n59_, NET_1 )
new_n61_ = NOR ( new_n60_, new_n56_ )
new_n62_ = NOT ( NET_10 )
new_n63_ = NOR ( NET_11, new_n62_ )
new_n64_ = NOR ( new_n56_, NET_10 )
NET_103 = OR ( new_n64_, new_n63_, new_n61_ )
new_n66_ = OR ( new_n59_, new_n62_ )
new_n67_ = NAND ( new_n66_, NET_11 )
new_n68_ = AND ( new_n67_, NET_1 )
NET_119 = OR ( new_n68_, new_n63_ )
new_n70_ = NOT ( NET_13 )
new_n71_ = OR ( NET_14, new_n70_ )
new_n72_ = OR ( new_n71_, new_n62_ )
new_n73_ = NOR ( new_n56_, new_n62_ )
new_n74_ = NAND ( new_n73_, NET_14 )
new_n75_ = NAND ( new_n74_, new_n70_ )
new_n76_ = OR ( new_n67_, new_n70_ )
new_n77_ = NAND ( new_n76_, new_n75_ )
NET_120 = NAND ( new_n77_, new_n72_ )
new_n79_ = NOT ( NET_14 )
new_n80_ = NAND ( new_n73_, new_n79_ )
new_n81_ = NAND ( new_n67_, NET_14 )
NET_123 = NAND ( new_n81_, new_n80_ )
new_n83_ = NAND ( new_n73_, new_n60_ )
new_n84_ = NAND ( new_n83_, NET_27 )
new_n85_ = NOT ( NET_23 )
new_n86_ = OR ( new_n83_, new_n85_ )
NET_135 = NAND ( new_n86_, new_n84_ )
new_n88_ = NAND ( new_n83_, NET_28 )
new_n89_ = NOT ( NET_24 )
new_n90_ = OR ( new_n83_, new_n89_ )
NET_136 = NAND ( new_n90_, new_n88_ )
new_n92_ = NAND ( new_n83_, NET_29 )
new_n93_ = NOT ( NET_25 )
new_n94_ = OR ( new_n83_, new_n93_ )
NET_137 = NAND ( new_n94_, new_n92_ )
new_n96_ = NAND ( new_n83_, NET_30 )
new_n97_ = NOT ( NET_26 )
new_n98_ = OR ( new_n83_, new_n97_ )
NET_138 = NAND ( new_n98_, new_n96_ )
new_n100_ = OR ( new_n64_, new_n57_ )
new_n101_ = NAND ( new_n73_, NET_14, NET_13, new_n57_ )
NET_144 = NAND ( new_n101_, new_n100_ )
new_n103_ = NAND ( new_n79_, NET_13, new_n57_ )
new_n104_ = NAND ( new_n79_, new_n70_, NET_12 )
new_n105_ = AND ( new_n104_, new_n103_, new_n59_ )
new_n106_ = NOT ( NET_21 )
new_n107_ = NAND ( new_n106_, new_n79_, NET_13, NET_12 )
new_n108_ = NAND ( NET_14, new_n70_, new_n57_ )
new_n109_ = NAND ( new_n79_, new_n70_, new_n57_ )
new_n110_ = OR ( new_n58_, NET_12 )
new_n111_ = OR ( NET_13, new_n57_ )
new_n112_ = AND ( new_n111_, new_n110_ )
new_n113_ = AND ( new_n112_, new_n109_ )
new_n114_ = NAND ( new_n113_, new_n108_, new_n59_, NET_22 )
new_n115_ = NOT ( NET_15 )
new_n116_ = OR ( new_n111_, new_n79_ )
new_n117_ = AND ( new_n109_, new_n108_, new_n105_ )
new_n118_ = NAND ( new_n117_, new_n116_, new_n115_ )
new_n119_ = NOT ( NET_20 )
new_n120_ = NAND ( new_n79_, NET_13, NET_12 )
new_n121_ = NAND ( new_n120_, new_n117_, new_n119_ )
new_n122_ = NAND ( new_n121_, new_n118_, new_n114_, new_n107_ )
new_n123_ = NAND ( new_n120_, new_n113_, NET_16 )
new_n124_ = NOT ( NET_17 )
new_n125_ = AND ( new_n120_, new_n105_, new_n110_ )
new_n126_ = NAND ( new_n125_, new_n116_, new_n124_ )
new_n127_ = NOT ( NET_16 )
new_n128_ = NAND ( new_n125_, new_n108_, new_n127_ )
new_n129_ = NAND ( new_n128_, new_n126_, new_n123_ )
new_n130_ = NAND ( new_n113_, new_n59_, NET_20 )
new_n131_ = NAND ( new_n120_, new_n103_ )
new_n132_ = NOT ( NET_22 )
new_n133_ = NAND ( new_n109_, new_n110_, new_n59_, new_n132_ )
new_n134_ = OR ( new_n133_, new_n131_ )
new_n135_ = NAND ( new_n112_, new_n71_, NET_15 )
new_n136_ = NOT ( NET_19 )
new_n137_ = NAND ( NET_14, NET_12 )
new_n138_ = OR ( new_n70_, NET_12 )
new_n139_ = NAND ( new_n138_, new_n137_, new_n136_ )
new_n140_ = AND ( new_n139_, new_n135_, new_n134_, new_n63_ )
new_n141_ = NAND ( new_n113_, new_n108_, NET_18 )
new_n142_ = NAND ( new_n120_, new_n113_, new_n59_, NET_21 )
new_n143_ = NAND ( new_n142_, new_n141_, new_n140_, new_n130_ )
new_n144_ = NAND ( NET_17, new_n79_, NET_13, NET_12 )
new_n145_ = NOT ( NET_18 )
new_n146_ = NAND ( new_n145_, NET_14, NET_13, new_n57_ )
new_n147_ = NAND ( new_n146_, new_n144_ )
new_n148_ = NOR ( new_n147_, new_n143_, new_n129_, new_n122_ )
new_n149_ = OR ( new_n148_, new_n64_ )
new_n150_ = NAND ( new_n149_, NET_10 )
new_n151_ = OR ( new_n150_, new_n105_ )
new_n152_ = AND ( new_n149_, new_n62_ )
new_n153_ = OR ( new_n152_, new_n89_ )
NET_162 = NAND ( new_n153_, new_n151_ )
new_n155_ = NAND ( new_n149_, new_n131_, NET_10 )
new_n156_ = OR ( new_n152_, new_n97_ )
NET_163 = NAND ( new_n156_, new_n155_ )
new_n158_ = OR ( new_n150_, NET_14 )
new_n159_ = OR ( new_n152_, new_n85_ )
new_n160_ = OR ( new_n150_, new_n112_ )
NET_166 = NAND ( new_n160_, new_n159_, new_n158_ )
new_n162_ = OR ( new_n150_, NET_12 )
new_n163_ = OR ( new_n152_, new_n93_ )
NET_167 = NAND ( new_n163_, new_n162_, new_n158_ )
new_n165_ = NAND ( new_n64_, NET_2 )
new_n166_ = OR ( new_n64_, new_n115_ )
NET_91 = NAND ( new_n166_, new_n165_ )
new_n168_ = NAND ( new_n64_, NET_3 )
new_n169_ = OR ( new_n64_, new_n127_ )
NET_92 = NAND ( new_n169_, new_n168_ )
new_n171_ = NAND ( new_n64_, NET_4 )
new_n172_ = OR ( new_n64_, new_n124_ )
NET_93 = NAND ( new_n172_, new_n171_ )
new_n174_ = NAND ( new_n64_, NET_5 )
new_n175_ = OR ( new_n64_, new_n145_ )
NET_94 = NAND ( new_n175_, new_n174_ )
new_n177_ = NAND ( new_n64_, NET_6 )
new_n178_ = OR ( new_n64_, new_n136_ )
NET_95 = NAND ( new_n178_, new_n177_ )
new_n180_ = NAND ( new_n64_, NET_7 )
new_n181_ = OR ( new_n64_, new_n119_ )
NET_96 = NAND ( new_n181_, new_n180_ )
new_n183_ = NAND ( new_n64_, NET_8 )
new_n184_ = OR ( new_n64_, new_n106_ )
NET_97 = NAND ( new_n184_, new_n183_ )
new_n186_ = NAND ( new_n64_, NET_9 )
new_n187_ = OR ( new_n64_, new_n132_ )
NET_98 = NAND ( new_n187_, new_n186_ )
NET_31 = BUF ( NET_27 )
NET_32 = BUF ( NET_28 )
NET_33 = BUF ( NET_29 )
NET_34 = BUF ( NET_30 )

172
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@ -1,172 +0,0 @@
# generated by verilog2bench.py https://gitea.yuhangq.com/YuhangQ/any2bench
INPUT(NET_1)
INPUT(NET_10)
INPUT(NET_11)
INPUT(NET_12)
INPUT(NET_13)
INPUT(NET_14)
INPUT(NET_15)
INPUT(NET_16)
INPUT(NET_17)
INPUT(NET_18)
INPUT(NET_19)
INPUT(NET_2)
INPUT(NET_20)
INPUT(NET_21)
INPUT(NET_22)
INPUT(NET_23)
INPUT(NET_24)
INPUT(NET_25)
INPUT(NET_26)
INPUT(NET_27)
INPUT(NET_28)
INPUT(NET_29)
INPUT(NET_3)
INPUT(NET_4)
INPUT(NET_5)
INPUT(NET_6)
INPUT(NET_7)
INPUT(NET_8)
INPUT(NET_9)
OUTPUT(NET_102)
OUTPUT(NET_103)
OUTPUT(NET_104)
OUTPUT(NET_105)
OUTPUT(NET_106)
OUTPUT(NET_107)
OUTPUT(NET_108)
OUTPUT(NET_109)
OUTPUT(NET_110)
OUTPUT(NET_111)
OUTPUT(NET_116)
OUTPUT(NET_117)
OUTPUT(NET_118)
OUTPUT(NET_119)
OUTPUT(NET_120)
OUTPUT(NET_121)
OUTPUT(NET_122)
OUTPUT(NET_123)
OUTPUT(NET_136)
OUTPUT(NET_152)
OUTPUT(NET_153)
OUTPUT(NET_154)
OUTPUT(NET_155)
OUTPUT(NET_156)
OUTPUT(NET_157)
OUTPUT(NET_158)
OUTPUT(NET_159)
OUTPUT(NET_30)
OUTPUT(NET_45)
new_n59_ = XNOR ( NET_22, NET_11 )
new_n60_ = XNOR ( NET_28, NET_17 )
new_n61_ = XNOR ( NET_21, NET_10 )
new_n62_ = XNOR ( NET_27, NET_16 )
new_n63_ = NAND ( new_n62_, new_n61_, new_n60_, new_n59_ )
new_n64_ = XNOR ( NET_26, NET_15 )
new_n65_ = XNOR ( NET_24, NET_13 )
new_n66_ = XNOR ( NET_25, NET_14 )
new_n67_ = XNOR ( NET_23, NET_12 )
new_n68_ = NAND ( new_n67_, new_n66_, new_n65_, new_n64_ )
new_n69_ = NOR ( new_n68_, new_n63_ )
new_n70_ = NAND ( new_n69_, NET_20, NET_19 )
new_n71_ = NOT ( NET_19 )
new_n72_ = NOR ( NET_29, new_n71_ )
new_n73_ = OR ( new_n72_, NET_20 )
new_n74_ = NOT ( NET_20 )
new_n75_ = OR ( NET_29, new_n74_ )
NET_102 = NAND ( new_n75_, new_n73_, new_n70_ )
new_n77_ = NOT ( NET_21 )
new_n78_ = NAND ( NET_29, NET_20 )
new_n79_ = OR ( new_n78_, new_n77_ )
new_n80_ = OR ( NET_20, NET_19 )
new_n81_ = NAND ( new_n80_, new_n78_, NET_10 )
NET_103 = NAND ( new_n81_, new_n79_ )
new_n83_ = NOT ( NET_22 )
new_n84_ = OR ( new_n78_, new_n83_ )
new_n85_ = NAND ( new_n80_, new_n78_, NET_11 )
NET_104 = NAND ( new_n85_, new_n84_ )
new_n87_ = NOT ( NET_23 )
new_n88_ = OR ( new_n78_, new_n87_ )
new_n89_ = NAND ( new_n80_, new_n78_, NET_12 )
NET_105 = NAND ( new_n89_, new_n88_ )
new_n91_ = NOT ( NET_24 )
new_n92_ = OR ( new_n78_, new_n91_ )
new_n93_ = NAND ( new_n80_, new_n78_, NET_13 )
NET_106 = NAND ( new_n93_, new_n92_ )
new_n95_ = NOT ( NET_25 )
new_n96_ = OR ( new_n78_, new_n95_ )
new_n97_ = NAND ( new_n80_, new_n78_, NET_14 )
NET_107 = NAND ( new_n97_, new_n96_ )
new_n99_ = NOT ( NET_26 )
new_n100_ = OR ( new_n78_, new_n99_ )
new_n101_ = NAND ( new_n80_, new_n78_, NET_15 )
NET_108 = NAND ( new_n101_, new_n100_ )
new_n103_ = NOT ( NET_27 )
new_n104_ = OR ( new_n78_, new_n103_ )
new_n105_ = NAND ( new_n80_, new_n78_, NET_16 )
NET_109 = NAND ( new_n105_, new_n104_ )
new_n107_ = NOT ( NET_28 )
new_n108_ = OR ( new_n78_, new_n107_ )
new_n109_ = NAND ( new_n80_, new_n78_, NET_17 )
NET_110 = NAND ( new_n109_, new_n108_ )
new_n111_ = OR ( new_n78_, new_n69_ )
new_n112_ = NOR ( NET_29, NET_18 )
new_n113_ = OR ( new_n74_, NET_19 )
new_n114_ = OR ( new_n113_, new_n112_ )
new_n115_ = NOT ( NET_29 )
new_n116_ = NAND ( NET_9, new_n115_, new_n74_, NET_19 )
NET_111 = NAND ( new_n116_, new_n114_, new_n111_ )
new_n118_ = NAND ( new_n80_, new_n78_ )
NET_116 = NOR ( new_n118_, new_n107_ )
NET_117 = NOR ( new_n118_, new_n103_ )
NET_118 = NOR ( new_n118_, new_n99_ )
NET_119 = NOR ( new_n118_, new_n95_ )
NET_120 = NOR ( new_n118_, new_n91_ )
NET_121 = NOR ( new_n118_, new_n87_ )
NET_122 = NOR ( new_n118_, new_n83_ )
NET_123 = NOR ( new_n118_, new_n77_ )
new_n127_ = OR ( NET_20, new_n71_ )
new_n128_ = NAND ( NET_20, NET_19 )
new_n129_ = OR ( new_n128_, NET_29 )
new_n130_ = NAND ( new_n129_, new_n127_, new_n113_ )
new_n131_ = NAND ( new_n130_, NET_1 )
new_n132_ = OR ( new_n69_, new_n128_ )
new_n133_ = NAND ( new_n132_, new_n113_ )
new_n134_ = NAND ( new_n133_, NET_29 )
NET_136 = NAND ( new_n134_, new_n131_ )
new_n136_ = OR ( NET_29, NET_20 )
new_n137_ = OR ( new_n115_, NET_19 )
new_n138_ = NAND ( new_n137_, new_n136_, new_n111_ )
new_n139_ = NAND ( new_n138_, NET_21, NET_20 )
new_n140_ = NAND ( new_n137_, new_n136_, new_n111_, NET_2 )
NET_152 = NAND ( new_n140_, new_n139_ )
new_n142_ = NAND ( new_n138_, NET_22, NET_20 )
new_n143_ = NAND ( new_n137_, new_n136_, new_n111_, NET_3 )
new_n144_ = NAND ( new_n115_, new_n74_, NET_2, NET_19 )
NET_153 = NAND ( new_n144_, new_n143_, new_n142_ )
new_n146_ = NAND ( new_n138_, NET_23, NET_20 )
new_n147_ = NAND ( new_n137_, new_n136_, new_n111_, NET_4 )
new_n148_ = NAND ( NET_3, new_n115_, new_n74_, NET_19 )
NET_154 = NAND ( new_n148_, new_n147_, new_n146_ )
new_n150_ = NAND ( new_n138_, NET_24, NET_20 )
new_n151_ = NAND ( new_n137_, new_n136_, new_n111_, NET_5 )
new_n152_ = NAND ( NET_4, new_n115_, new_n74_, NET_19 )
NET_155 = NAND ( new_n152_, new_n151_, new_n150_ )
new_n154_ = NAND ( new_n138_, NET_25, NET_20 )
new_n155_ = NAND ( new_n137_, new_n136_, new_n111_, NET_6 )
new_n156_ = NAND ( NET_5, new_n115_, new_n74_, NET_19 )
NET_156 = NAND ( new_n156_, new_n155_, new_n154_ )
new_n158_ = NAND ( new_n138_, NET_26, NET_20 )
new_n159_ = NAND ( new_n137_, new_n136_, new_n111_, NET_7 )
new_n160_ = NAND ( NET_6, new_n115_, new_n74_, NET_19 )
NET_157 = NAND ( new_n160_, new_n159_, new_n158_ )
new_n162_ = NAND ( new_n138_, NET_27, NET_20 )
new_n163_ = NAND ( new_n137_, new_n136_, new_n111_, NET_8 )
new_n164_ = NAND ( NET_7, new_n115_, new_n74_, NET_19 )
NET_158 = NAND ( new_n164_, new_n163_, new_n162_ )
new_n166_ = NAND ( new_n138_, NET_28, NET_20 )
new_n167_ = NAND ( new_n137_, new_n136_, new_n111_, NET_9 )
new_n168_ = NAND ( NET_8, new_n115_, new_n74_, NET_19 )
NET_159 = NAND ( new_n168_, new_n167_, new_n166_ )
NET_45 = NAND ( new_n78_, new_n71_ )
NET_30 = BUF ( NET_18 )

206
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View File

@ -1,206 +0,0 @@
# generated by verilog2bench.py https://gitea.yuhangq.com/YuhangQ/any2bench
INPUT(NET_1)
INPUT(NET_10)
INPUT(NET_11)
INPUT(NET_12)
INPUT(NET_13)
INPUT(NET_14)
INPUT(NET_15)
INPUT(NET_16)
INPUT(NET_17)
INPUT(NET_18)
INPUT(NET_19)
INPUT(NET_2)
INPUT(NET_20)
INPUT(NET_21)
INPUT(NET_22)
INPUT(NET_23)
INPUT(NET_24)
INPUT(NET_25)
INPUT(NET_26)
INPUT(NET_27)
INPUT(NET_28)
INPUT(NET_3)
INPUT(NET_4)
INPUT(NET_5)
INPUT(NET_6)
INPUT(NET_7)
INPUT(NET_8)
INPUT(NET_9)
OUTPUT(NET_121)
OUTPUT(NET_123)
OUTPUT(NET_124)
OUTPUT(NET_125)
OUTPUT(NET_126)
OUTPUT(NET_153)
OUTPUT(NET_154)
OUTPUT(NET_156)
OUTPUT(NET_157)
OUTPUT(NET_176)
OUTPUT(NET_177)
OUTPUT(NET_178)
OUTPUT(NET_179)
OUTPUT(NET_180)
OUTPUT(NET_187)
OUTPUT(NET_188)
OUTPUT(NET_189)
OUTPUT(NET_29)
OUTPUT(NET_30)
OUTPUT(NET_31)
OUTPUT(NET_32)
OUTPUT(NET_33)
OUTPUT(NET_34)
new_n52_ = NOT ( NET_27 )
new_n53_ = OR ( NET_25, NET_18 )
new_n54_ = NOR ( new_n53_, NET_17 )
new_n55_ = NAND ( new_n54_, new_n52_ )
new_n56_ = OR ( new_n55_, NET_5 )
new_n57_ = NAND ( new_n56_, NET_16 )
new_n58_ = NAND ( NET_25, NET_17 )
NET_121 = NAND ( new_n58_, new_n57_ )
new_n60_ = NOT ( NET_17 )
new_n61_ = NAND ( NET_7, new_n52_, NET_18, new_n60_ )
new_n62_ = NAND ( new_n61_, NET_12 )
new_n63_ = NOT ( NET_21 )
new_n64_ = OR ( new_n61_, new_n63_ )
NET_123 = NAND ( new_n64_, new_n62_ )
new_n66_ = NAND ( new_n61_, NET_13 )
new_n67_ = NOT ( NET_24 )
new_n68_ = OR ( new_n61_, new_n67_ )
NET_124 = NAND ( new_n68_, new_n66_ )
new_n70_ = NAND ( new_n61_, NET_14 )
new_n71_ = NOT ( NET_19 )
new_n72_ = OR ( new_n61_, new_n71_ )
NET_125 = NAND ( new_n72_, new_n70_ )
new_n74_ = NAND ( new_n61_, NET_15 )
new_n75_ = NOT ( NET_28 )
new_n76_ = OR ( new_n61_, new_n75_ )
NET_126 = NAND ( new_n76_, new_n74_ )
new_n78_ = NOR ( new_n52_, NET_18 )
new_n79_ = NOT ( NET_18 )
new_n80_ = NOR ( NET_27, new_n79_ )
new_n81_ = NOR ( new_n80_, new_n78_ )
new_n82_ = OR ( NET_6, new_n52_ )
new_n83_ = NOT ( NET_25 )
new_n84_ = OR ( NET_27, new_n83_ )
new_n85_ = NAND ( new_n84_, new_n82_, new_n81_, new_n60_ )
new_n86_ = NAND ( new_n85_, NET_20 )
new_n87_ = NOT ( NET_6 )
new_n88_ = NOR ( NET_27, new_n60_ )
new_n89_ = NAND ( new_n88_, new_n87_, NET_18 )
NET_153 = NAND ( new_n89_, new_n86_ )
new_n91_ = OR ( new_n52_, NET_17 )
new_n92_ = OR ( NET_25, NET_17 )
new_n93_ = NAND ( new_n92_, NET_7 )
new_n94_ = NAND ( new_n88_, NET_25 )
new_n95_ = NAND ( new_n94_, new_n93_, new_n91_, new_n81_ )
new_n96_ = NAND ( new_n95_, NET_23 )
new_n97_ = NAND ( new_n88_, NET_7, new_n83_, new_n79_ )
new_n98_ = NAND ( new_n80_, NET_25, new_n60_ )
NET_154 = NAND ( new_n98_, new_n97_, new_n96_, new_n61_ )
new_n100_ = NOT ( NET_4 )
new_n101_ = OR ( new_n53_, NET_17 )
new_n102_ = NOR ( new_n101_, new_n100_ )
new_n103_ = NAND ( new_n102_, NET_3, NET_27, NET_1 )
new_n104_ = NAND ( new_n102_, NET_3, NET_27 )
new_n105_ = NAND ( new_n104_, NET_22 )
NET_156 = NAND ( new_n105_, new_n103_ )
new_n107_ = NAND ( new_n102_, NET_3, NET_27, NET_2 )
new_n108_ = NAND ( new_n104_, NET_26 )
NET_157 = NAND ( new_n108_, new_n107_ )
new_n110_ = NAND ( NET_27, NET_18, new_n60_ )
new_n111_ = NOT ( new_n88_ )
new_n112_ = AND ( NET_9, NET_8, NET_25 )
new_n113_ = NAND ( new_n112_, NET_11, NET_10 )
new_n114_ = NOT ( NET_7 )
new_n115_ = NAND ( new_n114_, NET_27, NET_18 )
new_n116_ = OR ( new_n53_, new_n100_ )
new_n117_ = NAND ( new_n116_, new_n115_, new_n113_ )
new_n118_ = NAND ( new_n117_, NET_17 )
new_n119_ = OR ( new_n110_, new_n87_ )
new_n120_ = AND ( new_n119_, new_n55_ )
new_n121_ = OR ( new_n100_, NET_25 )
new_n122_ = NAND ( new_n121_, new_n78_, new_n58_ )
new_n123_ = NAND ( new_n114_, new_n52_, NET_25, new_n60_ )
new_n124_ = AND ( new_n123_, new_n89_, new_n61_ )
new_n125_ = NAND ( new_n124_, new_n122_, new_n120_, new_n118_ )
new_n126_ = NAND ( new_n75_, NET_24, new_n63_, NET_19 )
new_n127_ = NAND ( new_n126_, new_n60_ )
new_n128_ = NAND ( new_n127_, new_n125_, new_n111_ )
new_n129_ = NAND ( new_n128_, NET_18 )
new_n130_ = NAND ( new_n92_, new_n58_, NET_27 )
NET_176 = NAND ( new_n130_, new_n129_, new_n110_ )
new_n132_ = NOR ( new_n126_, new_n79_, NET_17 )
new_n133_ = NOR ( new_n101_, NET_5 )
new_n134_ = OR ( new_n133_, new_n132_ )
new_n135_ = NAND ( new_n134_, new_n125_, new_n52_ )
new_n136_ = NAND ( new_n125_, new_n60_ )
new_n137_ = NAND ( new_n136_, NET_25 )
NET_177 = NAND ( new_n137_, new_n135_ )
new_n139_ = OR ( new_n125_, new_n52_ )
new_n140_ = OR ( new_n52_, NET_25 )
new_n141_ = NAND ( new_n140_, new_n125_, NET_17 )
new_n142_ = OR ( new_n140_, NET_17 )
NET_178 = NAND ( new_n142_, new_n141_, new_n139_, new_n110_ )
new_n144_ = OR ( new_n126_, NET_25 )
new_n145_ = NAND ( new_n144_, new_n52_, new_n60_ )
new_n146_ = NAND ( new_n145_, new_n110_, new_n101_ )
new_n147_ = NAND ( new_n146_, new_n125_ )
new_n148_ = OR ( new_n125_, new_n60_ )
NET_179 = NAND ( new_n148_, new_n147_ )
new_n150_ = NOT ( NET_3 )
new_n151_ = NOR ( new_n101_, new_n150_ )
new_n152_ = NOR ( new_n83_, NET_16 )
new_n153_ = NOR ( new_n152_, new_n151_ )
new_n154_ = OR ( new_n153_, new_n52_ )
new_n155_ = OR ( new_n110_, NET_25 )
new_n156_ = NAND ( new_n88_, NET_25, new_n79_ )
new_n157_ = NAND ( new_n156_, new_n155_ )
new_n158_ = NAND ( new_n157_, NET_11 )
new_n159_ = NAND ( new_n158_, new_n154_ )
new_n160_ = NAND ( new_n92_, new_n78_, new_n58_ )
new_n161_ = NAND ( new_n160_, new_n156_, new_n120_, new_n116_ )
new_n162_ = NAND ( new_n161_, new_n159_ )
new_n163_ = OR ( new_n161_, new_n75_ )
NET_180 = NAND ( new_n163_, new_n162_ )
new_n165_ = NAND ( new_n78_, NET_3, new_n71_ )
new_n166_ = NAND ( new_n157_, NET_10 )
new_n167_ = NAND ( new_n166_, new_n165_ )
new_n168_ = NAND ( new_n88_, NET_4, new_n79_ )
new_n169_ = AND ( new_n168_, new_n156_, new_n120_ )
new_n170_ = NOT ( NET_26 )
new_n171_ = NAND ( new_n102_, new_n170_, NET_2 )
new_n172_ = NAND ( new_n102_, new_n150_ )
new_n173_ = NAND ( new_n172_, new_n171_, new_n169_ )
new_n174_ = NAND ( new_n173_, new_n167_ )
new_n175_ = OR ( new_n173_, new_n71_ )
NET_187 = NAND ( new_n175_, new_n174_ )
new_n177_ = XNOR ( NET_28, NET_24 )
new_n178_ = NAND ( new_n177_, new_n71_ )
new_n179_ = OR ( new_n177_, new_n71_ )
new_n180_ = NAND ( new_n179_, new_n178_, NET_27, NET_17 )
new_n181_ = NAND ( new_n157_, NET_8 )
new_n182_ = NAND ( new_n181_, new_n180_ )
new_n183_ = NAND ( NET_27, NET_17 )
new_n184_ = OR ( new_n100_, NET_3 )
new_n185_ = AND ( new_n184_, new_n183_ )
new_n186_ = OR ( new_n185_, new_n53_ )
new_n187_ = NAND ( new_n186_, new_n169_ )
new_n188_ = NAND ( new_n187_, new_n182_ )
new_n189_ = OR ( new_n187_, new_n63_ )
NET_188 = NAND ( new_n189_, new_n188_ )
new_n191_ = NAND ( new_n78_, NET_3, new_n67_ )
new_n192_ = NAND ( new_n157_, NET_9 )
new_n193_ = NAND ( new_n192_, new_n191_ )
new_n194_ = NOT ( NET_22 )
new_n195_ = NAND ( new_n102_, new_n194_, NET_1 )
new_n196_ = NAND ( new_n195_, new_n172_, new_n169_ )
new_n197_ = NAND ( new_n196_, new_n193_ )
new_n198_ = OR ( new_n196_, new_n67_ )
NET_189 = NAND ( new_n198_, new_n197_ )
NET_29 = BUF ( NET_23 )
NET_30 = BUF ( NET_20 )
NET_31 = BUF ( NET_12 )
NET_32 = BUF ( NET_13 )
NET_33 = BUF ( NET_14 )
NET_34 = BUF ( NET_15 )

467
ITC99BENCH/b11.bench
View File

@ -1,467 +0,0 @@
# generated by verilog2bench.py https://gitea.yuhangq.com/YuhangQ/any2bench
INPUT(NET_1)
INPUT(NET_10)
INPUT(NET_11)
INPUT(NET_12)
INPUT(NET_13)
INPUT(NET_14)
INPUT(NET_15)
INPUT(NET_16)
INPUT(NET_17)
INPUT(NET_18)
INPUT(NET_19)
INPUT(NET_2)
INPUT(NET_20)
INPUT(NET_21)
INPUT(NET_22)
INPUT(NET_23)
INPUT(NET_24)
INPUT(NET_25)
INPUT(NET_26)
INPUT(NET_27)
INPUT(NET_28)
INPUT(NET_29)
INPUT(NET_3)
INPUT(NET_30)
INPUT(NET_31)
INPUT(NET_32)
INPUT(NET_33)
INPUT(NET_34)
INPUT(NET_35)
INPUT(NET_36)
INPUT(NET_37)
INPUT(NET_38)
INPUT(NET_4)
INPUT(NET_5)
INPUT(NET_6)
INPUT(NET_7)
INPUT(NET_8)
INPUT(NET_9)
OUTPUT(NET_136)
OUTPUT(NET_140)
OUTPUT(NET_141)
OUTPUT(NET_142)
OUTPUT(NET_143)
OUTPUT(NET_144)
OUTPUT(NET_145)
OUTPUT(NET_169)
OUTPUT(NET_380)
OUTPUT(NET_381)
OUTPUT(NET_382)
OUTPUT(NET_383)
OUTPUT(NET_39)
OUTPUT(NET_40)
OUTPUT(NET_404)
OUTPUT(NET_405)
OUTPUT(NET_406)
OUTPUT(NET_407)
OUTPUT(NET_408)
OUTPUT(NET_41)
OUTPUT(NET_42)
OUTPUT(NET_426)
OUTPUT(NET_43)
OUTPUT(NET_44)
OUTPUT(NET_444)
OUTPUT(NET_445)
OUTPUT(NET_446)
OUTPUT(NET_447)
OUTPUT(NET_448)
OUTPUT(NET_449)
OUTPUT(NET_450)
OUTPUT(NET_460)
OUTPUT(NET_461)
OUTPUT(NET_462)
OUTPUT(NET_470)
OUTPUT(NET_478)
OUTPUT(NET_481)
new_n76_ = NOT ( NET_37 )
new_n77_ = NOR ( new_n76_, NET_36 )
new_n78_ = NAND ( new_n77_, NET_38 )
new_n79_ = NOT ( NET_36 )
new_n80_ = OR ( NET_38, new_n79_ )
new_n81_ = OR ( NET_37, new_n79_ )
NET_136 = NAND ( new_n81_, new_n80_, new_n78_ )
new_n83_ = NOR ( NET_37, NET_35 )
new_n84_ = NOT ( new_n83_ )
new_n85_ = NOR ( new_n84_, NET_36 )
new_n86_ = NAND ( new_n85_, NET_1 )
new_n87_ = NOT ( NET_8 )
new_n88_ = OR ( new_n85_, new_n87_ )
NET_140 = NAND ( new_n88_, new_n86_ )
new_n90_ = NAND ( new_n85_, NET_2 )
new_n91_ = NOT ( NET_9 )
new_n92_ = OR ( new_n85_, new_n91_ )
NET_141 = NAND ( new_n92_, new_n90_ )
new_n94_ = NAND ( new_n85_, NET_3 )
new_n95_ = NOT ( NET_10 )
new_n96_ = OR ( new_n85_, new_n95_ )
NET_142 = NAND ( new_n96_, new_n94_ )
new_n98_ = NAND ( new_n85_, NET_4 )
new_n99_ = NOT ( NET_11 )
new_n100_ = OR ( new_n85_, new_n99_ )
NET_143 = NAND ( new_n100_, new_n98_ )
new_n102_ = NAND ( new_n85_, NET_5 )
new_n103_ = NOT ( NET_12 )
new_n104_ = OR ( new_n85_, new_n103_ )
NET_144 = NAND ( new_n104_, new_n102_ )
new_n106_ = NAND ( new_n85_, NET_6 )
new_n107_ = NOT ( NET_13 )
new_n108_ = OR ( new_n85_, new_n107_ )
NET_145 = NAND ( new_n108_, new_n106_ )
new_n110_ = NOT ( NET_38 )
new_n111_ = NAND ( NET_37, NET_36 )
new_n112_ = OR ( new_n111_, new_n110_ )
new_n113_ = OR ( NET_13, NET_11 )
new_n114_ = NAND ( NET_9, NET_13 )
new_n115_ = NAND ( new_n114_, new_n113_ )
new_n116_ = OR ( new_n103_, NET_11 )
new_n117_ = OR ( NET_12, new_n95_ )
new_n118_ = OR ( new_n91_, NET_8 )
new_n119_ = OR ( new_n87_, NET_10 )
new_n120_ = AND ( new_n119_, new_n118_, new_n117_, new_n116_ )
new_n121_ = AND ( new_n120_, new_n115_ )
new_n122_ = NAND ( new_n121_, new_n77_, new_n110_ )
NET_169 = NAND ( new_n122_, new_n112_ )
new_n124_ = OR ( new_n111_, NET_38 )
new_n125_ = NOT ( NET_35 )
new_n126_ = NAND ( new_n121_, new_n79_, new_n125_, NET_18 )
new_n127_ = NAND ( new_n111_, new_n84_ )
new_n128_ = NOT ( new_n127_ )
new_n129_ = NOT ( new_n121_ )
new_n130_ = NAND ( new_n129_, new_n79_, new_n125_ )
new_n131_ = AND ( new_n130_, new_n128_ )
new_n132_ = NAND ( NET_35, NET_27 )
new_n133_ = NAND ( new_n132_, new_n131_, new_n126_ )
new_n134_ = NOT ( NET_27 )
new_n135_ = NOR ( new_n128_, new_n134_ )
new_n136_ = NOR ( new_n130_, new_n103_ )
new_n137_ = NOR ( new_n136_, new_n135_ )
new_n138_ = AND ( new_n137_, new_n133_ )
new_n139_ = NAND ( new_n121_, new_n79_, new_n125_ )
new_n140_ = OR ( new_n130_, new_n107_ )
new_n141_ = NAND ( new_n127_, NET_28 )
new_n142_ = NAND ( new_n141_, new_n140_, new_n139_ )
new_n143_ = NAND ( new_n121_, new_n79_, new_n125_, NET_19 )
new_n144_ = NAND ( NET_35, NET_28 )
new_n145_ = NAND ( new_n144_, new_n143_, new_n142_, new_n111_ )
new_n146_ = OR ( new_n145_, new_n138_ )
new_n147_ = NOT ( NET_26 )
new_n148_ = NOR ( new_n128_, new_n147_ )
new_n149_ = NOR ( new_n130_, new_n99_ )
new_n150_ = NOR ( new_n149_, new_n148_ )
new_n151_ = NOT ( NET_17 )
new_n152_ = OR ( new_n139_, new_n151_ )
new_n153_ = NAND ( NET_35, NET_26 )
new_n154_ = NAND ( new_n153_, new_n152_, new_n111_ )
new_n155_ = OR ( new_n154_, new_n150_ )
new_n156_ = OR ( new_n137_, new_n133_ )
new_n157_ = NAND ( new_n156_, new_n155_, new_n146_ )
new_n158_ = NOT ( NET_16 )
new_n159_ = OR ( new_n139_, new_n158_ )
new_n160_ = NAND ( NET_35, NET_25 )
new_n161_ = NAND ( new_n160_, new_n159_, new_n131_ )
new_n162_ = OR ( new_n130_, new_n95_ )
new_n163_ = NAND ( new_n127_, NET_25 )
new_n164_ = AND ( new_n163_, new_n162_, new_n139_ )
new_n165_ = NAND ( new_n164_, new_n161_ )
new_n166_ = NAND ( new_n154_, new_n150_ )
new_n167_ = NAND ( new_n166_, new_n165_, new_n157_ )
new_n168_ = OR ( new_n130_, new_n91_ )
new_n169_ = NAND ( new_n127_, NET_24 )
new_n170_ = AND ( new_n169_, new_n168_, new_n139_ )
new_n171_ = NOT ( NET_15 )
new_n172_ = OR ( new_n139_, new_n171_ )
new_n173_ = NAND ( NET_35, NET_24 )
new_n174_ = NAND ( new_n173_, new_n172_, new_n131_ )
new_n175_ = OR ( new_n174_, new_n170_ )
new_n176_ = OR ( new_n164_, new_n161_ )
new_n177_ = NAND ( new_n176_, new_n175_, new_n167_ )
new_n178_ = NOT ( NET_14 )
new_n179_ = OR ( new_n139_, new_n178_ )
new_n180_ = NAND ( NET_35, NET_23 )
new_n181_ = NAND ( new_n180_, new_n179_, new_n111_ )
new_n182_ = NOT ( NET_23 )
new_n183_ = NOR ( new_n128_, new_n182_ )
new_n184_ = NOR ( new_n130_, new_n87_ )
new_n185_ = NOR ( new_n184_, new_n183_ )
new_n186_ = NAND ( new_n185_, new_n181_ )
new_n187_ = NAND ( new_n174_, new_n170_ )
new_n188_ = NAND ( new_n187_, new_n186_, new_n177_ )
new_n189_ = NAND ( new_n127_, new_n125_, NET_22 )
new_n190_ = OR ( new_n185_, new_n181_ )
new_n191_ = NAND ( new_n190_, new_n189_, new_n188_ )
new_n192_ = NAND ( new_n128_, NET_35, NET_21 )
new_n193_ = NAND ( new_n128_, NET_35, NET_22 )
new_n194_ = NAND ( new_n193_, new_n192_, new_n191_ )
new_n195_ = NAND ( new_n127_, new_n125_, NET_21 )
new_n196_ = NAND ( new_n128_, NET_35, NET_20 )
new_n197_ = NAND ( new_n127_, new_n125_, NET_20 )
new_n198_ = NAND ( new_n197_, new_n196_, new_n195_, new_n194_ )
new_n199_ = NOT ( new_n77_ )
new_n200_ = NAND ( new_n127_, new_n199_, new_n125_, NET_20 )
new_n201_ = NAND ( new_n200_, new_n198_ )
new_n202_ = NOT ( new_n201_ )
new_n203_ = OR ( new_n202_, new_n124_ )
new_n204_ = NAND ( new_n129_, new_n77_, new_n110_ )
new_n205_ = NAND ( NET_7, new_n76_, new_n79_ )
new_n206_ = NOR ( new_n110_, NET_37 )
new_n207_ = NAND ( new_n206_, NET_36 )
new_n208_ = NAND ( new_n110_, new_n76_, new_n79_ )
new_n209_ = OR ( new_n81_, new_n103_ )
new_n210_ = AND ( new_n209_, new_n208_, new_n207_, new_n205_ )
NET_380 = NAND ( new_n210_, new_n204_, new_n203_ )
new_n212_ = AND ( NET_38, NET_37 )
new_n213_ = NAND ( new_n212_, NET_11, NET_10 )
new_n214_ = NAND ( new_n212_, new_n99_, NET_10 )
new_n215_ = NAND ( new_n83_, new_n110_, new_n103_ )
new_n216_ = NAND ( new_n215_, new_n214_, new_n213_, new_n124_ )
new_n217_ = NOR ( new_n216_, NET_35 )
new_n218_ = OR ( new_n217_, new_n147_ )
new_n219_ = NAND ( new_n83_, new_n110_, NET_12 )
new_n220_ = OR ( new_n219_, new_n99_ )
new_n221_ = NAND ( new_n212_, new_n99_, new_n95_ )
new_n222_ = NAND ( new_n221_, new_n220_, new_n218_, new_n152_ )
new_n223_ = NOT ( new_n206_ )
new_n224_ = OR ( NET_37, NET_12 )
new_n225_ = OR ( new_n110_, NET_10 )
new_n226_ = NAND ( new_n225_, new_n224_, new_n223_, new_n125_ )
new_n227_ = XOR ( new_n226_, new_n222_ )
new_n228_ = NAND ( NET_38, NET_37 )
new_n229_ = NOR ( new_n228_, new_n99_, NET_10 )
new_n230_ = NOR ( new_n229_, new_n206_ )
new_n231_ = NAND ( new_n230_, new_n221_, new_n219_ )
new_n232_ = NAND ( new_n231_, NET_26 )
new_n233_ = OR ( new_n215_, new_n99_ )
new_n234_ = NAND ( new_n233_, new_n232_, new_n214_, new_n213_ )
new_n235_ = OR ( new_n234_, new_n227_ )
new_n236_ = NAND ( new_n234_, new_n227_ )
new_n237_ = NAND ( new_n236_, new_n235_ )
new_n238_ = NAND ( new_n231_, NET_28 )
new_n239_ = OR ( new_n215_, new_n107_ )
new_n240_ = NAND ( new_n239_, new_n238_, new_n214_, new_n139_ )
new_n241_ = NOT ( NET_28 )
new_n242_ = OR ( new_n217_, new_n241_ )
new_n243_ = OR ( new_n219_, new_n107_ )
new_n244_ = AND ( new_n243_, new_n242_, new_n221_, new_n143_ )
new_n245_ = NOR ( new_n244_, new_n240_ )
new_n246_ = NAND ( new_n243_, new_n242_, new_n221_, new_n143_ )
new_n247_ = NOR ( new_n246_, new_n226_ )
new_n248_ = OR ( new_n247_, new_n245_ )
new_n249_ = OR ( new_n217_, new_n134_ )
new_n250_ = NAND ( new_n249_, new_n230_, new_n219_, new_n126_ )
new_n251_ = XOR ( new_n250_, new_n226_ )
new_n252_ = NAND ( new_n231_, NET_27 )
new_n253_ = NAND ( new_n252_, new_n214_, new_n124_ )
new_n254_ = NOR ( new_n253_, new_n251_ )
new_n255_ = OR ( new_n254_, new_n248_ )
new_n256_ = NAND ( new_n253_, new_n251_ )
new_n257_ = NAND ( new_n256_, new_n255_ )
new_n258_ = XNOR ( new_n257_, new_n237_ )
new_n259_ = NAND ( new_n85_, new_n110_ )
new_n260_ = NAND ( new_n259_, new_n122_ )
new_n261_ = AND ( new_n260_, new_n202_, NET_37 )
new_n262_ = NAND ( new_n261_, new_n258_ )
new_n263_ = OR ( new_n260_, new_n151_ )
NET_381 = NAND ( new_n263_, new_n262_ )
new_n265_ = NOT ( new_n254_ )
new_n266_ = NAND ( new_n256_, new_n265_ )
new_n267_ = XOR ( new_n266_, new_n248_ )
new_n268_ = NAND ( new_n267_, new_n261_ )
new_n269_ = NOT ( NET_18 )
new_n270_ = OR ( new_n260_, new_n269_ )
NET_382 = NAND ( new_n270_, new_n268_ )
new_n272_ = AND ( new_n246_, new_n226_ )
new_n273_ = NOR ( new_n272_, new_n247_ )
new_n274_ = XOR ( new_n273_, new_n240_ )
new_n275_ = XOR ( new_n274_, new_n226_ )
new_n276_ = NAND ( new_n275_, new_n261_ )
new_n277_ = NOT ( NET_19 )
new_n278_ = OR ( new_n260_, new_n277_ )
NET_383 = NAND ( new_n278_, new_n276_ )
new_n280_ = NOT ( NET_25 )
new_n281_ = OR ( new_n217_, new_n280_ )
new_n282_ = OR ( new_n219_, new_n95_ )
new_n283_ = NAND ( new_n282_, new_n281_, new_n230_, new_n159_ )
new_n284_ = XOR ( new_n283_, new_n226_ )
new_n285_ = AND ( new_n213_, new_n124_ )
new_n286_ = NAND ( new_n231_, NET_25 )
new_n287_ = OR ( new_n215_, new_n95_ )
new_n288_ = NAND ( new_n287_, new_n286_, new_n285_ )
new_n289_ = OR ( new_n288_, new_n284_ )
new_n290_ = NAND ( new_n288_, new_n284_ )
new_n291_ = NAND ( new_n290_, new_n289_ )
new_n292_ = NAND ( new_n257_, new_n235_ )
new_n293_ = NAND ( new_n292_, new_n236_ )
new_n294_ = XNOR ( new_n293_, new_n291_ )
new_n295_ = NAND ( new_n294_, new_n261_ )
new_n296_ = OR ( new_n260_, new_n158_ )
NET_404 = NAND ( new_n296_, new_n295_ )
new_n298_ = OR ( new_n208_, new_n202_, new_n125_ )
new_n299_ = OR ( new_n298_, new_n280_ )
new_n300_ = NAND ( new_n208_, NET_31 )
new_n301_ = NOR ( new_n208_, new_n201_, new_n125_ )
new_n302_ = NAND ( new_n301_, new_n294_ )
NET_405 = NAND ( new_n302_, new_n300_, new_n299_ )
new_n304_ = OR ( new_n298_, new_n147_ )
new_n305_ = NAND ( new_n208_, NET_32 )
new_n306_ = NAND ( new_n301_, new_n258_ )
NET_406 = NAND ( new_n306_, new_n305_, new_n304_ )
new_n308_ = OR ( new_n298_, new_n134_ )
new_n309_ = NAND ( new_n208_, NET_33 )
new_n310_ = NAND ( new_n301_, new_n267_ )
NET_407 = NAND ( new_n310_, new_n309_, new_n308_ )
new_n312_ = OR ( new_n298_, new_n241_ )
new_n313_ = NAND ( new_n208_, NET_34 )
new_n314_ = NAND ( new_n301_, new_n275_ )
NET_408 = NAND ( new_n314_, new_n313_, new_n312_ )
new_n316_ = OR ( NET_38, NET_12 )
new_n317_ = NAND ( new_n206_, new_n201_ )
new_n318_ = NAND ( new_n317_, new_n316_ )
new_n319_ = NAND ( new_n318_, NET_36 )
new_n320_ = OR ( new_n204_, new_n202_ )
new_n321_ = OR ( new_n223_, NET_7, NET_36 )
NET_426 = NAND ( new_n321_, new_n320_, new_n319_, new_n124_ )
new_n323_ = NOT ( NET_24 )
new_n324_ = NOR ( new_n217_, new_n323_ )
new_n325_ = OR ( new_n219_, new_n91_ )
new_n326_ = NAND ( new_n325_, new_n221_, new_n223_, new_n172_ )
new_n327_ = OR ( new_n326_, new_n324_ )
new_n328_ = XOR ( new_n327_, new_n226_ )
new_n329_ = NAND ( new_n231_, NET_24 )
new_n330_ = OR ( new_n215_, new_n91_ )
new_n331_ = NAND ( new_n330_, new_n329_, new_n285_ )
new_n332_ = OR ( new_n331_, new_n328_ )
new_n333_ = NAND ( new_n331_, new_n328_ )
new_n334_ = NAND ( new_n333_, new_n332_ )
new_n335_ = NAND ( new_n293_, new_n289_ )
new_n336_ = NAND ( new_n335_, new_n290_ )
new_n337_ = XNOR ( new_n336_, new_n334_ )
new_n338_ = NAND ( new_n337_, new_n261_ )
new_n339_ = OR ( new_n260_, new_n171_ )
NET_444 = NAND ( new_n339_, new_n338_ )
new_n341_ = OR ( new_n201_, new_n79_ )
new_n342_ = NAND ( new_n121_, new_n77_ )
new_n343_ = OR ( new_n81_, NET_38 )
new_n344_ = AND ( new_n343_, new_n342_, new_n228_ )
new_n345_ = NAND ( new_n344_, new_n341_ )
new_n346_ = AND ( new_n345_, new_n199_ )
new_n347_ = NAND ( new_n346_, new_n337_ )
new_n348_ = NAND ( new_n345_, new_n110_, new_n79_ )
new_n349_ = OR ( new_n348_, new_n91_ )
new_n350_ = OR ( new_n345_, new_n323_ )
new_n351_ = AND ( NET_38, NET_37, new_n79_ )
new_n352_ = NAND ( new_n351_, new_n107_ )
new_n353_ = NOR ( new_n352_, new_n171_ )
new_n354_ = NAND ( new_n351_, NET_13 )
new_n355_ = NOR ( new_n354_, new_n158_ )
new_n356_ = NOR ( new_n355_, new_n353_ )
NET_445 = NAND ( new_n356_, new_n350_, new_n349_, new_n347_ )
new_n358_ = NAND ( new_n346_, new_n294_ )
new_n359_ = OR ( new_n348_, new_n95_ )
new_n360_ = OR ( new_n345_, new_n280_ )
new_n361_ = NOR ( new_n352_, new_n158_ )
new_n362_ = NOR ( new_n354_, new_n151_ )
new_n363_ = NOR ( new_n362_, new_n361_ )
NET_446 = NAND ( new_n363_, new_n360_, new_n359_, new_n358_ )
new_n365_ = NAND ( new_n346_, new_n258_ )
new_n366_ = OR ( new_n348_, new_n99_ )
new_n367_ = OR ( new_n345_, new_n147_ )
new_n368_ = NOR ( new_n352_, new_n151_ )
new_n369_ = NOR ( new_n354_, new_n269_ )
new_n370_ = NOR ( new_n369_, new_n368_ )
NET_447 = NAND ( new_n370_, new_n367_, new_n366_, new_n365_ )
new_n372_ = NAND ( new_n346_, new_n267_ )
new_n373_ = OR ( new_n348_, new_n103_ )
new_n374_ = OR ( new_n345_, new_n134_ )
new_n375_ = NOR ( new_n352_, new_n269_ )
new_n376_ = NOR ( new_n354_, new_n277_ )
new_n377_ = NOR ( new_n376_, new_n375_ )
NET_448 = NAND ( new_n377_, new_n374_, new_n373_, new_n372_ )
new_n379_ = OR ( new_n352_, new_n277_ )
new_n380_ = OR ( new_n348_, new_n107_ )
new_n381_ = NAND ( new_n346_, new_n275_ )
new_n382_ = OR ( new_n345_, new_n241_ )
NET_449 = NAND ( new_n382_, new_n381_, new_n380_, new_n379_ )
new_n384_ = OR ( new_n298_, new_n323_ )
new_n385_ = NAND ( new_n208_, NET_30 )
new_n386_ = NAND ( new_n337_, new_n301_ )
NET_450 = NAND ( new_n386_, new_n385_, new_n384_ )
new_n388_ = NOT ( new_n229_ )
new_n389_ = OR ( new_n217_, new_n182_ )
new_n390_ = OR ( new_n219_, new_n87_ )
new_n391_ = NAND ( new_n390_, new_n389_, new_n388_, new_n179_ )
new_n392_ = XOR ( new_n391_, new_n226_ )
new_n393_ = NAND ( new_n231_, NET_23 )
new_n394_ = OR ( new_n215_, new_n87_ )
new_n395_ = NAND ( new_n394_, new_n393_ )
new_n396_ = OR ( new_n395_, new_n392_ )
new_n397_ = NAND ( new_n395_, new_n392_ )
new_n398_ = NAND ( new_n397_, new_n396_ )
new_n399_ = NAND ( new_n336_, new_n332_ )
new_n400_ = NAND ( new_n399_, new_n333_ )
new_n401_ = XNOR ( new_n400_, new_n398_ )
new_n402_ = NAND ( new_n401_, new_n261_ )
new_n403_ = OR ( new_n260_, new_n178_ )
NET_460 = NAND ( new_n403_, new_n402_ )
new_n405_ = NAND ( new_n401_, new_n346_ )
new_n406_ = OR ( new_n348_, new_n87_ )
new_n407_ = OR ( new_n345_, new_n182_ )
new_n408_ = NOR ( new_n352_, new_n178_ )
new_n409_ = NOR ( new_n354_, new_n171_ )
new_n410_ = NOR ( new_n409_, new_n408_ )
NET_461 = NAND ( new_n410_, new_n407_, new_n406_, new_n405_ )
new_n412_ = NAND ( new_n401_, new_n301_ )
new_n413_ = NAND ( new_n208_, NET_29 )
new_n414_ = OR ( new_n298_, new_n182_ )
NET_462 = NAND ( new_n414_, new_n413_, new_n412_ )
new_n416_ = NAND ( new_n216_, NET_22 )
new_n417_ = NAND ( new_n416_, new_n180_ )
new_n418_ = XOR ( new_n417_, new_n226_ )
new_n419_ = NOT ( new_n418_ )
new_n420_ = NAND ( new_n231_, NET_22 )
new_n421_ = OR ( new_n420_, new_n419_ )
new_n422_ = NAND ( new_n420_, new_n419_ )
new_n423_ = AND ( new_n422_, new_n421_ )
new_n424_ = NAND ( new_n400_, new_n396_ )
new_n425_ = NAND ( new_n424_, new_n397_ )
new_n426_ = NAND ( new_n425_, new_n423_ )
new_n427_ = OR ( new_n425_, new_n423_ )
new_n428_ = NAND ( new_n427_, new_n426_, new_n346_ )
new_n429_ = NAND ( new_n344_, new_n341_, NET_22 )
new_n430_ = OR ( new_n354_, new_n178_ )
NET_470 = NAND ( new_n430_, new_n429_, new_n428_ )
new_n432_ = NAND ( new_n216_, NET_21 )
new_n433_ = NAND ( new_n432_, new_n180_ )
new_n434_ = XOR ( new_n433_, new_n226_ )
new_n435_ = NOT ( new_n434_ )
new_n436_ = NAND ( new_n231_, NET_21 )
new_n437_ = OR ( new_n436_, new_n435_ )
new_n438_ = NAND ( new_n436_, new_n435_ )
new_n439_ = NAND ( new_n425_, new_n422_ )
new_n440_ = NAND ( new_n439_, new_n421_ )
new_n441_ = NAND ( new_n440_, new_n438_, new_n437_ )
new_n442_ = NAND ( new_n438_, new_n437_ )
new_n443_ = NAND ( new_n442_, new_n439_, new_n421_ )
new_n444_ = NAND ( new_n443_, new_n441_, new_n346_ )
new_n445_ = NAND ( new_n344_, new_n341_, NET_21 )
NET_478 = NAND ( new_n445_, new_n444_ )
new_n447_ = NAND ( new_n440_, new_n438_ )
new_n448_ = AND ( new_n447_, new_n437_ )
new_n449_ = NAND ( new_n231_, NET_20 )
new_n450_ = OR ( new_n449_, new_n448_ )
new_n451_ = NAND ( new_n449_, new_n447_, new_n437_ )
new_n452_ = NAND ( new_n451_, new_n450_ )
new_n453_ = NAND ( new_n216_, NET_20 )
new_n454_ = NAND ( new_n453_, new_n180_ )
new_n455_ = XNOR ( new_n454_, new_n226_ )
new_n456_ = OR ( new_n455_, new_n452_ )
new_n457_ = NAND ( new_n455_, new_n452_ )
new_n458_ = NAND ( new_n457_, new_n456_, new_n346_ )
new_n459_ = NAND ( new_n344_, new_n341_, NET_20 )
NET_481 = NAND ( new_n459_, new_n458_ )
NET_39 = BUF ( NET_29 )
NET_40 = BUF ( NET_30 )
NET_41 = BUF ( NET_31 )
NET_42 = BUF ( NET_32 )
NET_43 = BUF ( NET_33 )
NET_44 = BUF ( NET_34 )

1167
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@ -1,386 +0,0 @@
# generated by verilog2bench.py https://gitea.yuhangq.com/YuhangQ/any2bench
INPUT(NET_1)
INPUT(NET_10)
INPUT(NET_11)
INPUT(NET_12)
INPUT(NET_13)
INPUT(NET_14)
INPUT(NET_15)
INPUT(NET_16)
INPUT(NET_17)
INPUT(NET_18)
INPUT(NET_19)
INPUT(NET_2)
INPUT(NET_20)
INPUT(NET_21)
INPUT(NET_22)
INPUT(NET_23)
INPUT(NET_24)
INPUT(NET_25)
INPUT(NET_26)
INPUT(NET_27)
INPUT(NET_28)
INPUT(NET_29)
INPUT(NET_3)
INPUT(NET_30)
INPUT(NET_31)
INPUT(NET_32)
INPUT(NET_33)
INPUT(NET_34)
INPUT(NET_35)
INPUT(NET_36)
INPUT(NET_37)
INPUT(NET_38)
INPUT(NET_39)
INPUT(NET_4)
INPUT(NET_40)
INPUT(NET_41)
INPUT(NET_42)
INPUT(NET_43)
INPUT(NET_44)
INPUT(NET_45)
INPUT(NET_46)
INPUT(NET_47)
INPUT(NET_48)
INPUT(NET_49)
INPUT(NET_5)
INPUT(NET_50)
INPUT(NET_51)
INPUT(NET_52)
INPUT(NET_53)
INPUT(NET_54)
INPUT(NET_55)
INPUT(NET_56)
INPUT(NET_57)
INPUT(NET_58)
INPUT(NET_59)
INPUT(NET_6)
INPUT(NET_60)
INPUT(NET_61)
INPUT(NET_62)
INPUT(NET_63)
INPUT(NET_7)
INPUT(NET_8)
INPUT(NET_9)
OUTPUT(NET_171)
OUTPUT(NET_172)
OUTPUT(NET_173)
OUTPUT(NET_174)
OUTPUT(NET_215)
OUTPUT(NET_216)
OUTPUT(NET_217)
OUTPUT(NET_218)
OUTPUT(NET_219)
OUTPUT(NET_220)
OUTPUT(NET_221)
OUTPUT(NET_223)
OUTPUT(NET_224)
OUTPUT(NET_225)
OUTPUT(NET_251)
OUTPUT(NET_252)
OUTPUT(NET_253)
OUTPUT(NET_255)
OUTPUT(NET_256)
OUTPUT(NET_257)
OUTPUT(NET_258)
OUTPUT(NET_259)
OUTPUT(NET_260)
OUTPUT(NET_261)
OUTPUT(NET_262)
OUTPUT(NET_263)
OUTPUT(NET_264)
OUTPUT(NET_286)
OUTPUT(NET_287)
OUTPUT(NET_288)
OUTPUT(NET_289)
OUTPUT(NET_290)
OUTPUT(NET_291)
OUTPUT(NET_292)
OUTPUT(NET_301)
OUTPUT(NET_302)
OUTPUT(NET_303)
OUTPUT(NET_318)
OUTPUT(NET_319)
OUTPUT(NET_320)
OUTPUT(NET_321)
OUTPUT(NET_322)
OUTPUT(NET_323)
OUTPUT(NET_324)
OUTPUT(NET_325)
OUTPUT(NET_326)
OUTPUT(NET_327)
OUTPUT(NET_328)
OUTPUT(NET_333)
OUTPUT(NET_337)
OUTPUT(NET_338)
OUTPUT(NET_339)
OUTPUT(NET_64)
OUTPUT(NET_65)
OUTPUT(NET_66)
OUTPUT(NET_67)
OUTPUT(NET_68)
OUTPUT(NET_69)
OUTPUT(NET_70)
OUTPUT(NET_71)
OUTPUT(NET_72)
OUTPUT(NET_73)
OUTPUT(NET_75)
new_n127_ = NOT ( NET_58 )
new_n128_ = OR ( NET_59, new_n127_ )
new_n129_ = NAND ( NET_59, NET_57 )
NET_171 = NAND ( new_n129_, new_n128_ )
new_n131_ = OR ( new_n127_, NET_57, NET_55 )
new_n132_ = NAND ( new_n127_, NET_57, NET_1 )
NET_172 = NAND ( new_n132_, new_n131_, NET_59 )
new_n134_ = NOT ( NET_50 )
new_n135_ = NAND ( NET_47, NET_10 )
new_n136_ = OR ( new_n135_, new_n134_ )
new_n137_ = NOT ( NET_44 )
new_n138_ = OR ( NET_62, new_n137_ )
NET_173 = NAND ( new_n138_, new_n136_ )
new_n140_ = NOR ( NET_50, NET_42 )
new_n141_ = OR ( new_n140_, NET_46 )
new_n142_ = NAND ( NET_50, NET_42 )
NET_174 = NAND ( new_n142_, new_n141_ )
new_n144_ = NOT ( NET_61 )
new_n145_ = NAND ( new_n144_, NET_60, NET_52 )
new_n146_ = NOT ( NET_60 )
new_n147_ = NAND ( new_n144_, new_n146_, NET_43 )
NET_215 = NAND ( new_n147_, new_n145_ )
new_n149_ = NOR ( NET_46, NET_42 )
new_n150_ = NAND ( new_n149_, NET_53 )
new_n151_ = NOT ( NET_46 )
new_n152_ = NAND ( new_n151_, NET_42 )
new_n153_ = NAND ( new_n152_, NET_41 )
NET_216 = NAND ( new_n153_, new_n150_ )
new_n155_ = NAND ( NET_62, NET_42 )
new_n156_ = NAND ( new_n155_, NET_46 )
new_n157_ = NOT ( NET_53 )
new_n158_ = OR ( new_n157_, NET_42 )
NET_217 = NAND ( new_n158_, new_n156_ )
new_n160_ = OR ( new_n129_, new_n127_ )
new_n161_ = NOT ( NET_59 )
new_n162_ = NAND ( NET_58, NET_55 )
new_n163_ = OR ( new_n162_, new_n161_ )
new_n164_ = NAND ( new_n163_, NET_43 )
NET_218 = NAND ( new_n164_, new_n160_ )
new_n166_ = NOT ( NET_57 )
new_n167_ = NAND ( new_n161_, new_n127_, new_n166_ )
new_n168_ = OR ( NET_58, NET_1 )
new_n169_ = OR ( new_n168_, new_n129_ )
new_n170_ = NAND ( new_n169_, NET_45 )
NET_219 = NAND ( new_n170_, new_n167_ )
new_n172_ = OR ( new_n155_, new_n151_ )
new_n173_ = NOT ( NET_52 )
new_n174_ = OR ( new_n149_, new_n173_ )
NET_220 = NAND ( new_n174_, new_n172_ )
new_n176_ = NAND ( new_n144_, NET_60, new_n173_ )
new_n177_ = NAND ( new_n176_, NET_53 )
new_n178_ = OR ( new_n144_, NET_60 )
NET_221 = NAND ( new_n178_, new_n177_ )
new_n180_ = OR ( new_n151_, NET_42 )
new_n181_ = NAND ( NET_62, NET_46 )
new_n182_ = NAND ( new_n181_, NET_42 )
NET_223 = NAND ( new_n182_, new_n180_ )
new_n184_ = NAND ( new_n128_, NET_49 )
new_n185_ = OR ( new_n128_, NET_57 )
NET_224 = NAND ( new_n185_, new_n184_ )
new_n187_ = OR ( new_n173_, NET_51 )
new_n188_ = NAND ( new_n187_, new_n144_, NET_60 )
NET_225 = NAND ( new_n188_, new_n178_ )
new_n190_ = NAND ( new_n145_, NET_51 )
new_n191_ = OR ( new_n145_, NET_51 )
NET_251 = NAND ( new_n191_, new_n190_ )
new_n193_ = NOT ( NET_54 )
NET_252 = NAND ( new_n191_, new_n193_ )
new_n195_ = NOT ( NET_15 )
new_n196_ = NOT ( NET_16 )
new_n197_ = NAND ( NET_18, NET_17 )
new_n198_ = OR ( new_n197_, new_n196_ )
new_n199_ = NOR ( new_n128_, new_n166_ )
new_n200_ = NOT ( new_n199_ )
new_n201_ = NOR ( new_n200_, new_n198_ )
NET_253 = NOR ( new_n201_, new_n195_ )
new_n203_ = NOT ( NET_41 )
new_n204_ = NAND ( NET_56, new_n203_ )
new_n205_ = NAND ( NET_47, NET_41 )
new_n206_ = NAND ( new_n205_, new_n204_ )
new_n207_ = NAND ( new_n206_, new_n134_ )
new_n208_ = NAND ( new_n135_, NET_50 )
NET_255 = NAND ( new_n208_, new_n207_ )
new_n210_ = NOR ( NET_47, new_n203_ )
new_n211_ = NAND ( new_n210_, NET_2 )
new_n212_ = NOT ( new_n210_ )
new_n213_ = NAND ( new_n212_, NET_19 )
NET_256 = NAND ( new_n213_, new_n211_ )
new_n215_ = NAND ( new_n210_, NET_3 )
new_n216_ = NAND ( new_n212_, NET_20 )
NET_257 = NAND ( new_n216_, new_n215_ )
new_n218_ = NAND ( new_n210_, NET_4 )
new_n219_ = NAND ( new_n212_, NET_21 )
NET_258 = NAND ( new_n219_, new_n218_ )
new_n221_ = NAND ( new_n210_, NET_5 )
new_n222_ = NAND ( new_n212_, NET_22 )
NET_259 = NAND ( new_n222_, new_n221_ )
new_n224_ = NAND ( new_n210_, NET_6 )
new_n225_ = NAND ( new_n212_, NET_23 )
NET_260 = NAND ( new_n225_, new_n224_ )
new_n227_ = NAND ( new_n210_, NET_7 )
new_n228_ = NAND ( new_n212_, NET_24 )
NET_261 = NAND ( new_n228_, new_n227_ )
new_n230_ = NAND ( new_n210_, NET_8 )
new_n231_ = NAND ( new_n212_, NET_25 )
NET_262 = NAND ( new_n231_, new_n230_ )
new_n233_ = NAND ( new_n210_, NET_9 )
new_n234_ = NAND ( new_n212_, NET_26 )
NET_263 = NAND ( new_n234_, new_n233_ )
new_n236_ = OR ( NET_59, new_n166_ )
new_n237_ = NAND ( new_n162_, new_n166_ )
new_n238_ = NAND ( new_n237_, new_n168_ )
new_n239_ = NAND ( new_n238_, NET_59 )
NET_264 = NAND ( new_n239_, new_n236_ )
new_n241_ = NAND ( new_n199_, new_n198_ )
new_n242_ = OR ( new_n241_, new_n195_ )
new_n243_ = NAND ( new_n200_, NET_11 )
NET_286 = NAND ( new_n243_, new_n242_ )
new_n245_ = OR ( new_n241_, new_n196_ )
new_n246_ = NAND ( new_n200_, NET_12 )
new_n247_ = OR ( new_n241_, new_n197_ )
NET_287 = NAND ( new_n247_, new_n246_, new_n245_ )
new_n249_ = NAND ( new_n200_, NET_14 )
new_n250_ = OR ( new_n241_, NET_18 )
NET_288 = NAND ( new_n250_, new_n249_ )
new_n252_ = OR ( new_n200_, new_n197_ )
new_n253_ = NAND ( new_n252_, NET_16 )
NET_289 = NAND ( new_n253_, new_n247_ )
new_n255_ = NAND ( new_n200_, NET_18 )
NET_290 = NAND ( new_n255_, new_n250_ )
new_n257_ = NAND ( new_n200_, NET_48 )
NET_291 = NAND ( new_n257_, new_n169_ )
new_n259_ = NAND ( new_n144_, NET_60, NET_52, NET_51 )
new_n260_ = NAND ( new_n259_, NET_55 )
NET_292 = NAND ( new_n260_, new_n147_ )
new_n262_ = NOT ( NET_31 )
new_n263_ = NOT ( NET_32 )
new_n264_ = NOT ( NET_33 )
new_n265_ = NOT ( NET_37 )
new_n266_ = NOR ( NET_40, NET_39, NET_38 )
new_n267_ = NOR ( new_n266_, new_n265_ )
new_n268_ = OR ( new_n267_, NET_36 )
new_n269_ = NAND ( new_n268_, NET_35, NET_34 )
new_n270_ = NAND ( new_n269_, new_n264_, new_n263_, new_n262_ )
new_n271_ = AND ( new_n270_, NET_44 )
new_n272_ = NOT ( NET_30 )
new_n273_ = NOT ( NET_28 )
new_n274_ = NAND ( NET_29, new_n273_, NET_19 )
new_n275_ = NAND ( NET_27, NET_25 )
new_n276_ = NAND ( NET_29, NET_28, NET_23 )
new_n277_ = NOT ( NET_29 )
new_n278_ = NAND ( new_n277_, NET_28, NET_21 )
new_n279_ = NAND ( new_n278_, new_n276_, new_n275_, new_n274_ )
new_n280_ = NAND ( new_n279_, new_n272_ )
new_n281_ = NAND ( new_n277_, NET_28, NET_22 )
new_n282_ = NAND ( NET_27, NET_26 )
new_n283_ = NAND ( NET_29, NET_28, NET_24 )
new_n284_ = NOT ( NET_27 )
new_n285_ = NAND ( new_n277_, new_n273_, new_n284_ )
new_n286_ = NAND ( NET_29, new_n273_, NET_20 )
new_n287_ = AND ( new_n286_, new_n285_, new_n283_ )
new_n288_ = NAND ( new_n287_, new_n282_, new_n281_ )
new_n289_ = NAND ( new_n288_, NET_30 )
NET_301 = NAND ( new_n289_, new_n280_, new_n271_ )
new_n291_ = NOT ( NET_17 )
new_n292_ = OR ( new_n250_, new_n291_ )
new_n293_ = NAND ( new_n200_, NET_13 )
new_n294_ = NAND ( new_n199_, new_n198_, NET_18, new_n291_ )
NET_302 = NAND ( new_n294_, new_n293_, new_n292_ )
new_n296_ = NAND ( new_n199_, NET_18 )
new_n297_ = NAND ( new_n296_, NET_17 )
NET_303 = NAND ( new_n297_, new_n294_ )
new_n299_ = NAND ( new_n270_, NET_44, NET_30 )
NET_318 = NOR ( new_n299_, new_n285_ )
new_n301_ = NOR ( new_n270_, new_n137_ )
new_n302_ = NOT ( NET_34 )
new_n303_ = NOT ( NET_35 )
new_n304_ = NOT ( NET_36 )
new_n305_ = NAND ( NET_40, NET_39, NET_38 )
new_n306_ = OR ( new_n305_, new_n265_, new_n304_ )
new_n307_ = OR ( new_n306_, new_n303_ )
new_n308_ = OR ( new_n307_, new_n302_ )
new_n309_ = OR ( new_n308_, new_n264_ )
new_n310_ = NAND ( new_n309_, new_n263_ )
new_n311_ = OR ( new_n308_, new_n264_, new_n263_ )
new_n312_ = NAND ( new_n311_, new_n310_, new_n301_ )
new_n313_ = OR ( NET_44, new_n263_ )
NET_319 = NAND ( new_n313_, new_n312_ )
new_n315_ = NAND ( new_n308_, new_n264_ )
new_n316_ = NAND ( new_n315_, new_n309_, new_n301_ )
new_n317_ = OR ( NET_44, new_n264_ )
NET_320 = NAND ( new_n317_, new_n316_ )
new_n319_ = NAND ( new_n307_, new_n302_ )
new_n320_ = NAND ( new_n319_, new_n308_, new_n301_ )
new_n321_ = OR ( NET_44, new_n302_ )
NET_321 = NAND ( new_n321_, new_n320_ )
new_n323_ = NAND ( new_n306_, new_n303_ )
new_n324_ = NAND ( new_n323_, new_n307_, new_n301_ )
new_n325_ = OR ( NET_44, new_n303_ )
NET_322 = NAND ( new_n325_, new_n324_ )
new_n327_ = OR ( new_n305_, new_n265_ )
new_n328_ = NAND ( new_n327_, new_n304_ )
new_n329_ = OR ( new_n327_, new_n304_ )
new_n330_ = NAND ( new_n329_, new_n328_, new_n301_ )
new_n331_ = OR ( NET_44, new_n304_ )
NET_323 = NAND ( new_n331_, new_n330_ )
new_n333_ = NAND ( new_n305_, new_n265_ )
new_n334_ = NAND ( new_n333_, new_n327_, new_n301_ )
new_n335_ = OR ( NET_44, new_n265_ )
NET_324 = NAND ( new_n335_, new_n334_ )
new_n337_ = NOT ( NET_38 )
new_n338_ = NAND ( NET_40, NET_39 )
new_n339_ = OR ( new_n338_, new_n337_ )
new_n340_ = NAND ( new_n338_, new_n337_ )
new_n341_ = NAND ( new_n340_, new_n339_, new_n301_ )
new_n342_ = OR ( NET_44, new_n337_ )
NET_325 = NAND ( new_n342_, new_n341_ )
new_n344_ = OR ( NET_40, NET_39 )
new_n345_ = NAND ( new_n344_, new_n338_, new_n301_ )
new_n346_ = NAND ( new_n137_, NET_39 )
NET_326 = NAND ( new_n346_, new_n345_ )
new_n348_ = NOT ( NET_40 )
new_n349_ = NAND ( new_n301_, new_n348_ )
new_n350_ = OR ( NET_44, new_n348_ )
NET_327 = NAND ( new_n350_, new_n349_ )
new_n352_ = NOR ( NET_29, NET_28 )
new_n353_ = NOR ( new_n352_, NET_30 )
new_n354_ = OR ( new_n353_, NET_27 )
new_n355_ = NAND ( new_n354_, new_n271_ )
new_n356_ = OR ( new_n271_, new_n272_ )
NET_328 = NAND ( new_n356_, new_n355_ )
new_n358_ = XOR ( new_n311_, new_n262_ )
new_n359_ = NAND ( new_n358_, new_n301_ )
new_n360_ = OR ( NET_44, new_n262_ )
NET_333 = NAND ( new_n360_, new_n359_ )
new_n362_ = OR ( NET_29, new_n273_ )
new_n363_ = NAND ( new_n299_, NET_28 )
new_n364_ = OR ( new_n299_, new_n277_, NET_28 )
NET_337 = NAND ( new_n364_, new_n363_, new_n362_ )
new_n366_ = NAND ( new_n272_, new_n273_, new_n284_ )
new_n367_ = OR ( new_n362_, new_n272_ )
new_n368_ = NAND ( new_n367_, new_n366_ )
new_n369_ = NAND ( new_n368_, new_n271_ )
new_n370_ = NAND ( new_n299_, NET_29 )
NET_338 = NAND ( new_n370_, new_n369_ )
new_n372_ = OR ( new_n299_, new_n277_, new_n273_ )
new_n373_ = NAND ( new_n299_, NET_27 )
NET_339 = NAND ( new_n373_, new_n372_ )
NET_75 = OR ( NET_62, NET_47, NET_41 )
NET_64 = BUF ( NET_49 )
NET_65 = BUF ( NET_48 )
NET_66 = BUF ( NET_54 )
NET_67 = BUF ( NET_11 )
NET_68 = BUF ( NET_12 )
NET_69 = BUF ( NET_13 )
NET_70 = BUF ( NET_14 )
NET_71 = BUF ( NET_45 )
NET_72 = BUF ( NET_56 )
NET_73 = BUF ( NET_63 )

25223
ITC99BENCH/b17.bench
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9247
ITC99BENCH/b20.bench
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9508
ITC99BENCH/b21.bench
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14479
ITC99BENCH/b22.bench
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atpg
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623
bench_test/c1355.bench
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@ -1,623 +0,0 @@
# c1355
INPUT(1)
INPUT(8)
INPUT(15)
INPUT(22)
INPUT(29)
INPUT(36)
INPUT(43)
INPUT(50)
INPUT(57)
INPUT(64)
INPUT(71)
INPUT(78)
INPUT(85)
INPUT(92)
INPUT(99)
INPUT(106)
INPUT(113)
INPUT(120)
INPUT(127)
INPUT(134)
INPUT(141)
INPUT(148)
INPUT(155)
INPUT(162)
INPUT(169)
INPUT(176)
INPUT(183)
INPUT(190)
INPUT(197)
INPUT(204)
INPUT(211)
INPUT(218)
INPUT(225)
INPUT(226)
INPUT(227)
INPUT(228)
INPUT(229)
INPUT(230)
INPUT(231)
INPUT(232)
INPUT(233)
OUTPUT(1324)
OUTPUT(1325)
OUTPUT(1326)
OUTPUT(1327)
OUTPUT(1328)
OUTPUT(1329)
OUTPUT(1330)
OUTPUT(1331)
OUTPUT(1332)
OUTPUT(1333)
OUTPUT(1334)
OUTPUT(1335)
OUTPUT(1336)
OUTPUT(1337)
OUTPUT(1338)
OUTPUT(1339)
OUTPUT(1340)
OUTPUT(1341)
OUTPUT(1342)
OUTPUT(1343)
OUTPUT(1344)
OUTPUT(1345)
OUTPUT(1346)
OUTPUT(1347)
OUTPUT(1348)
OUTPUT(1349)
OUTPUT(1350)
OUTPUT(1351)
OUTPUT(1352)
OUTPUT(1353)
OUTPUT(1354)
OUTPUT(1355)
242 = AND(225, 233)
245 = AND(226, 233)
248 = AND(227, 233)
251 = AND(228, 233)
254 = AND(229, 233)
257 = AND(230, 233)
260 = AND(231, 233)
263 = AND(232, 233)
266 = NAND(1, 8)
269 = NAND(15, 22)
272 = NAND(29, 36)
275 = NAND(43, 50)
278 = NAND(57, 64)
281 = NAND(71, 78)
284 = NAND(85, 92)
287 = NAND(99, 106)
290 = NAND(113, 120)
293 = NAND(127, 134)
296 = NAND(141, 148)
299 = NAND(155, 162)
302 = NAND(169, 176)
305 = NAND(183, 190)
308 = NAND(197, 204)
311 = NAND(211, 218)
314 = NAND(1, 29)
317 = NAND(57, 85)
320 = NAND(8, 36)
323 = NAND(64, 92)
326 = NAND(15, 43)
329 = NAND(71, 99)
332 = NAND(22, 50)
335 = NAND(78, 106)
338 = NAND(113, 141)
341 = NAND(169, 197)
344 = NAND(120, 148)
347 = NAND(176, 204)
350 = NAND(127, 155)
353 = NAND(183, 211)
356 = NAND(134, 162)
359 = NAND(190, 218)
362 = NAND(1, 266)
363 = NAND(8, 266)
364 = NAND(15, 269)
365 = NAND(22, 269)
366 = NAND(29, 272)
367 = NAND(36, 272)
368 = NAND(43, 275)
369 = NAND(50, 275)
370 = NAND(57, 278)
371 = NAND(64, 278)
372 = NAND(71, 281)
373 = NAND(78, 281)
374 = NAND(85, 284)
375 = NAND(92, 284)
376 = NAND(99, 287)
377 = NAND(106, 287)
378 = NAND(113, 290)
379 = NAND(120, 290)
380 = NAND(127, 293)
381 = NAND(134, 293)
382 = NAND(141, 296)
383 = NAND(148, 296)
384 = NAND(155, 299)
385 = NAND(162, 299)
386 = NAND(169, 302)
387 = NAND(176, 302)
388 = NAND(183, 305)
389 = NAND(190, 305)
390 = NAND(197, 308)
391 = NAND(204, 308)
392 = NAND(211, 311)
393 = NAND(218, 311)
394 = NAND(1, 314)
395 = NAND(29, 314)
396 = NAND(57, 317)
397 = NAND(85, 317)
398 = NAND(8, 320)
399 = NAND(36, 320)
400 = NAND(64, 323)
401 = NAND(92, 323)
402 = NAND(15, 326)
403 = NAND(43, 326)
404 = NAND(71, 329)
405 = NAND(99, 329)
406 = NAND(22, 332)
407 = NAND(50, 332)
408 = NAND(78, 335)
409 = NAND(106, 335)
410 = NAND(113, 338)
411 = NAND(141, 338)
412 = NAND(169, 341)
413 = NAND(197, 341)
414 = NAND(120, 344)
415 = NAND(148, 344)
416 = NAND(176, 347)
417 = NAND(204, 347)
418 = NAND(127, 350)
419 = NAND(155, 350)
420 = NAND(183, 353)
421 = NAND(211, 353)
422 = NAND(134, 356)
423 = NAND(162, 356)
424 = NAND(190, 359)
425 = NAND(218, 359)
426 = NAND(362, 363)
429 = NAND(364, 365)
432 = NAND(366, 367)
435 = NAND(368, 369)
438 = NAND(370, 371)
441 = NAND(372, 373)
444 = NAND(374, 375)
447 = NAND(376, 377)
450 = NAND(378, 379)
453 = NAND(380, 381)
456 = NAND(382, 383)
459 = NAND(384, 385)
462 = NAND(386, 387)
465 = NAND(388, 389)
468 = NAND(390, 391)
471 = NAND(392, 393)
474 = NAND(394, 395)
477 = NAND(396, 397)
480 = NAND(398, 399)
483 = NAND(400, 401)
486 = NAND(402, 403)
489 = NAND(404, 405)
492 = NAND(406, 407)
495 = NAND(408, 409)
498 = NAND(410, 411)
501 = NAND(412, 413)
504 = NAND(414, 415)
507 = NAND(416, 417)
510 = NAND(418, 419)
513 = NAND(420, 421)
516 = NAND(422, 423)
519 = NAND(424, 425)
522 = NAND(426, 429)
525 = NAND(432, 435)
528 = NAND(438, 441)
531 = NAND(444, 447)
534 = NAND(450, 453)
537 = NAND(456, 459)
540 = NAND(462, 465)
543 = NAND(468, 471)
546 = NAND(474, 477)
549 = NAND(480, 483)
552 = NAND(486, 489)
555 = NAND(492, 495)
558 = NAND(498, 501)
561 = NAND(504, 507)
564 = NAND(510, 513)
567 = NAND(516, 519)
570 = NAND(426, 522)
571 = NAND(429, 522)
572 = NAND(432, 525)
573 = NAND(435, 525)
574 = NAND(438, 528)
575 = NAND(441, 528)
576 = NAND(444, 531)
577 = NAND(447, 531)
578 = NAND(450, 534)
579 = NAND(453, 534)
580 = NAND(456, 537)
581 = NAND(459, 537)
582 = NAND(462, 540)
583 = NAND(465, 540)
584 = NAND(468, 543)
585 = NAND(471, 543)
586 = NAND(474, 546)
587 = NAND(477, 546)
588 = NAND(480, 549)
589 = NAND(483, 549)
590 = NAND(486, 552)
591 = NAND(489, 552)
592 = NAND(492, 555)
593 = NAND(495, 555)
594 = NAND(498, 558)
595 = NAND(501, 558)
596 = NAND(504, 561)
597 = NAND(507, 561)
598 = NAND(510, 564)
599 = NAND(513, 564)
600 = NAND(516, 567)
601 = NAND(519, 567)
602 = NAND(570, 571)
607 = NAND(572, 573)
612 = NAND(574, 575)
617 = NAND(576, 577)
622 = NAND(578, 579)
627 = NAND(580, 581)
632 = NAND(582, 583)
637 = NAND(584, 585)
642 = NAND(586, 587)
645 = NAND(588, 589)
648 = NAND(590, 591)
651 = NAND(592, 593)
654 = NAND(594, 595)
657 = NAND(596, 597)
660 = NAND(598, 599)
663 = NAND(600, 601)
666 = NAND(602, 607)
669 = NAND(612, 617)
672 = NAND(602, 612)
675 = NAND(607, 617)
678 = NAND(622, 627)
681 = NAND(632, 637)
684 = NAND(622, 632)
687 = NAND(627, 637)
690 = NAND(602, 666)
691 = NAND(607, 666)
692 = NAND(612, 669)
693 = NAND(617, 669)
694 = NAND(602, 672)
695 = NAND(612, 672)
696 = NAND(607, 675)
697 = NAND(617, 675)
698 = NAND(622, 678)
699 = NAND(627, 678)
700 = NAND(632, 681)
701 = NAND(637, 681)
702 = NAND(622, 684)
703 = NAND(632, 684)
704 = NAND(627, 687)
705 = NAND(637, 687)
706 = NAND(690, 691)
709 = NAND(692, 693)
712 = NAND(694, 695)
715 = NAND(696, 697)
718 = NAND(698, 699)
721 = NAND(700, 701)
724 = NAND(702, 703)
727 = NAND(704, 705)
730 = NAND(242, 718)
733 = NAND(245, 721)
736 = NAND(248, 724)
739 = NAND(251, 727)
742 = NAND(254, 706)
745 = NAND(257, 709)
748 = NAND(260, 712)
751 = NAND(263, 715)
754 = NAND(242, 730)
755 = NAND(718, 730)
756 = NAND(245, 733)
757 = NAND(721, 733)
758 = NAND(248, 736)
759 = NAND(724, 736)
760 = NAND(251, 739)
761 = NAND(727, 739)
762 = NAND(254, 742)
763 = NAND(706, 742)
764 = NAND(257, 745)
765 = NAND(709, 745)
766 = NAND(260, 748)
767 = NAND(712, 748)
768 = NAND(263, 751)
769 = NAND(715, 751)
770 = NAND(754, 755)
773 = NAND(756, 757)
776 = NAND(758, 759)
779 = NAND(760, 761)
782 = NAND(762, 763)
785 = NAND(764, 765)
788 = NAND(766, 767)
791 = NAND(768, 769)
794 = NAND(642, 770)
797 = NAND(645, 773)
800 = NAND(648, 776)
803 = NAND(651, 779)
806 = NAND(654, 782)
809 = NAND(657, 785)
812 = NAND(660, 788)
815 = NAND(663, 791)
818 = NAND(642, 794)
819 = NAND(770, 794)
820 = NAND(645, 797)
821 = NAND(773, 797)
822 = NAND(648, 800)
823 = NAND(776, 800)
824 = NAND(651, 803)
825 = NAND(779, 803)
826 = NAND(654, 806)
827 = NAND(782, 806)
828 = NAND(657, 809)
829 = NAND(785, 809)
830 = NAND(660, 812)
831 = NAND(788, 812)
832 = NAND(663, 815)
833 = NAND(791, 815)
834 = NAND(818, 819)
847 = NAND(820, 821)
860 = NAND(822, 823)
873 = NAND(824, 825)
886 = NAND(828, 829)
899 = NAND(832, 833)
912 = NAND(830, 831)
925 = NAND(826, 827)
938 = NOT(834)
939 = NOT(847)
940 = NOT(860)
941 = NOT(834)
942 = NOT(847)
943 = NOT(873)
944 = NOT(834)
945 = NOT(860)
946 = NOT(873)
947 = NOT(847)
948 = NOT(860)
949 = NOT(873)
950 = NOT(886)
951 = NOT(899)
952 = NOT(886)
953 = NOT(912)
954 = NOT(925)
955 = NOT(899)
956 = NOT(925)
957 = NOT(912)
958 = NOT(925)
959 = NOT(886)
960 = NOT(912)
961 = NOT(925)
962 = NOT(886)
963 = NOT(899)
964 = NOT(925)
965 = NOT(912)
966 = NOT(899)
967 = NOT(886)
968 = NOT(912)
969 = NOT(899)
970 = NOT(847)
971 = NOT(873)
972 = NOT(847)
973 = NOT(860)
974 = NOT(834)
975 = NOT(873)
976 = NOT(834)
977 = NOT(860)
978 = AND(938, 939, 940, 873)
979 = AND(941, 942, 860, 943)
980 = AND(944, 847, 945, 946)
981 = AND(834, 947, 948, 949)
982 = AND(958, 959, 960, 899)
983 = AND(961, 962, 912, 963)
984 = AND(964, 886, 965, 966)
985 = AND(925, 967, 968, 969)
986 = OR(978, 979, 980, 981)
991 = OR(982, 983, 984, 985)
996 = AND(925, 950, 912, 951, 986)
1001 = AND(925, 952, 953, 899, 986)
1006 = AND(954, 886, 912, 955, 986)
1011 = AND(956, 886, 957, 899, 986)
1016 = AND(834, 970, 860, 971, 991)
1021 = AND(834, 972, 973, 873, 991)
1026 = AND(974, 847, 860, 975, 991)
1031 = AND(976, 847, 977, 873, 991)
1036 = AND(834, 996)
1039 = AND(847, 996)
1042 = AND(860, 996)
1045 = AND(873, 996)
1048 = AND(834, 1001)
1051 = AND(847, 1001)
1054 = AND(860, 1001)
1057 = AND(873, 1001)
1060 = AND(834, 1006)
1063 = AND(847, 1006)
1066 = AND(860, 1006)
1069 = AND(873, 1006)
1072 = AND(834, 1011)
1075 = AND(847, 1011)
1078 = AND(860, 1011)
1081 = AND(873, 1011)
1084 = AND(925, 1016)
1087 = AND(886, 1016)
1090 = AND(912, 1016)
1093 = AND(899, 1016)
1096 = AND(925, 1021)
1099 = AND(886, 1021)
1102 = AND(912, 1021)
1105 = AND(899, 1021)
1108 = AND(925, 1026)
1111 = AND(886, 1026)
1114 = AND(912, 1026)
1117 = AND(899, 1026)
1120 = AND(925, 1031)
1123 = AND(886, 1031)
1126 = AND(912, 1031)
1129 = AND(899, 1031)
1132 = NAND(1, 1036)
1135 = NAND(8, 1039)
1138 = NAND(15, 1042)
1141 = NAND(22, 1045)
1144 = NAND(29, 1048)
1147 = NAND(36, 1051)
1150 = NAND(43, 1054)
1153 = NAND(50, 1057)
1156 = NAND(57, 1060)
1159 = NAND(64, 1063)
1162 = NAND(71, 1066)
1165 = NAND(78, 1069)
1168 = NAND(85, 1072)
1171 = NAND(92, 1075)
1174 = NAND(99, 1078)
1177 = NAND(106, 1081)
1180 = NAND(113, 1084)
1183 = NAND(120, 1087)
1186 = NAND(127, 1090)
1189 = NAND(134, 1093)
1192 = NAND(141, 1096)
1195 = NAND(148, 1099)
1198 = NAND(155, 1102)
1201 = NAND(162, 1105)
1204 = NAND(169, 1108)
1207 = NAND(176, 1111)
1210 = NAND(183, 1114)
1213 = NAND(190, 1117)
1216 = NAND(197, 1120)
1219 = NAND(204, 1123)
1222 = NAND(211, 1126)
1225 = NAND(218, 1129)
1228 = NAND(1, 1132)
1229 = NAND(1036, 1132)
1230 = NAND(8, 1135)
1231 = NAND(1039, 1135)
1232 = NAND(15, 1138)
1233 = NAND(1042, 1138)
1234 = NAND(22, 1141)
1235 = NAND(1045, 1141)
1236 = NAND(29, 1144)
1237 = NAND(1048, 1144)
1238 = NAND(36, 1147)
1239 = NAND(1051, 1147)
1240 = NAND(43, 1150)
1241 = NAND(1054, 1150)
1242 = NAND(50, 1153)
1243 = NAND(1057, 1153)
1244 = NAND(57, 1156)
1245 = NAND(1060, 1156)
1246 = NAND(64, 1159)
1247 = NAND(1063, 1159)
1248 = NAND(71, 1162)
1249 = NAND(1066, 1162)
1250 = NAND(78, 1165)
1251 = NAND(1069, 1165)
1252 = NAND(85, 1168)
1253 = NAND(1072, 1168)
1254 = NAND(92, 1171)
1255 = NAND(1075, 1171)
1256 = NAND(99, 1174)
1257 = NAND(1078, 1174)
1258 = NAND(106, 1177)
1259 = NAND(1081, 1177)
1260 = NAND(113, 1180)
1261 = NAND(1084, 1180)
1262 = NAND(120, 1183)
1263 = NAND(1087, 1183)
1264 = NAND(127, 1186)
1265 = NAND(1090, 1186)
1266 = NAND(134, 1189)
1267 = NAND(1093, 1189)
1268 = NAND(141, 1192)
1269 = NAND(1096, 1192)
1270 = NAND(148, 1195)
1271 = NAND(1099, 1195)
1272 = NAND(155, 1198)
1273 = NAND(1102, 1198)
1274 = NAND(162, 1201)
1275 = NAND(1105, 1201)
1276 = NAND(169, 1204)
1277 = NAND(1108, 1204)
1278 = NAND(176, 1207)
1279 = NAND(1111, 1207)
1280 = NAND(183, 1210)
1281 = NAND(1114, 1210)
1282 = NAND(190, 1213)
1283 = NAND(1117, 1213)
1284 = NAND(197, 1216)
1285 = NAND(1120, 1216)
1286 = NAND(204, 1219)
1287 = NAND(1123, 1219)
1288 = NAND(211, 1222)
1289 = NAND(1126, 1222)
1290 = NAND(218, 1225)
1291 = NAND(1129, 1225)
1292 = NAND(1228, 1229)
1293 = NAND(1230, 1231)
1294 = NAND(1232, 1233)
1295 = NAND(1234, 1235)
1296 = NAND(1236, 1237)
1297 = NAND(1238, 1239)
1298 = NAND(1240, 1241)
1299 = NAND(1242, 1243)
1300 = NAND(1244, 1245)
1301 = NAND(1246, 1247)
1302 = NAND(1248, 1249)
1303 = NAND(1250, 1251)
1304 = NAND(1252, 1253)
1305 = NAND(1254, 1255)
1306 = NAND(1256, 1257)
1307 = NAND(1258, 1259)
1308 = NAND(1260, 1261)
1309 = NAND(1262, 1263)
1310 = NAND(1264, 1265)
1311 = NAND(1266, 1267)
1312 = NAND(1268, 1269)
1313 = NAND(1270, 1271)
1314 = NAND(1272, 1273)
1315 = NAND(1274, 1275)
1316 = NAND(1276, 1277)
1317 = NAND(1278, 1279)
1318 = NAND(1280, 1281)
1319 = NAND(1282, 1283)
1320 = NAND(1284, 1285)
1321 = NAND(1286, 1287)
1322 = NAND(1288, 1289)
1323 = NAND(1290, 1291)
1324 = BUFF(1292)
1325 = BUFF(1293)
1326 = BUFF(1294)
1327 = BUFF(1295)
1328 = BUFF(1296)
1329 = BUFF(1297)
1330 = BUFF(1298)
1331 = BUFF(1299)
1332 = BUFF(1300)
1333 = BUFF(1301)
1334 = BUFF(1302)
1335 = BUFF(1303)
1336 = BUFF(1304)
1337 = BUFF(1305)
1338 = BUFF(1306)
1339 = BUFF(1307)
1340 = BUFF(1308)
1341 = BUFF(1309)
1342 = BUFF(1310)
1343 = BUFF(1311)
1344 = BUFF(1312)
1345 = BUFF(1313)
1346 = BUFF(1314)
1347 = BUFF(1315)
1348 = BUFF(1316)
1349 = BUFF(1317)
1350 = BUFF(1318)
1351 = BUFF(1319)
1352 = BUFF(1320)
1353 = BUFF(1321)
1354 = BUFF(1322)
1355 = BUFF(1323)

942
bench_test/c1908.bench
View File

@ -1,942 +0,0 @@
# c1908
INPUT(1)
INPUT(4)
INPUT(7)
INPUT(10)
INPUT(13)
INPUT(16)
INPUT(19)
INPUT(22)
INPUT(25)
INPUT(28)
INPUT(31)
INPUT(34)
INPUT(37)
INPUT(40)
INPUT(43)
INPUT(46)
INPUT(49)
INPUT(53)
INPUT(56)
INPUT(60)
INPUT(63)
INPUT(66)
INPUT(69)
INPUT(72)
INPUT(76)
INPUT(79)
INPUT(82)
INPUT(85)
INPUT(88)
INPUT(91)
INPUT(94)
INPUT(99)
INPUT(104)
OUTPUT(2753)
OUTPUT(2754)
OUTPUT(2755)
OUTPUT(2756)
OUTPUT(2762)
OUTPUT(2767)
OUTPUT(2768)
OUTPUT(2779)
OUTPUT(2780)
OUTPUT(2781)
OUTPUT(2782)
OUTPUT(2783)
OUTPUT(2784)
OUTPUT(2785)
OUTPUT(2786)
OUTPUT(2787)
OUTPUT(2811)
OUTPUT(2886)
OUTPUT(2887)
OUTPUT(2888)
OUTPUT(2889)
OUTPUT(2890)
OUTPUT(2891)
OUTPUT(2892)
OUTPUT(2899)
190 = NOT(1)
194 = NOT(4)
197 = NOT(7)
201 = NOT(10)
206 = NOT(13)
209 = NOT(16)
212 = NOT(19)
216 = NOT(22)
220 = NOT(25)
225 = NOT(28)
229 = NOT(31)
232 = NOT(34)
235 = NOT(37)
239 = NOT(40)
243 = NOT(43)
247 = NOT(46)
251 = NAND(63, 88)
252 = NAND(66, 91)
253 = NOT(72)
256 = NOT(72)
257 = BUFF(69)
260 = BUFF(69)
263 = NOT(76)
266 = NOT(79)
269 = NOT(82)
272 = NOT(85)
275 = NOT(104)
276 = NOT(104)
277 = NOT(88)
280 = NOT(91)
283 = BUFF(94)
290 = NOT(94)
297 = BUFF(94)
300 = NOT(94)
303 = BUFF(99)
306 = NOT(99)
313 = NOT(99)
316 = BUFF(104)
319 = NOT(104)
326 = BUFF(104)
331 = BUFF(104)
338 = NOT(104)
343 = BUFF(1)
346 = BUFF(4)
349 = BUFF(7)
352 = BUFF(10)
355 = BUFF(13)
358 = BUFF(16)
361 = BUFF(19)
364 = BUFF(22)
367 = BUFF(25)
370 = BUFF(28)
373 = BUFF(31)
376 = BUFF(34)
379 = BUFF(37)
382 = BUFF(40)
385 = BUFF(43)
388 = BUFF(46)
534 = NOT(343)
535 = NOT(346)
536 = NOT(349)
537 = NOT(352)
538 = NOT(355)
539 = NOT(358)
540 = NOT(361)
541 = NOT(364)
542 = NOT(367)
543 = NOT(370)
544 = NOT(373)
545 = NOT(376)
546 = NOT(379)
547 = NOT(382)
548 = NOT(385)
549 = NOT(388)
550 = NAND(306, 331)
551 = NAND(306, 331)
552 = NAND(306, 331)
553 = NAND(306, 331)
554 = NAND(306, 331)
555 = NAND(306, 331)
556 = BUFF(190)
559 = BUFF(194)
562 = BUFF(206)
565 = BUFF(209)
568 = BUFF(225)
571 = BUFF(243)
574 = AND(63, 319)
577 = BUFF(220)
580 = BUFF(229)
583 = BUFF(232)
586 = AND(66, 319)
589 = BUFF(239)
592 = AND(49, 253, 319)
595 = BUFF(247)
598 = BUFF(239)
601 = NAND(326, 277)
602 = NAND(326, 280)
603 = NAND(260, 72)
608 = NAND(260, 300)
612 = NAND(256, 300)
616 = BUFF(201)
619 = BUFF(216)
622 = BUFF(220)
625 = BUFF(239)
628 = BUFF(190)
631 = BUFF(190)
634 = BUFF(194)
637 = BUFF(229)
640 = BUFF(197)
643 = AND(56, 257, 319)
646 = BUFF(232)
649 = BUFF(201)
652 = BUFF(235)
655 = AND(60, 257, 319)
658 = BUFF(263)
661 = BUFF(263)
664 = BUFF(266)
667 = BUFF(266)
670 = BUFF(269)
673 = BUFF(269)
676 = BUFF(272)
679 = BUFF(272)
682 = AND(251, 316)
685 = AND(252, 316)
688 = BUFF(197)
691 = BUFF(197)
694 = BUFF(212)
697 = BUFF(212)
700 = BUFF(247)
703 = BUFF(247)
706 = BUFF(235)
709 = BUFF(235)
712 = BUFF(201)
715 = BUFF(201)
718 = BUFF(206)
721 = BUFF(216)
724 = AND(53, 253, 319)
727 = BUFF(243)
730 = BUFF(220)
733 = BUFF(220)
736 = BUFF(209)
739 = BUFF(216)
742 = BUFF(225)
745 = BUFF(243)
748 = BUFF(212)
751 = BUFF(225)
886 = NOT(682)
887 = NOT(685)
888 = NOT(616)
889 = NOT(619)
890 = NOT(622)
891 = NOT(625)
892 = NOT(631)
893 = NOT(643)
894 = NOT(649)
895 = NOT(652)
896 = NOT(655)
897 = AND(49, 612)
898 = AND(56, 608)
899 = NAND(53, 612)
903 = NAND(60, 608)
907 = NAND(49, 612)
910 = NAND(56, 608)
913 = NOT(661)
914 = NOT(658)
915 = NOT(667)
916 = NOT(664)
917 = NOT(673)
918 = NOT(670)
919 = NOT(679)
920 = NOT(676)
921 = NAND(277, 297, 326, 603)
922 = NAND(280, 297, 326, 603)
923 = NAND(303, 338, 603)
926 = AND(303, 338, 603)
935 = BUFF(556)
938 = NOT(688)
939 = BUFF(556)
942 = NOT(691)
943 = BUFF(562)
946 = NOT(694)
947 = BUFF(562)
950 = NOT(697)
951 = BUFF(568)
954 = NOT(700)
955 = BUFF(568)
958 = NOT(703)
959 = BUFF(574)
962 = BUFF(574)
965 = BUFF(580)
968 = NOT(706)
969 = BUFF(580)
972 = NOT(709)
973 = BUFF(586)
976 = NOT(712)
977 = BUFF(586)
980 = NOT(715)
981 = BUFF(592)
984 = NOT(628)
985 = BUFF(592)
988 = NOT(718)
989 = NOT(721)
990 = NOT(634)
991 = NOT(724)
992 = NOT(727)
993 = NOT(637)
994 = BUFF(595)
997 = NOT(730)
998 = BUFF(595)
1001 = NOT(733)
1002 = NOT(736)
1003 = NOT(739)
1004 = NOT(640)
1005 = NOT(742)
1006 = NOT(745)
1007 = NOT(646)
1008 = NOT(748)
1009 = NOT(751)
1010 = BUFF(559)
1013 = BUFF(559)
1016 = BUFF(565)
1019 = BUFF(565)
1022 = BUFF(571)
1025 = BUFF(571)
1028 = BUFF(577)
1031 = BUFF(577)
1034 = BUFF(583)
1037 = BUFF(583)
1040 = BUFF(589)
1043 = BUFF(589)
1046 = BUFF(598)
1049 = BUFF(598)
1054 = NAND(619, 888)
1055 = NAND(616, 889)
1063 = NAND(625, 890)
1064 = NAND(622, 891)
1067 = NAND(655, 895)
1068 = NAND(652, 896)
1119 = NAND(721, 988)
1120 = NAND(718, 989)
1121 = NAND(727, 991)
1122 = NAND(724, 992)
1128 = NAND(739, 1002)
1129 = NAND(736, 1003)
1130 = NAND(745, 1005)
1131 = NAND(742, 1006)
1132 = NAND(751, 1008)
1133 = NAND(748, 1009)
1148 = NOT(939)
1149 = NOT(935)
1150 = NAND(1054, 1055)
1151 = NOT(943)
1152 = NOT(947)
1153 = NOT(955)
1154 = NOT(951)
1155 = NOT(962)
1156 = NOT(969)
1157 = NOT(977)
1158 = NAND(1063, 1064)
1159 = NOT(985)
1160 = NAND(985, 892)
1161 = NOT(998)
1162 = NAND(1067, 1068)
1163 = NOT(899)
1164 = BUFF(899)
1167 = NOT(903)
1168 = BUFF(903)
1171 = NAND(921, 923)
1188 = NAND(922, 923)
1205 = NOT(1010)
1206 = NAND(1010, 938)
1207 = NOT(1013)
1208 = NAND(1013, 942)
1209 = NOT(1016)
1210 = NAND(1016, 946)
1211 = NOT(1019)
1212 = NAND(1019, 950)
1213 = NOT(1022)
1214 = NAND(1022, 954)
1215 = NOT(1025)
1216 = NAND(1025, 958)
1217 = NOT(1028)
1218 = NOT(959)
1219 = NOT(1031)
1220 = NOT(1034)
1221 = NAND(1034, 968)
1222 = NOT(965)
1223 = NOT(1037)
1224 = NAND(1037, 972)
1225 = NOT(1040)
1226 = NAND(1040, 976)
1227 = NOT(973)
1228 = NOT(1043)
1229 = NAND(1043, 980)
1230 = NOT(981)
1231 = NAND(981, 984)
1232 = NAND(1119, 1120)
1235 = NAND(1121, 1122)
1238 = NOT(1046)
1239 = NAND(1046, 997)
1240 = NOT(994)
1241 = NOT(1049)
1242 = NAND(1049, 1001)
1243 = NAND(1128, 1129)
1246 = NAND(1130, 1131)
1249 = NAND(1132, 1133)
1252 = BUFF(907)
1255 = BUFF(907)
1258 = BUFF(910)
1261 = BUFF(910)
1264 = NOT(1150)
1267 = NAND(631, 1159)
1309 = NAND(688, 1205)
1310 = NAND(691, 1207)
1311 = NAND(694, 1209)
1312 = NAND(697, 1211)
1313 = NAND(700, 1213)
1314 = NAND(703, 1215)
1315 = NAND(706, 1220)
1316 = NAND(709, 1223)
1317 = NAND(712, 1225)
1318 = NAND(715, 1228)
1319 = NOT(1158)
1322 = NAND(628, 1230)
1327 = NAND(730, 1238)
1328 = NAND(733, 1241)
1334 = NOT(1162)
1344 = NAND(1267, 1160)
1345 = NAND(1249, 894)
1346 = NOT(1249)
1348 = NOT(1255)
1349 = NOT(1252)
1350 = NOT(1261)
1351 = NOT(1258)
1352 = NAND(1309, 1206)
1355 = NAND(1310, 1208)
1358 = NAND(1311, 1210)
1361 = NAND(1312, 1212)
1364 = NAND(1313, 1214)
1367 = NAND(1314, 1216)
1370 = NAND(1315, 1221)
1373 = NAND(1316, 1224)
1376 = NAND(1317, 1226)
1379 = NAND(1318, 1229)
1383 = NAND(1322, 1231)
1386 = NOT(1232)
1387 = NAND(1232, 990)
1388 = NOT(1235)
1389 = NAND(1235, 993)
1390 = NAND(1327, 1239)
1393 = NAND(1328, 1242)
1396 = NOT(1243)
1397 = NAND(1243, 1004)
1398 = NOT(1246)
1399 = NAND(1246, 1007)
1409 = NOT(1319)
1412 = NAND(649, 1346)
1413 = NOT(1334)
1416 = BUFF(1264)
1419 = BUFF(1264)
1433 = NAND(634, 1386)
1434 = NAND(637, 1388)
1438 = NAND(640, 1396)
1439 = NAND(646, 1398)
1440 = NOT(1344)
1443 = NAND(1355, 1148)
1444 = NOT(1355)
1445 = NAND(1352, 1149)
1446 = NOT(1352)
1447 = NAND(1358, 1151)
1448 = NOT(1358)
1451 = NAND(1361, 1152)
1452 = NOT(1361)
1453 = NAND(1367, 1153)
1454 = NOT(1367)
1455 = NAND(1364, 1154)
1456 = NOT(1364)
1457 = NAND(1373, 1156)
1458 = NOT(1373)
1459 = NAND(1379, 1157)
1460 = NOT(1379)
1461 = NOT(1383)
1462 = NAND(1393, 1161)
1463 = NOT(1393)
1464 = NAND(1345, 1412)
1468 = NOT(1370)
1469 = NAND(1370, 1222)
1470 = NOT(1376)
1471 = NAND(1376, 1227)
1472 = NAND(1387, 1433)
1475 = NOT(1390)
1476 = NAND(1390, 1240)
1478 = NAND(1389, 1434)
1481 = NAND(1399, 1439)
1484 = NAND(1397, 1438)
1487 = NAND(939, 1444)
1488 = NAND(935, 1446)
1489 = NAND(943, 1448)
1490 = NOT(1419)
1491 = NOT(1416)
1492 = NAND(947, 1452)
1493 = NAND(955, 1454)
1494 = NAND(951, 1456)
1495 = NAND(969, 1458)
1496 = NAND(977, 1460)
1498 = NAND(998, 1463)
1499 = NOT(1440)
1500 = NAND(965, 1468)
1501 = NAND(973, 1470)
1504 = NAND(994, 1475)
1510 = NOT(1464)
1513 = NAND(1443, 1487)
1514 = NAND(1445, 1488)
1517 = NAND(1447, 1489)
1520 = NAND(1451, 1492)
1521 = NAND(1453, 1493)
1522 = NAND(1455, 1494)
1526 = NAND(1457, 1495)
1527 = NAND(1459, 1496)
1528 = NOT(1472)
1529 = NAND(1462, 1498)
1530 = NOT(1478)
1531 = NOT(1481)
1532 = NOT(1484)
1534 = NAND(1471, 1501)
1537 = NAND(1469, 1500)
1540 = NAND(1476, 1504)
1546 = NOT(1513)
1554 = NOT(1521)
1557 = NOT(1526)
1561 = NOT(1520)
1567 = NAND(1484, 1531)
1568 = NAND(1481, 1532)
1569 = NOT(1510)
1571 = NOT(1527)
1576 = NOT(1529)
1588 = BUFF(1522)
1591 = NOT(1534)
1593 = NOT(1537)
1594 = NAND(1540, 1530)
1595 = NOT(1540)
1596 = NAND(1567, 1568)
1600 = BUFF(1517)
1603 = BUFF(1517)
1606 = BUFF(1522)
1609 = BUFF(1522)
1612 = BUFF(1514)
1615 = BUFF(1514)
1620 = BUFF(1557)
1623 = BUFF(1554)
1635 = NOT(1571)
1636 = NAND(1478, 1595)
1638 = NAND(1576, 1569)
1639 = NOT(1576)
1640 = BUFF(1561)
1643 = BUFF(1561)
1647 = BUFF(1546)
1651 = BUFF(1546)
1658 = BUFF(1554)
1661 = BUFF(1557)
1664 = BUFF(1557)
1671 = NAND(1596, 893)
1672 = NOT(1596)
1675 = NOT(1600)
1677 = NOT(1603)
1678 = NAND(1606, 1217)
1679 = NOT(1606)
1680 = NAND(1609, 1219)
1681 = NOT(1609)
1682 = NOT(1612)
1683 = NOT(1615)
1685 = NAND(1594, 1636)
1688 = NAND(1510, 1639)
1697 = BUFF(1588)
1701 = BUFF(1588)
1706 = NAND(643, 1672)
1707 = NOT(1643)
1708 = NAND(1647, 1675)
1709 = NOT(1647)
1710 = NAND(1651, 1677)
1711 = NOT(1651)
1712 = NAND(1028, 1679)
1713 = NAND(1031, 1681)
1714 = BUFF(1620)
1717 = BUFF(1620)
1720 = NAND(1658, 1593)
1721 = NOT(1658)
1723 = NAND(1638, 1688)
1727 = NOT(1661)
1728 = NOT(1640)
1730 = NOT(1664)
1731 = BUFF(1623)
1734 = BUFF(1623)
1740 = NAND(1685, 1528)
1741 = NOT(1685)
1742 = NAND(1671, 1706)
1746 = NAND(1600, 1709)
1747 = NAND(1603, 1711)
1748 = NAND(1678, 1712)
1751 = NAND(1680, 1713)
1759 = NAND(1537, 1721)
1761 = NOT(1697)
1762 = NAND(1697, 1727)
1763 = NOT(1701)
1764 = NAND(1701, 1730)
1768 = NOT(1717)
1769 = NAND(1472, 1741)
1772 = NAND(1723, 1413)
1773 = NOT(1723)
1774 = NAND(1708, 1746)
1777 = NAND(1710, 1747)
1783 = NOT(1731)
1784 = NAND(1731, 1682)
1785 = NOT(1714)
1786 = NOT(1734)
1787 = NAND(1734, 1683)
1788 = NAND(1720, 1759)
1791 = NAND(1661, 1761)
1792 = NAND(1664, 1763)
1795 = NAND(1751, 1155)
1796 = NOT(1751)
1798 = NAND(1740, 1769)
1801 = NAND(1334, 1773)
1802 = NAND(1742, 290)
1807 = NOT(1748)
1808 = NAND(1748, 1218)
1809 = NAND(1612, 1783)
1810 = NAND(1615, 1786)
1812 = NAND(1791, 1762)
1815 = NAND(1792, 1764)
1818 = BUFF(1742)
1821 = NAND(1777, 1490)
1822 = NOT(1777)
1823 = NAND(1774, 1491)
1824 = NOT(1774)
1825 = NAND(962, 1796)
1826 = NAND(1788, 1409)
1827 = NOT(1788)
1830 = NAND(1772, 1801)
1837 = NAND(959, 1807)
1838 = NAND(1809, 1784)
1841 = NAND(1810, 1787)
1848 = NAND(1419, 1822)
1849 = NAND(1416, 1824)
1850 = NAND(1795, 1825)
1852 = NAND(1319, 1827)
1855 = NAND(1815, 1707)
1856 = NOT(1815)
1857 = NOT(1818)
1858 = NAND(1798, 290)
1864 = NOT(1812)
1865 = NAND(1812, 1728)
1866 = BUFF(1798)
1869 = BUFF(1802)
1872 = BUFF(1802)
1875 = NAND(1808, 1837)
1878 = NAND(1821, 1848)
1879 = NAND(1823, 1849)
1882 = NAND(1841, 1768)
1883 = NOT(1841)
1884 = NAND(1826, 1852)
1885 = NAND(1643, 1856)
1889 = NAND(1830, 290)
1895 = NOT(1838)
1896 = NAND(1838, 1785)
1897 = NAND(1640, 1864)
1898 = NOT(1850)
1902 = BUFF(1830)
1910 = NOT(1878)
1911 = NAND(1717, 1883)
1912 = NOT(1884)
1913 = NAND(1855, 1885)
1915 = NOT(1866)
1919 = NAND(1872, 919)
1920 = NOT(1872)
1921 = NAND(1869, 920)
1922 = NOT(1869)
1923 = NOT(1875)
1924 = NAND(1714, 1895)
1927 = BUFF(1858)
1930 = BUFF(1858)
1933 = NAND(1865, 1897)
1936 = NAND(1882, 1911)
1937 = NOT(1898)
1938 = NOT(1902)
1941 = NAND(679, 1920)
1942 = NAND(676, 1922)
1944 = BUFF(1879)
1947 = NOT(1913)
1950 = BUFF(1889)
1953 = BUFF(1889)
1958 = BUFF(1879)
1961 = NAND(1896, 1924)
1965 = AND(1910, 601)
1968 = AND(602, 1912)
1975 = NAND(1930, 917)
1976 = NOT(1930)
1977 = NAND(1927, 918)
1978 = NOT(1927)
1979 = NAND(1919, 1941)
1980 = NAND(1921, 1942)
1985 = NOT(1933)
1987 = NOT(1936)
1999 = NOT(1944)
2000 = NAND(1944, 1937)
2002 = NOT(1947)
2003 = NAND(1947, 1499)
2004 = NAND(1953, 1350)
2005 = NOT(1953)
2006 = NAND(1950, 1351)
2007 = NOT(1950)
2008 = NAND(673, 1976)
2009 = NAND(670, 1978)
2012 = NOT(1979)
2013 = NOT(1958)
2014 = NAND(1958, 1923)
2015 = NOT(1961)
2016 = NAND(1961, 1635)
2018 = NOT(1965)
2019 = NOT(1968)
2020 = NAND(1898, 1999)
2021 = NOT(1987)
2022 = NAND(1987, 1591)
2023 = NAND(1440, 2002)
2024 = NAND(1261, 2005)
2025 = NAND(1258, 2007)
2026 = NAND(1975, 2008)
2027 = NAND(1977, 2009)
2030 = NOT(1980)
2033 = BUFF(1980)
2036 = NAND(1875, 2013)
2037 = NAND(1571, 2015)
2038 = NAND(2020, 2000)
2039 = NAND(1534, 2021)
2040 = NAND(2023, 2003)
2041 = NAND(2004, 2024)
2042 = NAND(2006, 2025)
2047 = NOT(2026)
2052 = NAND(2036, 2014)
2055 = NAND(2037, 2016)
2060 = NOT(2038)
2061 = NAND(2039, 2022)
2062 = NAND(2040, 290)
2067 = NOT(2041)
2068 = NOT(2027)
2071 = BUFF(2027)
2076 = NOT(2052)
2077 = NOT(2055)
2078 = NAND(2060, 290)
2081 = NAND(2061, 290)
2086 = NOT(2042)
2089 = BUFF(2042)
2104 = AND(2030, 2068)
2119 = AND(2033, 2068)
2129 = AND(2030, 2071)
2143 = AND(2033, 2071)
2148 = BUFF(2062)
2151 = BUFF(2062)
2196 = BUFF(2078)
2199 = BUFF(2078)
2202 = BUFF(2081)
2205 = BUFF(2081)
2214 = NAND(2151, 915)
2215 = NOT(2151)
2216 = NAND(2148, 916)
2217 = NOT(2148)
2222 = NAND(2199, 1348)
2223 = NOT(2199)
2224 = NAND(2196, 1349)
2225 = NOT(2196)
2226 = NAND(2205, 913)
2227 = NOT(2205)
2228 = NAND(2202, 914)
2229 = NOT(2202)
2230 = NAND(667, 2215)
2231 = NAND(664, 2217)
2232 = NAND(1255, 2223)
2233 = NAND(1252, 2225)
2234 = NAND(661, 2227)
2235 = NAND(658, 2229)
2236 = NAND(2214, 2230)
2237 = NAND(2216, 2231)
2240 = NAND(2222, 2232)
2241 = NAND(2224, 2233)
2244 = NAND(2226, 2234)
2245 = NAND(2228, 2235)
2250 = NOT(2236)
2253 = NOT(2240)
2256 = NOT(2244)
2257 = NOT(2237)
2260 = BUFF(2237)
2263 = NOT(2241)
2266 = AND(1164, 2241)
2269 = NOT(2245)
2272 = AND(1168, 2245)
2279 = NAND(2067, 2012, 2047, 2250, 899, 2256, 2253, 903)
2286 = BUFF(2266)
2297 = BUFF(2266)
2315 = BUFF(2272)
2326 = BUFF(2272)
2340 = AND(2086, 2257)
2353 = AND(2089, 2257)
2361 = AND(2086, 2260)
2375 = AND(2089, 2260)
2384 = AND(338, 2279, 313, 313)
2385 = AND(1163, 2263)
2386 = AND(1164, 2263)
2426 = AND(1167, 2269)
2427 = AND(1168, 2269)
2537 = NAND(2286, 2315, 2361, 2104, 1171)
2540 = NAND(2286, 2315, 2340, 2129, 1171)
2543 = NAND(2286, 2315, 2340, 2119, 1171)
2546 = NAND(2286, 2315, 2353, 2104, 1171)
2549 = NAND(2297, 2315, 2375, 2119, 1188)
2552 = NAND(2297, 2326, 2361, 2143, 1188)
2555 = NAND(2297, 2326, 2375, 2129, 1188)
2558 = AND(2286, 2315, 2361, 2104, 1171)
2561 = AND(2286, 2315, 2340, 2129, 1171)
2564 = AND(2286, 2315, 2340, 2119, 1171)
2567 = AND(2286, 2315, 2353, 2104, 1171)
2570 = AND(2297, 2315, 2375, 2119, 1188)
2573 = AND(2297, 2326, 2361, 2143, 1188)
2576 = AND(2297, 2326, 2375, 2129, 1188)
2594 = NAND(2286, 2427, 2361, 2129, 1171)
2597 = NAND(2297, 2427, 2361, 2119, 1171)
2600 = NAND(2297, 2427, 2375, 2104, 1171)
2603 = NAND(2297, 2427, 2340, 2143, 1171)
2606 = NAND(2297, 2427, 2353, 2129, 1188)
2611 = NAND(2386, 2326, 2361, 2129, 1188)
2614 = NAND(2386, 2326, 2361, 2119, 1188)
2617 = NAND(2386, 2326, 2375, 2104, 1188)
2620 = NAND(2386, 2326, 2353, 2129, 1188)
2627 = NAND(2297, 2427, 2340, 2104, 926)
2628 = NAND(2386, 2326, 2340, 2104, 926)
2629 = NAND(2386, 2427, 2361, 2104, 926)
2630 = NAND(2386, 2427, 2340, 2129, 926)
2631 = NAND(2386, 2427, 2340, 2119, 926)
2632 = NAND(2386, 2427, 2353, 2104, 926)
2633 = NAND(2386, 2426, 2340, 2104, 926)
2634 = NAND(2385, 2427, 2340, 2104, 926)
2639 = AND(2286, 2427, 2361, 2129, 1171)
2642 = AND(2297, 2427, 2361, 2119, 1171)
2645 = AND(2297, 2427, 2375, 2104, 1171)
2648 = AND(2297, 2427, 2340, 2143, 1171)
2651 = AND(2297, 2427, 2353, 2129, 1188)
2655 = AND(2386, 2326, 2361, 2129, 1188)
2658 = AND(2386, 2326, 2361, 2119, 1188)
2661 = AND(2386, 2326, 2375, 2104, 1188)
2664 = AND(2386, 2326, 2353, 2129, 1188)
2669 = NAND(2558, 534)
2670 = NOT(2558)
2671 = NAND(2561, 535)
2672 = NOT(2561)
2673 = NAND(2564, 536)
2674 = NOT(2564)
2675 = NAND(2567, 537)
2676 = NOT(2567)
2682 = NAND(2570, 543)
2683 = NOT(2570)
2688 = NAND(2573, 548)
2689 = NOT(2573)
2690 = NAND(2576, 549)
2691 = NOT(2576)
2710 = AND(2627, 2628, 2629, 2630, 2631, 2632, 2633, 2634)
2720 = NAND(343, 2670)
2721 = NAND(346, 2672)
2722 = NAND(349, 2674)
2723 = NAND(352, 2676)
2724 = NAND(2639, 538)
2725 = NOT(2639)
2726 = NAND(2642, 539)
2727 = NOT(2642)
2728 = NAND(2645, 540)
2729 = NOT(2645)
2730 = NAND(2648, 541)
2731 = NOT(2648)
2732 = NAND(2651, 542)
2733 = NOT(2651)
2734 = NAND(370, 2683)
2735 = NAND(2655, 544)
2736 = NOT(2655)
2737 = NAND(2658, 545)
2738 = NOT(2658)
2739 = NAND(2661, 546)
2740 = NOT(2661)
2741 = NAND(2664, 547)
2742 = NOT(2664)
2743 = NAND(385, 2689)
2744 = NAND(388, 2691)
2745 = NAND(2537, 2540, 2543, 2546, 2594, 2597, 2600, 2603)
2746 = NAND(2606, 2549, 2611, 2614, 2617, 2620, 2552, 2555)
2747 = AND(2537, 2540, 2543, 2546, 2594, 2597, 2600, 2603)
2750 = AND(2606, 2549, 2611, 2614, 2617, 2620, 2552, 2555)
2753 = NAND(2669, 2720)
2754 = NAND(2671, 2721)
2755 = NAND(2673, 2722)
2756 = NAND(2675, 2723)
2757 = NAND(355, 2725)
2758 = NAND(358, 2727)
2759 = NAND(361, 2729)
2760 = NAND(364, 2731)
2761 = NAND(367, 2733)
2762 = NAND(2682, 2734)
2763 = NAND(373, 2736)
2764 = NAND(376, 2738)
2765 = NAND(379, 2740)
2766 = NAND(382, 2742)
2767 = NAND(2688, 2743)
2768 = NAND(2690, 2744)
2773 = AND(2745, 275)
2776 = AND(2746, 276)
2779 = NAND(2724, 2757)
2780 = NAND(2726, 2758)
2781 = NAND(2728, 2759)
2782 = NAND(2730, 2760)
2783 = NAND(2732, 2761)
2784 = NAND(2735, 2763)
2785 = NAND(2737, 2764)
2786 = NAND(2739, 2765)
2787 = NAND(2741, 2766)
2788 = AND(2747, 2750, 2710)
2789 = NAND(2747, 2750)
2800 = AND(338, 2279, 99, 2788)
2807 = NAND(2773, 2018)
2808 = NOT(2773)
2809 = NAND(2776, 2019)
2810 = NOT(2776)
2811 = NOR(2384, 2800)
2812 = AND(897, 283, 2789)
2815 = AND(76, 283, 2789)
2818 = AND(82, 283, 2789)
2821 = AND(85, 283, 2789)
2824 = AND(898, 283, 2789)
2827 = NAND(1965, 2808)
2828 = NAND(1968, 2810)
2829 = AND(79, 283, 2789)
2843 = NAND(2807, 2827)
2846 = NAND(2809, 2828)
2850 = NAND(2812, 2076)
2851 = NAND(2815, 2077)
2852 = NAND(2818, 1915)
2853 = NAND(2821, 1857)
2854 = NAND(2824, 1938)
2857 = NOT(2812)
2858 = NOT(2815)
2859 = NOT(2818)
2860 = NOT(2821)
2861 = NOT(2824)
2862 = NOT(2829)
2863 = NAND(2829, 1985)
2866 = NAND(2052, 2857)
2867 = NAND(2055, 2858)
2868 = NAND(1866, 2859)
2869 = NAND(1818, 2860)
2870 = NAND(1902, 2861)
2871 = NAND(2843, 886)
2872 = NOT(2843)
2873 = NAND(2846, 887)
2874 = NOT(2846)
2875 = NAND(1933, 2862)
2876 = NAND(2866, 2850)
2877 = NAND(2867, 2851)
2878 = NAND(2868, 2852)
2879 = NAND(2869, 2853)
2880 = NAND(2870, 2854)
2881 = NAND(682, 2872)
2882 = NAND(685, 2874)
2883 = NAND(2875, 2863)
2886 = AND(2876, 550)
2887 = AND(551, 2877)
2888 = AND(553, 2878)
2889 = AND(2879, 554)
2890 = AND(555, 2880)
2891 = NAND(2871, 2881)
2892 = NAND(2873, 2882)
2895 = NAND(2883, 1461)
2896 = NOT(2883)
2897 = NAND(1383, 2896)
2898 = NAND(2895, 2897)
2899 = AND(2898, 552)

1745
bench_test/c3540.bench
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bench_test/c499.bench
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# c499
INPUT(1)
INPUT(5)
INPUT(9)
INPUT(13)
INPUT(17)
INPUT(21)
INPUT(25)
INPUT(29)
INPUT(33)
INPUT(37)
INPUT(41)
INPUT(45)
INPUT(49)
INPUT(53)
INPUT(57)
INPUT(61)
INPUT(65)
INPUT(69)
INPUT(73)
INPUT(77)
INPUT(81)
INPUT(85)
INPUT(89)
INPUT(93)
INPUT(97)
INPUT(101)
INPUT(105)
INPUT(109)
INPUT(113)
INPUT(117)
INPUT(121)
INPUT(125)
INPUT(129)
INPUT(130)
INPUT(131)
INPUT(132)
INPUT(133)
INPUT(134)
INPUT(135)
INPUT(136)
INPUT(137)
OUTPUT(724)
OUTPUT(725)
OUTPUT(726)
OUTPUT(727)
OUTPUT(728)
OUTPUT(729)
OUTPUT(730)
OUTPUT(731)
OUTPUT(732)
OUTPUT(733)
OUTPUT(734)
OUTPUT(735)
OUTPUT(736)
OUTPUT(737)
OUTPUT(738)
OUTPUT(739)
OUTPUT(740)
OUTPUT(741)
OUTPUT(742)
OUTPUT(743)
OUTPUT(744)
OUTPUT(745)
OUTPUT(746)
OUTPUT(747)
OUTPUT(748)
OUTPUT(749)
OUTPUT(750)
OUTPUT(751)
OUTPUT(752)
OUTPUT(753)
OUTPUT(754)
OUTPUT(755)
250 = XOR(1, 5)
251 = XOR(9, 13)
252 = XOR(17, 21)
253 = XOR(25, 29)
254 = XOR(33, 37)
255 = XOR(41, 45)
256 = XOR(49, 53)
257 = XOR(57, 61)
258 = XOR(65, 69)
259 = XOR(73, 77)
260 = XOR(81, 85)
261 = XOR(89, 93)
262 = XOR(97, 101)
263 = XOR(105, 109)
264 = XOR(113, 117)
265 = XOR(121, 125)
266 = AND(129, 137)
267 = AND(130, 137)
268 = AND(131, 137)
269 = AND(132, 137)
270 = AND(133, 137)
271 = AND(134, 137)
272 = AND(135, 137)
273 = AND(136, 137)
274 = XOR(1, 17)
275 = XOR(33, 49)
276 = XOR(5, 21)
277 = XOR(37, 53)
278 = XOR(9, 25)
279 = XOR(41, 57)
280 = XOR(13, 29)
281 = XOR(45, 61)
282 = XOR(65, 81)
283 = XOR(97, 113)
284 = XOR(69, 85)
285 = XOR(101, 117)
286 = XOR(73, 89)
287 = XOR(105, 121)
288 = XOR(77, 93)
289 = XOR(109, 125)
290 = XOR(250, 251)
293 = XOR(252, 253)
296 = XOR(254, 255)
299 = XOR(256, 257)
302 = XOR(258, 259)
305 = XOR(260, 261)
308 = XOR(262, 263)
311 = XOR(264, 265)
314 = XOR(274, 275)
315 = XOR(276, 277)
316 = XOR(278, 279)
317 = XOR(280, 281)
318 = XOR(282, 283)
319 = XOR(284, 285)
320 = XOR(286, 287)
321 = XOR(288, 289)
338 = XOR(290, 293)
339 = XOR(296, 299)
340 = XOR(290, 296)
341 = XOR(293, 299)
342 = XOR(302, 305)
343 = XOR(308, 311)
344 = XOR(302, 308)
345 = XOR(305, 311)
346 = XOR(266, 342)
347 = XOR(267, 343)
348 = XOR(268, 344)
349 = XOR(269, 345)
350 = XOR(270, 338)
351 = XOR(271, 339)
352 = XOR(272, 340)
353 = XOR(273, 341)
354 = XOR(314, 346)
367 = XOR(315, 347)
380 = XOR(316, 348)
393 = XOR(317, 349)
406 = XOR(318, 350)
419 = XOR(319, 351)
432 = XOR(320, 352)
445 = XOR(321, 353)
554 = NOT(354)
555 = NOT(367)
556 = NOT(380)
557 = NOT(354)
558 = NOT(367)
559 = NOT(393)
560 = NOT(354)
561 = NOT(380)
562 = NOT(393)
563 = NOT(367)
564 = NOT(380)
565 = NOT(393)
566 = NOT(419)
567 = NOT(445)
568 = NOT(419)
569 = NOT(432)
570 = NOT(406)
571 = NOT(445)
572 = NOT(406)
573 = NOT(432)
574 = NOT(406)
575 = NOT(419)
576 = NOT(432)
577 = NOT(406)
578 = NOT(419)
579 = NOT(445)
580 = NOT(406)
581 = NOT(432)
582 = NOT(445)
583 = NOT(419)
584 = NOT(432)
585 = NOT(445)
586 = NOT(367)
587 = NOT(393)
588 = NOT(367)
589 = NOT(380)
590 = NOT(354)
591 = NOT(393)
592 = NOT(354)
593 = NOT(380)
594 = AND(554, 555, 556, 393)
595 = AND(557, 558, 380, 559)
596 = AND(560, 367, 561, 562)
597 = AND(354, 563, 564, 565)
598 = AND(574, 575, 576, 445)
599 = AND(577, 578, 432, 579)
600 = AND(580, 419, 581, 582)
601 = AND(406, 583, 584, 585)
602 = OR(594, 595, 596, 597)
607 = OR(598, 599, 600, 601)
620 = AND(406, 566, 432, 567, 602)
625 = AND(406, 568, 569, 445, 602)
630 = AND(570, 419, 432, 571, 602)
635 = AND(572, 419, 573, 445, 602)
640 = AND(354, 586, 380, 587, 607)
645 = AND(354, 588, 589, 393, 607)
650 = AND(590, 367, 380, 591, 607)
655 = AND(592, 367, 593, 393, 607)
692 = AND(354, 620)
693 = AND(367, 620)
694 = AND(380, 620)
695 = AND(393, 620)
696 = AND(354, 625)
697 = AND(367, 625)
698 = AND(380, 625)
699 = AND(393, 625)
700 = AND(354, 630)
701 = AND(367, 630)
702 = AND(380, 630)
703 = AND(393, 630)
704 = AND(354, 635)
705 = AND(367, 635)
706 = AND(380, 635)
707 = AND(393, 635)
708 = AND(406, 640)
709 = AND(419, 640)
710 = AND(432, 640)
711 = AND(445, 640)
712 = AND(406, 645)
713 = AND(419, 645)
714 = AND(432, 645)
715 = AND(445, 645)
716 = AND(406, 650)
717 = AND(419, 650)
718 = AND(432, 650)
719 = AND(445, 650)
720 = AND(406, 655)
721 = AND(419, 655)
722 = AND(432, 655)
723 = AND(445, 655)
724 = XOR(1, 692)
725 = XOR(5, 693)
726 = XOR(9, 694)
727 = XOR(13, 695)
728 = XOR(17, 696)
729 = XOR(21, 697)
730 = XOR(25, 698)
731 = XOR(29, 699)
732 = XOR(33, 700)
733 = XOR(37, 701)
734 = XOR(41, 702)
735 = XOR(45, 703)
736 = XOR(49, 704)
737 = XOR(53, 705)
738 = XOR(57, 706)
739 = XOR(61, 707)
740 = XOR(65, 708)
741 = XOR(69, 709)
742 = XOR(73, 710)
743 = XOR(77, 711)
744 = XOR(81, 712)
745 = XOR(85, 713)
746 = XOR(89, 714)
747 = XOR(93, 715)
748 = XOR(97, 716)
749 = XOR(101, 717)
750 = XOR(105, 718)
751 = XOR(109, 719)
752 = XOR(113, 720)
753 = XOR(117, 721)
754 = XOR(121, 722)
755 = XOR(125, 723)

2484
bench_test/c6288.bench
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473
bench_test/c880.bench
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# c880
INPUT(1)
INPUT(8)
INPUT(13)
INPUT(17)
INPUT(26)
INPUT(29)
INPUT(36)
INPUT(42)
INPUT(51)
INPUT(55)
INPUT(59)
INPUT(68)
INPUT(72)
INPUT(73)
INPUT(74)
INPUT(75)
INPUT(80)
INPUT(85)
INPUT(86)
INPUT(87)
INPUT(88)
INPUT(89)
INPUT(90)
INPUT(91)
INPUT(96)
INPUT(101)
INPUT(106)
INPUT(111)
INPUT(116)
INPUT(121)
INPUT(126)
INPUT(130)
INPUT(135)
INPUT(138)
INPUT(143)
INPUT(146)
INPUT(149)
INPUT(152)
INPUT(153)
INPUT(156)
INPUT(159)
INPUT(165)
INPUT(171)
INPUT(177)
INPUT(183)
INPUT(189)
INPUT(195)
INPUT(201)
INPUT(207)
INPUT(210)
INPUT(219)
INPUT(228)
INPUT(237)
INPUT(246)
INPUT(255)
INPUT(259)
INPUT(260)
INPUT(261)
INPUT(267)
INPUT(268)
OUTPUT(388)
OUTPUT(389)
OUTPUT(390)
OUTPUT(391)
OUTPUT(418)
OUTPUT(419)
OUTPUT(420)
OUTPUT(421)
OUTPUT(422)
OUTPUT(423)
OUTPUT(446)
OUTPUT(447)
OUTPUT(448)
OUTPUT(449)
OUTPUT(450)
OUTPUT(767)
OUTPUT(768)
OUTPUT(850)
OUTPUT(863)
OUTPUT(864)
OUTPUT(865)
OUTPUT(866)
OUTPUT(874)
OUTPUT(878)
OUTPUT(879)
OUTPUT(880)
269 = NAND(1, 8, 13, 17)
270 = NAND(1, 26, 13, 17)
273 = AND(29, 36, 42)
276 = AND(1, 26, 51)
279 = NAND(1, 8, 51, 17)
280 = NAND(1, 8, 13, 55)
284 = NAND(59, 42, 68, 72)
285 = NAND(29, 68)
286 = NAND(59, 68, 74)
287 = AND(29, 75, 80)
290 = AND(29, 75, 42)
291 = AND(29, 36, 80)
292 = AND(29, 36, 42)
293 = AND(59, 75, 80)
294 = AND(59, 75, 42)
295 = AND(59, 36, 80)
296 = AND(59, 36, 42)
297 = AND(85, 86)
298 = OR(87, 88)
301 = NAND(91, 96)
302 = OR(91, 96)
303 = NAND(101, 106)
304 = OR(101, 106)
305 = NAND(111, 116)
306 = OR(111, 116)
307 = NAND(121, 126)
308 = OR(121, 126)
309 = AND(8, 138)
310 = NOT(268)
316 = AND(51, 138)
317 = AND(17, 138)
318 = AND(152, 138)
319 = NAND(59, 156)
322 = NOR(17, 42)
323 = AND(17, 42)
324 = NAND(159, 165)
325 = OR(159, 165)
326 = NAND(171, 177)
327 = OR(171, 177)
328 = NAND(183, 189)
329 = OR(183, 189)
330 = NAND(195, 201)
331 = OR(195, 201)
332 = AND(210, 91)
333 = AND(210, 96)
334 = AND(210, 101)
335 = AND(210, 106)
336 = AND(210, 111)
337 = AND(255, 259)
338 = AND(210, 116)
339 = AND(255, 260)
340 = AND(210, 121)
341 = AND(255, 267)
342 = NOT(269)
343 = NOT(273)
344 = OR(270, 273)
345 = NOT(276)
346 = NOT(276)
347 = NOT(279)
348 = NOR(280, 284)
349 = OR(280, 285)
350 = OR(280, 286)
351 = NOT(293)
352 = NOT(294)
353 = NOT(295)
354 = NOT(296)
355 = NAND(89, 298)
356 = AND(90, 298)
357 = NAND(301, 302)
360 = NAND(303, 304)
363 = NAND(305, 306)
366 = NAND(307, 308)
369 = NOT(310)
375 = NOR(322, 323)
376 = NAND(324, 325)
379 = NAND(326, 327)
382 = NAND(328, 329)
385 = NAND(330, 331)
388 = BUFF(290)
389 = BUFF(291)
390 = BUFF(292)
391 = BUFF(297)
392 = OR(270, 343)
393 = NOT(345)
399 = NOT(346)
400 = AND(348, 73)
401 = NOT(349)
402 = NOT(350)
403 = NOT(355)
404 = NOT(357)
405 = NOT(360)
406 = AND(357, 360)
407 = NOT(363)
408 = NOT(366)
409 = AND(363, 366)
410 = NAND(347, 352)
411 = NOT(376)
412 = NOT(379)
413 = AND(376, 379)
414 = NOT(382)
415 = NOT(385)
416 = AND(382, 385)
417 = AND(210, 369)
418 = BUFF(342)
419 = BUFF(344)
420 = BUFF(351)
421 = BUFF(353)
422 = BUFF(354)
423 = BUFF(356)
424 = NOT(400)
425 = AND(404, 405)
426 = AND(407, 408)
427 = AND(319, 393, 55)
432 = AND(393, 17, 287)
437 = NAND(393, 287, 55)
442 = NAND(375, 59, 156, 393)
443 = NAND(393, 319, 17)
444 = AND(411, 412)
445 = AND(414, 415)
446 = BUFF(392)
447 = BUFF(399)
448 = BUFF(401)
449 = BUFF(402)
450 = BUFF(403)
451 = NOT(424)
460 = NOR(406, 425)
463 = NOR(409, 426)
466 = NAND(442, 410)
475 = AND(143, 427)
476 = AND(310, 432)
477 = AND(146, 427)
478 = AND(310, 432)
479 = AND(149, 427)
480 = AND(310, 432)
481 = AND(153, 427)
482 = AND(310, 432)
483 = NAND(443, 1)
488 = OR(369, 437)
489 = OR(369, 437)
490 = OR(369, 437)
491 = OR(369, 437)
492 = NOR(413, 444)
495 = NOR(416, 445)
498 = NAND(130, 460)
499 = OR(130, 460)
500 = NAND(463, 135)
501 = OR(463, 135)
502 = AND(91, 466)
503 = NOR(475, 476)
504 = AND(96, 466)
505 = NOR(477, 478)
506 = AND(101, 466)
507 = NOR(479, 480)
508 = AND(106, 466)
509 = NOR(481, 482)
510 = AND(143, 483)
511 = AND(111, 466)
512 = AND(146, 483)
513 = AND(116, 466)
514 = AND(149, 483)
515 = AND(121, 466)
516 = AND(153, 483)
517 = AND(126, 466)
518 = NAND(130, 492)
519 = OR(130, 492)
520 = NAND(495, 207)
521 = OR(495, 207)
522 = AND(451, 159)
523 = AND(451, 165)
524 = AND(451, 171)
525 = AND(451, 177)
526 = AND(451, 183)
527 = NAND(451, 189)
528 = NAND(451, 195)
529 = NAND(451, 201)
530 = NAND(498, 499)
533 = NAND(500, 501)
536 = NOR(309, 502)
537 = NOR(316, 504)
538 = NOR(317, 506)
539 = NOR(318, 508)
540 = NOR(510, 511)
541 = NOR(512, 513)
542 = NOR(514, 515)
543 = NOR(516, 517)
544 = NAND(518, 519)
547 = NAND(520, 521)
550 = NOT(530)
551 = NOT(533)
552 = AND(530, 533)
553 = NAND(536, 503)
557 = NAND(537, 505)
561 = NAND(538, 507)
565 = NAND(539, 509)
569 = NAND(488, 540)
573 = NAND(489, 541)
577 = NAND(490, 542)
581 = NAND(491, 543)
585 = NOT(544)
586 = NOT(547)
587 = AND(544, 547)
588 = AND(550, 551)
589 = AND(585, 586)
590 = NAND(553, 159)
593 = OR(553, 159)
596 = AND(246, 553)
597 = NAND(557, 165)
600 = OR(557, 165)
605 = AND(246, 557)
606 = NAND(561, 171)
609 = OR(561, 171)
615 = AND(246, 561)
616 = NAND(565, 177)
619 = OR(565, 177)
624 = AND(246, 565)
625 = NAND(569, 183)
628 = OR(569, 183)
631 = AND(246, 569)
632 = NAND(573, 189)
635 = OR(573, 189)
640 = AND(246, 573)
641 = NAND(577, 195)
644 = OR(577, 195)
650 = AND(246, 577)
651 = NAND(581, 201)
654 = OR(581, 201)
659 = AND(246, 581)
660 = NOR(552, 588)
661 = NOR(587, 589)
662 = NOT(590)
665 = AND(593, 590)
669 = NOR(596, 522)
670 = NOT(597)
673 = AND(600, 597)
677 = NOR(605, 523)
678 = NOT(606)
682 = AND(609, 606)
686 = NOR(615, 524)
687 = NOT(616)
692 = AND(619, 616)
696 = NOR(624, 525)
697 = NOT(625)
700 = AND(628, 625)
704 = NOR(631, 526)
705 = NOT(632)
708 = AND(635, 632)
712 = NOR(337, 640)
713 = NOT(641)
717 = AND(644, 641)
721 = NOR(339, 650)
722 = NOT(651)
727 = AND(654, 651)
731 = NOR(341, 659)
732 = NAND(654, 261)
733 = NAND(644, 654, 261)
734 = NAND(635, 644, 654, 261)
735 = NOT(662)
736 = AND(228, 665)
737 = AND(237, 662)
738 = NOT(670)
739 = AND(228, 673)
740 = AND(237, 670)
741 = NOT(678)
742 = AND(228, 682)
743 = AND(237, 678)
744 = NOT(687)
745 = AND(228, 692)
746 = AND(237, 687)
747 = NOT(697)
748 = AND(228, 700)
749 = AND(237, 697)
750 = NOT(705)
751 = AND(228, 708)
752 = AND(237, 705)
753 = NOT(713)
754 = AND(228, 717)
755 = AND(237, 713)
756 = NOT(722)
757 = NOR(727, 261)
758 = AND(727, 261)
759 = AND(228, 727)
760 = AND(237, 722)
761 = NAND(644, 722)
762 = NAND(635, 713)
763 = NAND(635, 644, 722)
764 = NAND(609, 687)
765 = NAND(600, 678)
766 = NAND(600, 609, 687)
767 = BUFF(660)
768 = BUFF(661)
769 = NOR(736, 737)
770 = NOR(739, 740)
771 = NOR(742, 743)
772 = NOR(745, 746)
773 = NAND(750, 762, 763, 734)
777 = NOR(748, 749)
778 = NAND(753, 761, 733)
781 = NOR(751, 752)
782 = NAND(756, 732)
785 = NOR(754, 755)
786 = NOR(757, 758)
787 = NOR(759, 760)
788 = NOR(700, 773)
789 = AND(700, 773)
790 = NOR(708, 778)
791 = AND(708, 778)
792 = NOR(717, 782)
793 = AND(717, 782)
794 = AND(219, 786)
795 = NAND(628, 773)
796 = NAND(795, 747)
802 = NOR(788, 789)
803 = NOR(790, 791)
804 = NOR(792, 793)
805 = NOR(340, 794)
806 = NOR(692, 796)
807 = AND(692, 796)
808 = AND(219, 802)
809 = AND(219, 803)
810 = AND(219, 804)
811 = NAND(805, 787, 731, 529)
812 = NAND(619, 796)
813 = NAND(609, 619, 796)
814 = NAND(600, 609, 619, 796)
815 = NAND(738, 765, 766, 814)
819 = NAND(741, 764, 813)
822 = NAND(744, 812)
825 = NOR(806, 807)
826 = NOR(335, 808)
827 = NOR(336, 809)
828 = NOR(338, 810)
829 = NOT(811)
830 = NOR(665, 815)
831 = AND(665, 815)
832 = NOR(673, 819)
833 = AND(673, 819)
834 = NOR(682, 822)
835 = AND(682, 822)
836 = AND(219, 825)
837 = NAND(826, 777, 704)
838 = NAND(827, 781, 712, 527)
839 = NAND(828, 785, 721, 528)
840 = NOT(829)
841 = NAND(815, 593)
842 = NOR(830, 831)
843 = NOR(832, 833)
844 = NOR(834, 835)
845 = NOR(334, 836)
846 = NOT(837)
847 = NOT(838)
848 = NOT(839)
849 = AND(735, 841)
850 = BUFF(840)
851 = AND(219, 842)
852 = AND(219, 843)
853 = AND(219, 844)
854 = NAND(845, 772, 696)
855 = NOT(846)
856 = NOT(847)
857 = NOT(848)
858 = NOT(849)
859 = NOR(417, 851)
860 = NOR(332, 852)
861 = NOR(333, 853)
862 = NOT(854)
863 = BUFF(855)
864 = BUFF(856)
865 = BUFF(857)
866 = BUFF(858)
867 = NAND(859, 769, 669)
868 = NAND(860, 770, 677)
869 = NAND(861, 771, 686)
870 = NOT(862)
871 = NOT(867)
872 = NOT(868)
873 = NOT(869)
874 = BUFF(870)
875 = NOT(871)
876 = NOT(872)
877 = NOT(873)
878 = BUFF(875)
879 = BUFF(876)
880 = BUFF(877)

207
c432.bench
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@ -1,207 +0,0 @@
# c432
INPUT(1)
INPUT(4)
INPUT(8)
INPUT(11)
INPUT(14)
INPUT(17)
INPUT(21)
INPUT(24)
INPUT(27)
INPUT(30)
INPUT(34)
INPUT(37)
INPUT(40)
INPUT(43)
INPUT(47)
INPUT(50)
INPUT(53)
INPUT(56)
INPUT(60)
INPUT(63)
INPUT(66)
INPUT(69)
INPUT(73)
INPUT(76)
INPUT(79)
INPUT(82)
INPUT(86)
INPUT(89)
INPUT(92)
INPUT(95)
INPUT(99)
INPUT(102)
INPUT(105)
INPUT(108)
INPUT(112)
INPUT(115)
OUTPUT(223)
OUTPUT(329)
OUTPUT(370)
OUTPUT(421)
OUTPUT(430)
OUTPUT(431)
OUTPUT(432)
118 = NOT(1)
119 = NOT(4)
122 = NOT(11)
123 = NOT(17)
126 = NOT(24)
127 = NOT(30)
130 = NOT(37)
131 = NOT(43)
134 = NOT(50)
135 = NOT(56)
138 = NOT(63)
139 = NOT(69)
142 = NOT(76)
143 = NOT(82)
146 = NOT(89)
147 = NOT(95)
150 = NOT(102)
151 = NOT(108)
154 = NAND(118, 4)
157 = NOR(8, 119)
158 = NOR(14, 119)
159 = NAND(122, 17)
162 = NAND(126, 30)
165 = NAND(130, 43)
168 = NAND(134, 56)
171 = NAND(138, 69)
174 = NAND(142, 82)
177 = NAND(146, 95)
180 = NAND(150, 108)
183 = NOR(21, 123)
184 = NOR(27, 123)
185 = NOR(34, 127)
186 = NOR(40, 127)
187 = NOR(47, 131)
188 = NOR(53, 131)
189 = NOR(60, 135)
190 = NOR(66, 135)
191 = NOR(73, 139)
192 = NOR(79, 139)
193 = NOR(86, 143)
194 = NOR(92, 143)
195 = NOR(99, 147)
196 = NOR(105, 147)
197 = NOR(112, 151)
198 = NOR(115, 151)
199 = AND(154, 159, 162, 165, 168, 171, 174, 177, 180)
203 = NOT(199)
213 = NOT(199)
223 = NOT(199)
224 = XOR(203, 154)
227 = XOR(203, 159)
230 = XOR(203, 162)
233 = XOR(203, 165)
236 = XOR(203, 168)
239 = XOR(203, 171)
242 = NAND(1, 213)
243 = XOR(203, 174)
246 = NAND(213, 11)
247 = XOR(203, 177)
250 = NAND(213, 24)
251 = XOR(203, 180)
254 = NAND(213, 37)
255 = NAND(213, 50)
256 = NAND(213, 63)
257 = NAND(213, 76)
258 = NAND(213, 89)
259 = NAND(213, 102)
260 = NAND(224, 157)
263 = NAND(224, 158)
264 = NAND(227, 183)
267 = NAND(230, 185)
270 = NAND(233, 187)
273 = NAND(236, 189)
276 = NAND(239, 191)
279 = NAND(243, 193)
282 = NAND(247, 195)
285 = NAND(251, 197)
288 = NAND(227, 184)
289 = NAND(230, 186)
290 = NAND(233, 188)
291 = NAND(236, 190)
292 = NAND(239, 192)
293 = NAND(243, 194)
294 = NAND(247, 196)
295 = NAND(251, 198)
296 = AND(260, 264, 267, 270, 273, 276, 279, 282, 285)
300 = NOT(263)
301 = NOT(288)
302 = NOT(289)
303 = NOT(290)
304 = NOT(291)
305 = NOT(292)
306 = NOT(293)
307 = NOT(294)
308 = NOT(295)
309 = NOT(296)
319 = NOT(296)
329 = NOT(296)
330 = XOR(309, 260)
331 = XOR(309, 264)
332 = XOR(309, 267)
333 = XOR(309, 270)
334 = NAND(8, 319)
335 = XOR(309, 273)
336 = NAND(319, 21)
337 = XOR(309, 276)
338 = NAND(319, 34)
339 = XOR(309, 279)
340 = NAND(319, 47)
341 = XOR(309, 282)
342 = NAND(319, 60)
343 = XOR(309, 285)
344 = NAND(319, 73)
345 = NAND(319, 86)
346 = NAND(319, 99)
347 = NAND(319, 112)
348 = NAND(330, 300)
349 = NAND(331, 301)
350 = NAND(332, 302)
351 = NAND(333, 303)
352 = NAND(335, 304)
353 = NAND(337, 305)
354 = NAND(339, 306)
355 = NAND(341, 307)
356 = NAND(343, 308)
357 = AND(348, 349, 350, 351, 352, 353, 354, 355, 356)
360 = NOT(357)
370 = NOT(357)
371 = NAND(14, 360)
372 = NAND(360, 27)
373 = NAND(360, 40)
374 = NAND(360, 53)
375 = NAND(360, 66)
376 = NAND(360, 79)
377 = NAND(360, 92)
378 = NAND(360, 105)
379 = NAND(360, 115)
380 = NAND(4, 242, 334, 371)
381 = NAND(246, 336, 372, 17)
386 = NAND(250, 338, 373, 30)
393 = NAND(254, 340, 374, 43)
399 = NAND(255, 342, 375, 56)
404 = NAND(256, 344, 376, 69)
407 = NAND(257, 345, 377, 82)
411 = NAND(258, 346, 378, 95)
414 = NAND(259, 347, 379, 108)
415 = NOT(380)
416 = AND(381, 386, 393, 399, 404, 407, 411, 414)
417 = NOT(393)
418 = NOT(404)
419 = NOT(407)
420 = NOT(411)
421 = NOR(415, 416)
422 = NAND(386, 417)
425 = NAND(386, 393, 418, 399)
428 = NAND(399, 393, 419)
429 = NAND(386, 393, 407, 420)
430 = NAND(381, 386, 422, 399)
431 = NAND(381, 386, 425, 428)
432 = NAND(381, 422, 425, 429)

10
c432.report
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@ -1,10 +0,0 @@
gates: 160
primary input: 36
primary output: 7
simulate patterns: 0
final patterns: 77
faults: 524
detect faults: 520
redundant faults: 0
test coverage:0.992
time: 0.00859

2484
c6288.bench
View File

File diff suppressed because it is too large Load Diff

26
check.log
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@ -1,26 +0,0 @@
[1/26] 任务 ./benchmark/c17.bench
[2/26] 任务 ./benchmark/b06.bench
[3/26] 任务 ./benchmark/b01.bench
[4/26] 任务 ./benchmark/b03.bench
[5/26] 任务 ./benchmark/b09.bench
[6/26] 任务 ./benchmark/c880.bench
[7/26] 任务 ./benchmark/b10.bench
[8/26] 任务 ./benchmark/b08.bench
[9/26] 任务 ./benchmark/c499.bench
[10/26] 任务 ./benchmark/c1355.bench
[11/26] 任务 ./benchmark/c3540.bench
[12/26] 任务 ./benchmark/c1908.bench
[13/26] 任务 ./benchmark/b11.bench
[14/26] 任务 ./benchmark/c6288.bench
[15/26] 任务 ./benchmark/c2670.bench
[16/26] 任务 ./benchmark/b21.bench
[17/26] 任务 ./benchmark/b13.bench
[18/26] 任务 ./benchmark/b22.bench
[19/26] 任务 ./benchmark/b17.bench
[20/26] 任务 ./benchmark/b20.bench
[21/26] 任务 ./benchmark/c7552.bench
[22/26] 任务 ./benchmark/b12.bench
[23/26] 任务 ./benchmark/c5315.bench
[24/26] 任务 ./benchmark/b04.bench
[25/26] 任务 ./benchmark/b07.bench
[26/26] 任务 ./benchmark/c432.bench

92
exp_result/ATPG-LS_b01.bench.txt
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@ -1,92 +0,0 @@
make: 'atpg' is up to date.
========================
parsing file ./benchmark/b01.bench ... Done.
====== Circuit Statistics ======
PI: 7
PO: 7
Gate: 48
Stem: 28
Level: 3
================================
[SOL] flip: 0, stem: 0, fault:181. flip_cnt: 0, stem_cnt: 28, fault_cnt:41
coverage: 42.708% pattern: 1 before: 96 now: 55
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:227. flip_cnt: 0, stem_cnt: 28, fault_cnt:37
coverage: 64.583% pattern: 2 before: 55 now: 34
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:59. flip_cnt: 0, stem_cnt: 28, fault_cnt:38
coverage: 77.083% pattern: 3 before: 34 now: 22
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:71. flip_cnt: 0, stem_cnt: 28, fault_cnt:39
coverage: 82.292% pattern: 4 before: 22 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:5. flip_cnt: 0, stem_cnt: 28, fault_cnt:39
coverage: 85.417% pattern: 5 before: 17 now: 14
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 85.417% pattern: 5 before: 14 now: 14
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:51. flip_cnt: 0, stem_cnt: 28, fault_cnt:37
coverage: 88.542% pattern: 6 before: 14 now: 11
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:66. flip_cnt: 0, stem_cnt: 28, fault_cnt:32
coverage: 92.708% pattern: 7 before: 11 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 92.708% pattern: 7 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:38
coverage: 92.708% pattern: 7 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:13. flip_cnt: 0, stem_cnt: 28, fault_cnt:31
coverage: 93.750% pattern: 8 before: 7 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 28, fault_cnt:34
coverage: 95.833% pattern: 9 before: 6 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:6. flip_cnt: 0, stem_cnt: 28, fault_cnt:37
coverage: 96.875% pattern: 10 before: 4 now: 3
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:6. flip_cnt: 0, stem_cnt: 28, fault_cnt:28
coverage: 97.917% pattern: 11 before: 3 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:37
coverage: 97.917% pattern: 11 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:38
coverage: 97.917% pattern: 11 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 97.917% pattern: 11 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 28, fault_cnt:33
coverage: 98.958% pattern: 12 before: 2 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:24
coverage: 98.958% pattern: 12 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 98.958% pattern: 12 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:39
coverage: 98.958% pattern: 12 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:38
coverage: 98.958% pattern: 12 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:25
coverage: 98.958% pattern: 12 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:34
coverage: 98.958% pattern: 12 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:31
coverage: 98.958% pattern: 12 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:17. flip_cnt: 0, stem_cnt: 28, fault_cnt:31
coverage: 100.000% pattern: 13 before: 1 now: 0
checking valid circuit ... result: 1.
real 0m0.239s
user 0m0.237s
sys 0m0.000s

101
exp_result/ATPG-LS_b03.bench.txt
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@ -1,101 +0,0 @@
make: 'atpg' is up to date.
========================
parsing file ./benchmark/b03.bench ... Done.
====== Circuit Statistics ======
PI: 34
PO: 34
Gate: 152
Stem: 86
Level: 3
================================
[SOL] flip: 0, stem: 0, fault:741. flip_cnt: 0, stem_cnt: 86, fault_cnt:117
coverage: 38.487% pattern: 1 before: 304 now: 187
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:440. flip_cnt: 0, stem_cnt: 86, fault_cnt:114
coverage: 65.789% pattern: 2 before: 187 now: 104
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:338. flip_cnt: 0, stem_cnt: 86, fault_cnt:119
coverage: 78.618% pattern: 3 before: 104 now: 65
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:113. flip_cnt: 0, stem_cnt: 86, fault_cnt:119
coverage: 84.539% pattern: 4 before: 65 now: 47
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:137. flip_cnt: 0, stem_cnt: 86, fault_cnt:111
coverage: 92.434% pattern: 5 before: 47 now: 23
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:32. flip_cnt: 0, stem_cnt: 86, fault_cnt:107
coverage: 94.737% pattern: 6 before: 23 now: 16
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 86, fault_cnt:108
coverage: 95.724% pattern: 7 before: 16 now: 13
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:2. flip_cnt: 0, stem_cnt: 86, fault_cnt:112
coverage: 96.382% pattern: 8 before: 13 now: 11
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:2. flip_cnt: 0, stem_cnt: 86, fault_cnt:120
coverage: 96.711% pattern: 9 before: 11 now: 10
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:112
coverage: 96.711% pattern: 9 before: 10 now: 10
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:115
coverage: 98.355% pattern: 10 before: 10 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:120
coverage: 98.355% pattern: 10 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:125
coverage: 98.355% pattern: 10 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:118
coverage: 98.355% pattern: 10 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:111
coverage: 98.355% pattern: 10 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:124
coverage: 98.355% pattern: 10 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:123
coverage: 98.355% pattern: 10 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:125
coverage: 98.355% pattern: 10 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:118
coverage: 98.355% pattern: 10 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:15. flip_cnt: 0, stem_cnt: 86, fault_cnt:109
coverage: 99.342% pattern: 11 before: 5 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:109
coverage: 99.342% pattern: 11 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:112
coverage: 99.342% pattern: 11 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1. flip_cnt: 0, stem_cnt: 86, fault_cnt:115
coverage: 99.671% pattern: 12 before: 2 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:115
coverage: 99.671% pattern: 12 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:114
coverage: 99.671% pattern: 12 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:116
coverage: 99.671% pattern: 12 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:111
coverage: 99.671% pattern: 12 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:117
coverage: 99.671% pattern: 12 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:3. flip_cnt: 0, stem_cnt: 86, fault_cnt:114
coverage: 100.000% pattern: 13 before: 1 now: 0
checking valid circuit ... result: 1.
real 0m0.783s
user 0m0.778s
sys 0m0.004s

38440
exp_result/ATPG-LS_b04.bench.txt
View File

File diff suppressed because it is too large Load Diff

74
exp_result/ATPG-LS_b06.bench.txt
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@ -1,74 +0,0 @@
make: 'atpg' is up to date.
========================
parsing file ./benchmark/b06.bench ... Done.
====== Circuit Statistics ======
PI: 11
PO: 15
Gate: 56
Stem: 42
Level: 3
================================
[SOL] flip: 0, stem: 0, fault:159. flip_cnt: 0, stem_cnt: 42, fault_cnt:43
coverage: 38.393% pattern: 1 before: 112 now: 69
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:107. flip_cnt: 0, stem_cnt: 42, fault_cnt:43
coverage: 65.179% pattern: 2 before: 69 now: 39
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:23. flip_cnt: 0, stem_cnt: 42, fault_cnt:45
coverage: 78.571% pattern: 3 before: 39 now: 24
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:64. flip_cnt: 0, stem_cnt: 42, fault_cnt:46
coverage: 90.179% pattern: 4 before: 24 now: 11
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 42, fault_cnt:41
coverage: 91.071% pattern: 5 before: 11 now: 10
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:54. flip_cnt: 0, stem_cnt: 42, fault_cnt:45
coverage: 94.643% pattern: 6 before: 10 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:18. flip_cnt: 0, stem_cnt: 42, fault_cnt:36
coverage: 97.321% pattern: 7 before: 6 now: 3
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:14. flip_cnt: 0, stem_cnt: 42, fault_cnt:43
coverage: 98.214% pattern: 8 before: 3 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:40
coverage: 98.214% pattern: 8 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:44
coverage: 98.214% pattern: 8 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:34
coverage: 98.214% pattern: 8 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:46
coverage: 98.214% pattern: 8 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:45
coverage: 98.214% pattern: 8 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:35
coverage: 98.214% pattern: 8 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:36
coverage: 98.214% pattern: 8 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:41
coverage: 98.214% pattern: 8 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:13. flip_cnt: 0, stem_cnt: 42, fault_cnt:47
coverage: 99.107% pattern: 9 before: 2 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:41
coverage: 99.107% pattern: 9 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:46
coverage: 99.107% pattern: 9 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:15. flip_cnt: 0, stem_cnt: 42, fault_cnt:44
coverage: 100.000% pattern: 10 before: 1 now: 0
checking valid circuit ... result: 1.
real 0m0.107s
user 0m0.105s
sys 0m0.000s

53773
exp_result/ATPG-LS_b07.bench.txt
View File

File diff suppressed because it is too large Load Diff

3653
exp_result/ATPG-LS_b08.bench.txt
View File

File diff suppressed because it is too large Load Diff

692
exp_result/ATPG-LS_b09.bench.txt
View File

@ -1,692 +0,0 @@
make: 'atpg' is up to date.
========================
parsing file ./benchmark/b09.bench ... Done.
====== Circuit Statistics ======
PI: 29
PO: 29
Gate: 142
Stem: 79
Level: 3
================================
[SOL] flip: 0, stem: 0, fault:606. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
coverage: 39.789% pattern: 1 before: 284 now: 171
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:402. flip_cnt: 0, stem_cnt: 79, fault_cnt:91
coverage: 64.437% pattern: 2 before: 171 now: 101
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:142. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
coverage: 70.775% pattern: 3 before: 101 now: 83
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:150. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
coverage: 79.930% pattern: 4 before: 83 now: 57
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:43. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
coverage: 89.085% pattern: 5 before: 57 now: 31
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:154. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
coverage: 93.310% pattern: 6 before: 31 now: 19
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:17. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
coverage: 93.662% pattern: 7 before: 19 now: 18
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
coverage: 94.014% pattern: 8 before: 18 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:2. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
coverage: 94.366% pattern: 9 before: 17 now: 16
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:2. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
coverage: 94.718% pattern: 10 before: 16 now: 15
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
coverage: 95.070% pattern: 11 before: 15 now: 14
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
coverage: 95.070% pattern: 11 before: 14 now: 14
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
coverage: 95.070% pattern: 11 before: 14 now: 14
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
coverage: 95.070% pattern: 11 before: 14 now: 14
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 79, fault_cnt:87
coverage: 95.423% pattern: 12 before: 14 now: 13
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:10. flip_cnt: 0, stem_cnt: 79, fault_cnt:83
coverage: 97.535% pattern: 13 before: 13 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
coverage: 97.535% pattern: 13 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
coverage: 97.535% pattern: 13 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:119
coverage: 97.535% pattern: 13 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
coverage: 97.535% pattern: 13 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 79, fault_cnt:95
coverage: 97.887% pattern: 14 before: 7 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:81
coverage: 97.887% pattern: 14 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
coverage: 97.887% pattern: 14 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
coverage: 97.887% pattern: 14 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:93
coverage: 97.887% pattern: 14 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
coverage: 97.887% pattern: 14 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
coverage: 98.239% pattern: 15 before: 6 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
coverage: 98.239% pattern: 15 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
coverage: 98.239% pattern: 15 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
coverage: 98.239% pattern: 15 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:16. flip_cnt: 0, stem_cnt: 79, fault_cnt:91
coverage: 98.592% pattern: 16 before: 5 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
coverage: 98.592% pattern: 16 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
coverage: 98.592% pattern: 16 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:93
coverage: 98.592% pattern: 16 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:85
coverage: 98.592% pattern: 16 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117
coverage: 98.592% pattern: 16 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:119
coverage: 98.592% pattern: 16 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84
coverage: 98.592% pattern: 16 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
coverage: 98.592% pattern: 16 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
coverage: 98.592% pattern: 16 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
coverage: 98.592% pattern: 16 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
coverage: 98.592% pattern: 16 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
coverage: 98.592% pattern: 16 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
coverage: 98.592% pattern: 16 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
coverage: 98.592% pattern: 16 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117
coverage: 98.592% pattern: 16 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
coverage: 98.592% pattern: 16 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
coverage: 98.592% pattern: 16 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
coverage: 98.592% pattern: 16 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
coverage: 98.592% pattern: 16 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:76
coverage: 98.592% pattern: 16 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
coverage: 98.592% pattern: 16 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:119
coverage: 98.592% pattern: 16 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:18. flip_cnt: 0, stem_cnt: 79, fault_cnt:89
coverage: 98.944% pattern: 17 before: 4 now: 3
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 79, fault_cnt:95
coverage: 99.296% pattern: 18 before: 3 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:82
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:102
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:81
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:76
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:89
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:102
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:82
coverage: 99.296% pattern: 18 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:12. flip_cnt: 0, stem_cnt: 79, fault_cnt:97
coverage: 99.648% pattern: 19 before: 2 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:79
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:82
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:94
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:76
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:85
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:102
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:82
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:87
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:102
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:78
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:93
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:89
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:81
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:85
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:81
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:87
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:87
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:93
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:79
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:80
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:80
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:79
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:89
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:89
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:93
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:85
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:83
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:85
coverage: 99.648% pattern: 19 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:8. flip_cnt: 0, stem_cnt: 79, fault_cnt:94
coverage: 100.000% pattern: 20 before: 1 now: 0
checking valid circuit ... result: 1.
real 0m6.723s
user 0m6.720s
sys 0m0.000s

941
exp_result/ATPG-LS_b10.bench.txt
View File

@ -1,941 +0,0 @@
make: 'atpg' is up to date.
========================
parsing file ./benchmark/b10.bench ... Done.
====== Circuit Statistics ======
PI: 28
PO: 23
Gate: 182
Stem: 91
Level: 3
================================
[SOL] flip: 0, stem: 0, fault:1035. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
coverage: 30.769% pattern: 1 before: 364 now: 252
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:665. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
coverage: 45.879% pattern: 2 before: 252 now: 197
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:387. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 56.044% pattern: 3 before: 197 now: 160
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:253. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 60.440% pattern: 4 before: 160 now: 144
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:70. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
coverage: 62.637% pattern: 5 before: 144 now: 136
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:203. flip_cnt: 0, stem_cnt: 91, fault_cnt:96
coverage: 70.055% pattern: 6 before: 136 now: 109
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 70.879% pattern: 7 before: 109 now: 106
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:256. flip_cnt: 0, stem_cnt: 91, fault_cnt:120
coverage: 76.923% pattern: 8 before: 106 now: 84
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 78.022% pattern: 9 before: 84 now: 80
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:23. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 78.571% pattern: 10 before: 80 now: 78
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:115. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 80.495% pattern: 11 before: 78 now: 71
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:147. flip_cnt: 0, stem_cnt: 91, fault_cnt:113
coverage: 85.165% pattern: 12 before: 71 now: 54
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
coverage: 85.989% pattern: 13 before: 54 now: 51
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:54. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 90.659% pattern: 14 before: 51 now: 34
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 90.659% pattern: 14 before: 34 now: 34
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:11. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
coverage: 91.209% pattern: 15 before: 34 now: 32
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
coverage: 91.209% pattern: 15 before: 32 now: 32
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
coverage: 92.308% pattern: 16 before: 32 now: 28
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
coverage: 92.308% pattern: 16 before: 28 now: 28
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:110
coverage: 92.857% pattern: 17 before: 28 now: 26
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 92.857% pattern: 17 before: 26 now: 26
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 92.857% pattern: 17 before: 26 now: 26
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:16. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 93.132% pattern: 18 before: 26 now: 25
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:110
coverage: 93.132% pattern: 18 before: 25 now: 25
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
coverage: 93.132% pattern: 18 before: 25 now: 25
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:31. flip_cnt: 0, stem_cnt: 91, fault_cnt:110
coverage: 93.956% pattern: 19 before: 25 now: 22
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 94.231% pattern: 20 before: 22 now: 21
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:90
coverage: 94.231% pattern: 20 before: 21 now: 21
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:32. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 94.780% pattern: 21 before: 21 now: 19
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 94.780% pattern: 21 before: 19 now: 19
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
coverage: 94.780% pattern: 21 before: 19 now: 19
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:41. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
coverage: 95.604% pattern: 22 before: 19 now: 16
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:6. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
coverage: 95.879% pattern: 23 before: 16 now: 15
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:29. flip_cnt: 0, stem_cnt: 91, fault_cnt:115
coverage: 96.429% pattern: 24 before: 15 now: 13
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 96.429% pattern: 24 before: 13 now: 13
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 96.429% pattern: 24 before: 13 now: 13
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:118
coverage: 96.429% pattern: 24 before: 13 now: 13
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 96.429% pattern: 24 before: 13 now: 13
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:16. flip_cnt: 0, stem_cnt: 91, fault_cnt:115
coverage: 97.527% pattern: 25 before: 13 now: 9
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:5. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
coverage: 97.802% pattern: 26 before: 9 now: 8
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
coverage: 97.802% pattern: 26 before: 8 now: 8
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 97.802% pattern: 26 before: 8 now: 8
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 97.802% pattern: 26 before: 8 now: 8
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 97.802% pattern: 26 before: 8 now: 8
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:96
coverage: 97.802% pattern: 26 before: 8 now: 8
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 97.802% pattern: 26 before: 8 now: 8
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 97.802% pattern: 26 before: 8 now: 8
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
coverage: 97.802% pattern: 26 before: 8 now: 8
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
coverage: 97.802% pattern: 26 before: 8 now: 8
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 97.802% pattern: 26 before: 8 now: 8
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 97.802% pattern: 26 before: 8 now: 8
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
coverage: 97.802% pattern: 26 before: 8 now: 8
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:110
coverage: 97.802% pattern: 26 before: 8 now: 8
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 97.802% pattern: 26 before: 8 now: 8
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
coverage: 98.077% pattern: 27 before: 8 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:16. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
coverage: 98.626% pattern: 28 before: 7 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:35. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 99.451% pattern: 29 before: 5 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:110
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:115
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:119
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:95
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:116
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:114
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:117
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:113
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:110
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:94
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:96
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:91
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:96
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:118
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:94
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:117
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:96
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:95
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
coverage: 99.451% pattern: 29 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 91, fault_cnt:114
coverage: 99.725% pattern: 30 before: 2 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:113
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:116
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:114
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:96
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:95
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:93
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:113
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:116
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:95
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:116
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:94
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:113
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:116
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:95
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:114
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:110
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:113
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:94
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:110
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:96
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:116
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:110
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:114
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:84
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:92
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:113
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:113
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:94
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:120
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:117
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:115
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:114
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:116
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:95
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:95
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:95
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 99.725% pattern: 30 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 91, fault_cnt:118
coverage: 100.000% pattern: 31 before: 1 now: 0
checking valid circuit ... result: 1.
real 0m13.802s
user 0m13.797s
sys 0m0.000s

24271
exp_result/ATPG-LS_b11.bench.txt
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File diff suppressed because it is too large Load Diff

2941
exp_result/ATPG-LS_b12.bench.txt
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File diff suppressed because it is too large Load Diff

108628
exp_result/ATPG-LS_b13.bench.txt
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File diff suppressed because it is too large Load Diff

10
exp_result/ATPG-LS_b17.bench.txt
View File

@ -1,10 +0,0 @@
make: 'atpg' is up to date.
========================
parsing file ./benchmark/b17.bench ... Done.
====== Circuit Statistics ======
PI: 1452
PO: 1512
Gate: 23710
Stem: 8257
Level: 7
================================

79
exp_result/ATPG-LS_b20.bench.txt
View File

@ -1,79 +0,0 @@
make: 'atpg' is up to date.
========================
parsing file ./benchmark/b20.bench ... Done.
====== Circuit Statistics ======
PI: 522
PO: 512
Gate: 8734
Stem: 3428
Level: 7
================================
[SOL] flip: 0, stem: 0, fault:49107. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3179
coverage: 18.199% pattern: 1 before: 17468 now: 14289
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:28816. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3009
coverage: 27.908% pattern: 2 before: 14289 now: 12593
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:31154. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3635
coverage: 37.423% pattern: 3 before: 12593 now: 10931
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:7652. flip_cnt: 0, stem_cnt: 3428, fault_cnt:2945
coverage: 39.873% pattern: 4 before: 10931 now: 10503
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:3885. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3014
coverage: 41.127% pattern: 5 before: 10503 now: 10284
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:5760. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3259
coverage: 42.896% pattern: 6 before: 10284 now: 9975
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1034. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3045
coverage: 43.222% pattern: 7 before: 9975 now: 9918
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1011. flip_cnt: 0, stem_cnt: 3428, fault_cnt:2979
coverage: 43.537% pattern: 8 before: 9918 now: 9863
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:381. flip_cnt: 0, stem_cnt: 3428, fault_cnt:2987
coverage: 43.657% pattern: 9 before: 9863 now: 9842
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:10489. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3399
coverage: 46.823% pattern: 10 before: 9842 now: 9289
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:153. flip_cnt: 0, stem_cnt: 3428, fault_cnt:2905
coverage: 46.874% pattern: 11 before: 9289 now: 9280
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:5681. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3417
coverage: 48.586% pattern: 12 before: 9280 now: 8981
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:63. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3038
coverage: 48.615% pattern: 13 before: 8981 now: 8976
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 3428, fault_cnt:2944
coverage: 48.632% pattern: 14 before: 8976 now: 8973
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3002
coverage: 48.655% pattern: 15 before: 8973 now: 8969
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:23. flip_cnt: 0, stem_cnt: 3428, fault_cnt:2898
coverage: 48.666% pattern: 16 before: 8969 now: 8967
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3189
coverage: 48.683% pattern: 17 before: 8967 now: 8964
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3016
coverage: 48.683% pattern: 17 before: 8964 now: 8964
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 3428, fault_cnt:2987
coverage: 48.683% pattern: 17 before: 8964 now: 8964
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3030
coverage: 48.695% pattern: 18 before: 8964 now: 8962
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3133
coverage: 48.695% pattern: 18 before: 8962 now: 8962
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:874. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3187
coverage: 48.958% pattern: 19 before: 8962 now: 8916
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3076
coverage: 48.958% pattern: 19 before: 8916 now: 8916
checking valid circuit ... result: 1.

76
exp_result/ATPG-LS_b21.bench.txt
View File

@ -1,76 +0,0 @@
make: 'atpg' is up to date.
========================
parsing file ./benchmark/b21.bench ... Done.
====== Circuit Statistics ======
PI: 522
PO: 512
Gate: 8995
Stem: 3647
Level: 8
================================
[SOL] flip: 0, stem: 0, fault:51387. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2917
coverage: 16.215% pattern: 1 before: 17990 now: 15073
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:31083. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2990
coverage: 26.148% pattern: 2 before: 15073 now: 13286
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:13816. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2964
coverage: 30.812% pattern: 3 before: 13286 now: 12447
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:8210. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2890
coverage: 33.346% pattern: 4 before: 12447 now: 11991
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:14317. flip_cnt: 0, stem_cnt: 3647, fault_cnt:3232
coverage: 37.599% pattern: 5 before: 11991 now: 11226
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:2900. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2982
coverage: 38.471% pattern: 6 before: 11226 now: 11069
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1253. flip_cnt: 0, stem_cnt: 3647, fault_cnt:3028
coverage: 38.844% pattern: 7 before: 11069 now: 11002
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:3176. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2858
coverage: 39.789% pattern: 8 before: 11002 now: 10832
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:5492. flip_cnt: 0, stem_cnt: 3647, fault_cnt:3168
coverage: 41.401% pattern: 9 before: 10832 now: 10542
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:290. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2893
coverage: 41.501% pattern: 10 before: 10542 now: 10524
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:382. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2988
coverage: 41.618% pattern: 11 before: 10524 now: 10503
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:191. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2956
coverage: 41.679% pattern: 12 before: 10503 now: 10492
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2804
coverage: 41.723% pattern: 13 before: 10492 now: 10484
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1750. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2770
coverage: 42.240% pattern: 14 before: 10484 now: 10391
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:78. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2984
coverage: 42.268% pattern: 15 before: 10391 now: 10386
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2959
coverage: 42.279% pattern: 16 before: 10386 now: 10384
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2897
coverage: 42.279% pattern: 16 before: 10384 now: 10384
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:3610. flip_cnt: 0, stem_cnt: 3647, fault_cnt:3191
coverage: 43.335% pattern: 17 before: 10384 now: 10194
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:513. flip_cnt: 0, stem_cnt: 3647, fault_cnt:3083
coverage: 43.485% pattern: 18 before: 10194 now: 10167
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2897
coverage: 43.513% pattern: 19 before: 10167 now: 10162
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1501. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2843
coverage: 43.952% pattern: 20 before: 10162 now: 10083
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:4629. flip_cnt: 0, stem_cnt: 3647, fault_cnt:3206
coverage: 45.309% pattern: 21 before: 10083 now: 9839
checking valid circuit ... result: 1.

22
exp_result/ATPG-LS_b22.bench.txt
View File

@ -1,22 +0,0 @@
make: 'atpg' is up to date.
========================
parsing file ./benchmark/b22.bench ... Done.
====== Circuit Statistics ======
PI: 767
PO: 757
Gate: 13721
Stem: 5379
Level: 8
================================
[SOL] flip: 0, stem: 0, fault:75481. flip_cnt: 0, stem_cnt: 5379, fault_cnt:4379
coverage: 15.957% pattern: 1 before: 27442 now: 23063
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:42481. flip_cnt: 0, stem_cnt: 5379, fault_cnt:4587
coverage: 24.299% pattern: 2 before: 23063 now: 20774
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19160. flip_cnt: 0, stem_cnt: 5379, fault_cnt:4476
coverage: 28.613% pattern: 3 before: 20774 now: 19590
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:10322. flip_cnt: 0, stem_cnt: 5379, fault_cnt:4248
coverage: 30.701% pattern: 4 before: 19590 now: 19017
checking valid circuit ... result: 1.

12233
exp_result/ATPG-LS_c1355.bench.txt
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File diff suppressed because it is too large Load Diff

29
exp_result/ATPG-LS_c17.bench.txt
View File

@ -1,29 +0,0 @@
make: 'atpg' is up to date.
========================
parsing file ./benchmark/c17.bench ... Done.
====== Circuit Statistics ======
PI: 5
PO: 2
Gate: 11
Stem: 9
Level: 2
================================
[SOL] flip: 0, stem: 0, fault:8. flip_cnt: 0, stem_cnt: 9, fault_cnt:8
coverage: 36.364% pattern: 1 before: 22 now: 14
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 9, fault_cnt:9
coverage: 54.545% pattern: 2 before: 14 now: 10
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:18. flip_cnt: 0, stem_cnt: 9, fault_cnt:9
coverage: 90.909% pattern: 3 before: 10 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 9, fault_cnt:8
coverage: 90.909% pattern: 3 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:2. flip_cnt: 0, stem_cnt: 9, fault_cnt:5
coverage: 100.000% pattern: 4 before: 2 now: 0
checking valid circuit ... result: 1.
real 0m0.003s
user 0m0.002s
sys 0m0.000s

18373
exp_result/ATPG-LS_c1908.bench.txt
View File

File diff suppressed because it is too large Load Diff

13489
exp_result/ATPG-LS_c2670.bench.txt
View File

File diff suppressed because it is too large Load Diff

1312
exp_result/ATPG-LS_c3540.bench.txt
View File

File diff suppressed because it is too large Load Diff

180163
exp_result/ATPG-LS_c432.bench.txt
View File

File diff suppressed because it is too large Load Diff

7481
exp_result/ATPG-LS_c499.bench.txt
View File

File diff suppressed because it is too large Load Diff

2434
exp_result/ATPG-LS_c5315.bench.txt
View File

File diff suppressed because it is too large Load Diff

499
exp_result/ATPG-LS_c6288.bench.txt
View File

@ -1,499 +0,0 @@
make: 'atpg' is up to date.
========================
parsing file ./benchmark/c6288.bench ... Done.
====== Circuit Statistics ======
PI: 32
PO: 32
Gate: 2448
Stem: 1488
Level: 7
================================
[SOL] flip: 0, stem: 0, fault:41770. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2199
coverage: 44.914% pattern: 1 before: 4896 now: 2697
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:17100. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196
coverage: 63.297% pattern: 2 before: 2697 now: 1797
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:12844. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2205
coverage: 77.104% pattern: 3 before: 1797 now: 1121
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:7239. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2201
coverage: 84.886% pattern: 4 before: 1121 now: 740
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:4275. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2202
coverage: 89.481% pattern: 5 before: 740 now: 515
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:2660. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2187
coverage: 92.341% pattern: 6 before: 515 now: 375
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1634. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
coverage: 94.097% pattern: 7 before: 375 now: 289
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1121. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
coverage: 95.302% pattern: 8 before: 289 now: 230
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:665. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2201
coverage: 96.017% pattern: 9 before: 230 now: 195
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:950. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197
coverage: 97.038% pattern: 10 before: 195 now: 145
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:380. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2167
coverage: 97.447% pattern: 11 before: 145 now: 125
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:399. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
coverage: 97.876% pattern: 12 before: 125 now: 104
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2207
coverage: 98.080% pattern: 13 before: 104 now: 94
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2208
coverage: 98.284% pattern: 14 before: 94 now: 84
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194
coverage: 98.366% pattern: 15 before: 84 now: 80
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2173
coverage: 98.529% pattern: 16 before: 80 now: 72
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2185
coverage: 98.754% pattern: 17 before: 72 now: 61
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
coverage: 98.775% pattern: 18 before: 61 now: 60
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2190
coverage: 98.958% pattern: 19 before: 60 now: 51
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2188
coverage: 99.040% pattern: 20 before: 51 now: 47
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194
coverage: 99.163% pattern: 21 before: 47 now: 41
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2185
coverage: 99.224% pattern: 22 before: 41 now: 38
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2188
coverage: 99.265% pattern: 23 before: 38 now: 36
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2206
coverage: 99.265% pattern: 23 before: 36 now: 36
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2204
coverage: 99.265% pattern: 23 before: 36 now: 36
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2212
coverage: 99.285% pattern: 24 before: 36 now: 35
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2203
coverage: 99.326% pattern: 25 before: 35 now: 33
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
coverage: 99.367% pattern: 26 before: 33 now: 31
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2177
coverage: 99.387% pattern: 27 before: 31 now: 30
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2180
coverage: 99.387% pattern: 27 before: 30 now: 30
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2235
coverage: 99.408% pattern: 28 before: 30 now: 29
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2202
coverage: 99.408% pattern: 28 before: 29 now: 29
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2184
coverage: 99.428% pattern: 29 before: 29 now: 28
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
coverage: 99.449% pattern: 30 before: 28 now: 27
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
coverage: 99.449% pattern: 30 before: 27 now: 27
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
coverage: 99.449% pattern: 30 before: 27 now: 27
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
coverage: 99.449% pattern: 30 before: 27 now: 27
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2207
coverage: 99.489% pattern: 31 before: 27 now: 25
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
coverage: 99.530% pattern: 32 before: 25 now: 23
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2185
coverage: 99.551% pattern: 33 before: 23 now: 22
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
coverage: 99.551% pattern: 33 before: 22 now: 22
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2182
coverage: 99.571% pattern: 34 before: 22 now: 21
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2185
coverage: 99.571% pattern: 34 before: 21 now: 21
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2233
coverage: 99.571% pattern: 34 before: 21 now: 21
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2188
coverage: 99.571% pattern: 34 before: 21 now: 21
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2177
coverage: 99.571% pattern: 34 before: 21 now: 21
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2198
coverage: 99.571% pattern: 34 before: 21 now: 21
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194
coverage: 99.571% pattern: 34 before: 21 now: 21
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197
coverage: 99.571% pattern: 34 before: 21 now: 21
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2179
coverage: 99.592% pattern: 35 before: 21 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2223
coverage: 99.592% pattern: 35 before: 20 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2187
coverage: 99.592% pattern: 35 before: 20 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2208
coverage: 99.592% pattern: 35 before: 20 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
coverage: 99.592% pattern: 35 before: 20 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2202
coverage: 99.592% pattern: 35 before: 20 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
coverage: 99.592% pattern: 35 before: 20 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196
coverage: 99.592% pattern: 35 before: 20 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
coverage: 99.592% pattern: 35 before: 20 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2162
coverage: 99.592% pattern: 35 before: 20 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2198
coverage: 99.592% pattern: 35 before: 20 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194
coverage: 99.592% pattern: 35 before: 20 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
coverage: 99.592% pattern: 35 before: 20 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2187
coverage: 99.592% pattern: 35 before: 20 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
coverage: 99.592% pattern: 35 before: 20 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2203
coverage: 99.592% pattern: 35 before: 20 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
coverage: 99.592% pattern: 35 before: 20 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
coverage: 99.592% pattern: 35 before: 20 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2181
coverage: 99.592% pattern: 35 before: 20 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194
coverage: 99.592% pattern: 35 before: 20 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
coverage: 99.592% pattern: 35 before: 20 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2181
coverage: 99.592% pattern: 35 before: 20 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2199
coverage: 99.592% pattern: 35 before: 20 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
coverage: 99.592% pattern: 35 before: 20 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
coverage: 99.592% pattern: 35 before: 20 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
coverage: 99.592% pattern: 35 before: 20 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2212
coverage: 99.592% pattern: 35 before: 20 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2209
coverage: 99.592% pattern: 35 before: 20 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2210
coverage: 99.592% pattern: 35 before: 20 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2231
coverage: 99.612% pattern: 36 before: 20 now: 19
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
coverage: 99.612% pattern: 36 before: 19 now: 19
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
coverage: 99.612% pattern: 36 before: 19 now: 19
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
coverage: 99.612% pattern: 36 before: 19 now: 19
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2215
coverage: 99.612% pattern: 36 before: 19 now: 19
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2199
coverage: 99.612% pattern: 36 before: 19 now: 19
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
coverage: 99.612% pattern: 36 before: 19 now: 19
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194
coverage: 99.612% pattern: 36 before: 19 now: 19
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2190
coverage: 99.612% pattern: 36 before: 19 now: 19
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
coverage: 99.612% pattern: 36 before: 19 now: 19
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2190
coverage: 99.612% pattern: 36 before: 19 now: 19
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196
coverage: 99.612% pattern: 36 before: 19 now: 19
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197
coverage: 99.612% pattern: 36 before: 19 now: 19
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193
coverage: 99.612% pattern: 36 before: 19 now: 19
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197
coverage: 99.612% pattern: 36 before: 19 now: 19
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
coverage: 99.612% pattern: 36 before: 19 now: 19
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2186
coverage: 99.612% pattern: 36 before: 19 now: 19
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
coverage: 99.612% pattern: 36 before: 19 now: 19
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2180
coverage: 99.653% pattern: 37 before: 19 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2200
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2186
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2209
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2181
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2190
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2179
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2203
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2180
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2186
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2182
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2184
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2177
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2180
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2185
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2172
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2188
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2184
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2179
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2213
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2174
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2179
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2174
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2199
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2224
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2203
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2181
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2187
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2190
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2201
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2179
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2198
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2203
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2201
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2186
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2188
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2201
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2204
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2216
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2202
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2203
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2174
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2181
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2186
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2170
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2181
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2190
coverage: 99.653% pattern: 37 before: 17 now: 17
checking valid circuit ... result: 1.

1939
exp_result/ATPG-LS_c7552.bench.txt
View File

File diff suppressed because it is too large Load Diff

530
exp_result/ATPG-LS_c880.bench.txt
View File

@ -1,530 +0,0 @@
make: 'atpg' is up to date.
========================
parsing file ./benchmark/c880.bench ... Done.
====== Circuit Statistics ======
PI: 60
PO: 26
Gate: 443
Stem: 165
Level: 6
================================
[SOL] flip: 0, stem: 0, fault:2949. flip_cnt: 0, stem_cnt: 165, fault_cnt:256
coverage: 28.894% pattern: 1 before: 886 now: 630
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:2909. flip_cnt: 0, stem_cnt: 165, fault_cnt:319
coverage: 56.321% pattern: 2 before: 630 now: 387
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:738. flip_cnt: 0, stem_cnt: 165, fault_cnt:231
coverage: 64.447% pattern: 3 before: 387 now: 315
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1090. flip_cnt: 0, stem_cnt: 165, fault_cnt:288
coverage: 73.589% pattern: 4 before: 315 now: 234
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:453. flip_cnt: 0, stem_cnt: 165, fault_cnt:272
coverage: 78.217% pattern: 5 before: 234 now: 193
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:680. flip_cnt: 0, stem_cnt: 165, fault_cnt:293
coverage: 82.957% pattern: 6 before: 193 now: 151
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 165, fault_cnt:175
coverage: 83.521% pattern: 7 before: 151 now: 146
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:34. flip_cnt: 0, stem_cnt: 165, fault_cnt:216
coverage: 83.973% pattern: 8 before: 146 now: 142
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:380. flip_cnt: 0, stem_cnt: 165, fault_cnt:265
coverage: 86.230% pattern: 9 before: 142 now: 122
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:197. flip_cnt: 0, stem_cnt: 165, fault_cnt:250
coverage: 87.810% pattern: 10 before: 122 now: 108
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:266
coverage: 87.923% pattern: 11 before: 108 now: 107
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:283
coverage: 87.923% pattern: 11 before: 107 now: 107
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 165, fault_cnt:246
coverage: 88.488% pattern: 12 before: 107 now: 102
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 165, fault_cnt:248
coverage: 88.713% pattern: 13 before: 102 now: 100
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 165, fault_cnt:244
coverage: 89.278% pattern: 14 before: 100 now: 95
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:170
coverage: 89.391% pattern: 15 before: 95 now: 94
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:237. flip_cnt: 0, stem_cnt: 165, fault_cnt:254
coverage: 90.858% pattern: 16 before: 94 now: 81
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:183. flip_cnt: 0, stem_cnt: 165, fault_cnt:204
coverage: 93.002% pattern: 17 before: 81 now: 62
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:102. flip_cnt: 0, stem_cnt: 165, fault_cnt:284
coverage: 94.018% pattern: 18 before: 62 now: 53
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:137. flip_cnt: 0, stem_cnt: 165, fault_cnt:212
coverage: 95.372% pattern: 19 before: 53 now: 41
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 165, fault_cnt:259
coverage: 95.598% pattern: 20 before: 41 now: 39
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:18. flip_cnt: 0, stem_cnt: 165, fault_cnt:202
coverage: 96.388% pattern: 21 before: 39 now: 32
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:5. flip_cnt: 0, stem_cnt: 165, fault_cnt:218
coverage: 96.614% pattern: 22 before: 32 now: 30
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:268
coverage: 96.727% pattern: 23 before: 30 now: 29
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:40. flip_cnt: 0, stem_cnt: 165, fault_cnt:318
coverage: 97.178% pattern: 24 before: 29 now: 25
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:50. flip_cnt: 0, stem_cnt: 165, fault_cnt:186
coverage: 97.743% pattern: 25 before: 25 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 165, fault_cnt:224
coverage: 98.081% pattern: 26 before: 20 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 165, fault_cnt:255
coverage: 98.307% pattern: 27 before: 17 now: 15
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:8. flip_cnt: 0, stem_cnt: 165, fault_cnt:246
coverage: 98.420% pattern: 28 before: 15 now: 14
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216
coverage: 98.420% pattern: 28 before: 14 now: 14
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:234
coverage: 98.533% pattern: 29 before: 14 now: 13
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220
coverage: 98.533% pattern: 29 before: 13 now: 13
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:254
coverage: 98.533% pattern: 29 before: 13 now: 13
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:34. flip_cnt: 0, stem_cnt: 165, fault_cnt:212
coverage: 98.758% pattern: 30 before: 13 now: 11
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253
coverage: 98.758% pattern: 30 before: 11 now: 11
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:274
coverage: 98.758% pattern: 30 before: 11 now: 11
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 165, fault_cnt:267
coverage: 98.984% pattern: 31 before: 11 now: 9
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241
coverage: 98.984% pattern: 31 before: 9 now: 9
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:238
coverage: 98.984% pattern: 31 before: 9 now: 9
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:197
coverage: 98.984% pattern: 31 before: 9 now: 9
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216
coverage: 98.984% pattern: 31 before: 9 now: 9
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:239
coverage: 98.984% pattern: 31 before: 9 now: 9
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:268
coverage: 99.210% pattern: 32 before: 9 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:247
coverage: 99.210% pattern: 32 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:313
coverage: 99.210% pattern: 32 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:211
coverage: 99.210% pattern: 32 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:330
coverage: 99.210% pattern: 32 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:252
coverage: 99.210% pattern: 32 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:269
coverage: 99.210% pattern: 32 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:200
coverage: 99.210% pattern: 32 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:182
coverage: 99.210% pattern: 32 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:201
coverage: 99.210% pattern: 32 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:272
coverage: 99.210% pattern: 32 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:255
coverage: 99.210% pattern: 32 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:246
coverage: 99.210% pattern: 32 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:260
coverage: 99.210% pattern: 32 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241
coverage: 99.210% pattern: 32 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:257
coverage: 99.210% pattern: 32 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241
coverage: 99.210% pattern: 32 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:340
coverage: 99.210% pattern: 32 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:242
coverage: 99.210% pattern: 32 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228
coverage: 99.210% pattern: 32 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:163
coverage: 99.210% pattern: 32 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:219
coverage: 99.210% pattern: 32 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:252
coverage: 99.210% pattern: 32 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:310
coverage: 99.210% pattern: 32 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:272
coverage: 99.210% pattern: 32 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
coverage: 99.210% pattern: 32 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:250
coverage: 99.210% pattern: 32 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:265
coverage: 99.210% pattern: 32 before: 7 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:229
coverage: 99.323% pattern: 33 before: 7 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
coverage: 99.323% pattern: 33 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:251
coverage: 99.323% pattern: 33 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:239
coverage: 99.323% pattern: 33 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:259
coverage: 99.323% pattern: 33 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:288
coverage: 99.323% pattern: 33 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:211
coverage: 99.323% pattern: 33 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:235
coverage: 99.323% pattern: 33 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:227
coverage: 99.323% pattern: 33 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:231
coverage: 99.323% pattern: 33 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:217
coverage: 99.323% pattern: 33 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:301
coverage: 99.323% pattern: 33 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:252
coverage: 99.323% pattern: 33 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228
coverage: 99.323% pattern: 33 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:219
coverage: 99.323% pattern: 33 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:240
coverage: 99.323% pattern: 33 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:180
coverage: 99.323% pattern: 33 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:270
coverage: 99.323% pattern: 33 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:209
coverage: 99.323% pattern: 33 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:283
coverage: 99.323% pattern: 33 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:189
coverage: 99.323% pattern: 33 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:188
coverage: 99.323% pattern: 33 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:205
coverage: 99.323% pattern: 33 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225
coverage: 99.323% pattern: 33 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:185
coverage: 99.323% pattern: 33 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:259
coverage: 99.323% pattern: 33 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:208
coverage: 99.323% pattern: 33 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:256
coverage: 99.323% pattern: 33 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:200
coverage: 99.323% pattern: 33 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:246
coverage: 99.323% pattern: 33 before: 6 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:2. flip_cnt: 0, stem_cnt: 165, fault_cnt:198
coverage: 99.436% pattern: 34 before: 6 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:162
coverage: 99.436% pattern: 34 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253
coverage: 99.436% pattern: 34 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
coverage: 99.436% pattern: 34 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233
coverage: 99.436% pattern: 34 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216
coverage: 99.436% pattern: 34 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:285
coverage: 99.436% pattern: 34 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:247
coverage: 99.436% pattern: 34 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:201
coverage: 99.436% pattern: 34 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:167
coverage: 99.436% pattern: 34 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225
coverage: 99.436% pattern: 34 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:278
coverage: 99.436% pattern: 34 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
coverage: 99.436% pattern: 34 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233
coverage: 99.436% pattern: 34 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:274
coverage: 99.436% pattern: 34 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253
coverage: 99.436% pattern: 34 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:287
coverage: 99.436% pattern: 34 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:264
coverage: 99.436% pattern: 34 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218
coverage: 99.436% pattern: 34 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:259
coverage: 99.436% pattern: 34 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:257
coverage: 99.436% pattern: 34 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:285
coverage: 99.549% pattern: 35 before: 5 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:262
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:242
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:264
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:276
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:274
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:237
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:327
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:269
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:205
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:195
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:286
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:247
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:268
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:200
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:172
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:251
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:237
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:201
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:304
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:172
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:293
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:164
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:195
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:254
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:205
coverage: 99.549% pattern: 35 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:33. flip_cnt: 0, stem_cnt: 165, fault_cnt:270
coverage: 99.774% pattern: 36 before: 4 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:15. flip_cnt: 0, stem_cnt: 165, fault_cnt:295
coverage: 99.887% pattern: 37 before: 2 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236
coverage: 99.887% pattern: 37 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228
coverage: 99.887% pattern: 37 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:226
coverage: 99.887% pattern: 37 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:245
coverage: 99.887% pattern: 37 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:282
coverage: 99.887% pattern: 37 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221
coverage: 99.887% pattern: 37 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:246
coverage: 99.887% pattern: 37 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:182
coverage: 99.887% pattern: 37 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241
coverage: 99.887% pattern: 37 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:238
coverage: 99.887% pattern: 37 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236
coverage: 99.887% pattern: 37 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:203
coverage: 99.887% pattern: 37 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228
coverage: 99.887% pattern: 37 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:210
coverage: 99.887% pattern: 37 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:263
coverage: 99.887% pattern: 37 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:222
coverage: 99.887% pattern: 37 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:185
coverage: 99.887% pattern: 37 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:16. flip_cnt: 0, stem_cnt: 165, fault_cnt:229
coverage: 100.000% pattern: 38 before: 1 now: 0
checking valid circuit ... result: 1.
real 0m13.726s
user 0m13.723s
sys 0m0.000s

1
fault-simulator

@ -1 +0,0 @@
Subproject commit 54d48b917c1f5ab7a9ea4c8de2573b649dd73575

89
makefile
View File

@ -1,72 +1,35 @@
#一个实用的makefile，能自动编译当前目录下所有.c/.cpp源文件，支持二者混合编译
#并且当某个.c/.cpp、.h或依赖的源文件被修改后，仅重编涉及到的源文件，未涉及的不编译
#详解文档：http://blog.csdn.net/huyansoft/article/details/8924624
#author：胡彦 2013-5-21
# 定义源文件列表
SOURCES := $(wildcard *.c) $(wildcard *.cpp) $(wildcard CCAnr/*.cpp)
#----------------------------------------------------------
#编译工具用g++，以同时支持C和C++程序，以及二者的混合编译
CC=g++
# 将源文件列表转换为目标文件列表
OBJECTS := $(addprefix build/,$(SOURCES:%=%.o))
CPPFLAGS=-O3 -std=c++17 -g
# 声明编译器和编译选项
CC := gcc
CXX := g++
CFLAGS := -O3 -g -Wall -Wextra -MMD -MP -flto
CXXFLAGS := -O3 -g -Wall -Wextra -MMD -MP -flto
#使用$(winldcard *.c)来获取工作目录下的所有.c文件的列表
#sources:=main.cpp command.c
# 默认目标，编译所有目标文件
atpg: $(OBJECTS)
$(CXX) $(CXXFLAGS) $^ -o $@
#变量sources得到当前目录下待编译的.c/.cpp文件的列表，两次调用winldcard、结果连在一起即可
sources:=$(wildcard *.c) $(wildcard *.cpp)
# 生成目标文件的规则
build/%.o: % | build
$(CC) $(CFLAGS) -c $< -o $@
#变量objects得到待生成的.o文件的列表，把sources中每个文件的扩展名换成.o即可。这里两次调用patsubst函数，第1次把sources中所有.cpp换成.o，第2次把第1次结果里所有.c换成.o
objects:=$(patsubst %.c,%.o,$(patsubst %.cpp,%.o,$(sources)))
build/%.o: %.cpp | build
$(CXX) $(CXXFLAGS) -c $< -o $@
#变量dependence得到待生成的.d文件的列表，把objects中每个扩展名.o换成.d即可。也可写成$(patsubst %.o,%.d,$(objects))
dependence:=$(objects:.o=.d)
# 包含依赖文件
-include $(OBJECTS:.o=.d)
#----------------------------------------------------------
#当$(objects)列表里所有文件都生成后，便可调用这里的 $(CC) $^ -o $@ 命令生成最终目标all了
#把all定义成第1个规则，使得可以把make all命令简写成make
atpg: $(objects)
$(CC) $(CPPFLAGS) $^ -o $@
# @./$@ #编译后立即执行
# 如果需要，则递归创建源文件的目录结构
build:
mkdir -p $(sort $(dir $(OBJECTS)))
#这段使用make的模式规则，指示如何由.c文件生成.o，即对每个.c文件，调用gcc -c XX.c -o XX.o命令生成对应的.o文件
#如果不写这段也可以，因为make的隐含规则可以起到同样的效果
%.o: %.c
$(CC) $(CPPFLAGS) -c $< -o $@
# 清除所有目标文件和build目录
clean:
rm -rf build $(OBJECTS)
#同上，指示如何由.cpp生成.o，可省略
%.o: %.cpp
$(CC) $(CPPFLAGS) -c $< -o $@
#----------------------------------------------------------
include $(dependence) #注意该句要放在终极目标all的规则之后，否则.d文件里的规则会被误当作终极规则了
#因为这4行命令要多次凋用，定义成命令包以简化书写
define gen_dep
set -e; rm -f $@; \
$(CC) -MM $(CPPFLAGS) $< > $@.$$$$; \
sed 's,\($*\)\.o[ :]*,\1.o $@ : ,g' < $@.$$$$ > $@; \
rm -f $@.$$$$
endef
#指示如何由.c生成其依赖规则文件.d
#这段使用make的模式规则，指示对每个.c文件，如何生成其依赖规则文件.d，调用上面的命令包即可
%.d: %.c
$(gen_dep)
#同上，指示对每个.cpp，如何生成其依赖规则文件.d
%.d: %.cpp
$(gen_dep)
#----------------------------------------------------------
#清除所有临时文件（所有.o和.d）。之所以把clean定义成伪目标，是因为这个目标并不对应实际的文件
.PHONY: clean
clean: #.$$已在每次使用后立即删除。-f参数表示被删文件不存在时不报错
rm -f all $(objects) $(dependence)
echo: #调试时显示一些变量的值
@echo sources=$(sources)
@echo objects=$(objects)
@echo dependence=$(dependence)
@echo CPPFLAGS=$(CPPFLAGS)
#提醒：当混合编译.c/.cpp时，为了能够在C++程序里调用C函数，必须把每一个要调用的C函数，其声明都包括在extern "C"{}块里面，这样C++链接时才能成功链接它们。
.PHONY: clean all

90
res.txt
View File

@ -1,90 +0,0 @@
parsing file c432.bench...
INPUT(1)
tokens: $INPUT$ $($ $1$ $)$
INPUT(4)
tokens: $INPUT$ $($ $4$ $)$
INPUT(8)
tokens: $INPUT$ $($ $8$ $)$
INPUT(11)
tokens: $INPUT$ $($ $11$ $)$
INPUT(14)
tokens: $INPUT$ $($ $14$ $)$
INPUT(17)
tokens: $INPUT$ $($ $17$ $)$
INPUT(21)
tokens: $INPUT$ $($ $21$ $)$
INPUT(24)
tokens: $INPUT$ $($ $24$ $)$
INPUT(27)
tokens: $INPUT$ $($ $27$ $)$
INPUT(30)
tokens: $INPUT$ $($ $30$ $)$
INPUT(34)
tokens: $INPUT$ $($ $34$ $)$
INPUT(37)
tokens: $INPUT$ $($ $37$ $)$
INPUT(40)
tokens: $INPUT$ $($ $40$ $)$
INPUT(43)
tokens: $INPUT$ $($ $43$ $)$
INPUT(47)
tokens: $INPUT$ $($ $47$ $)$
INPUT(50)
tokens: $INPUT$ $($ $50$ $)$
INPUT(53)
tokens: $INPUT$ $($ $53$ $)$
INPUT(56)
tokens: $INPUT$ $($ $56$ $)$
INPUT(60)
tokens: $INPUT$ $($ $60$ $)$
INPUT(63)
tokens: $INPUT$ $($ $63$ $)$
INPUT(66)
tokens: $INPUT$ $($ $66$ $)$
INPUT(69)
tokens: $INPUT$ $($ $69$ $)$
INPUT(73)
tokens: $INPUT$ $($ $73$ $)$
INPUT(76)
tokens: $INPUT$ $($ $76$ $)$
INPUT(79)
tokens: $INPUT$ $($ $79$ $)$
INPUT(82)
tokens: $INPUT$ $($ $82$ $)$
INPUT(86)
tokens: $INPUT$ $($ $86$ $)$
INPUT(89)
tokens: $INPUT$ $($ $89$ $)$
INPUT(92)
tokens: $INPUT$ $($ $92$ $)$
INPUT(95)
tokens: $INPUT$ $($ $95$ $)$
INPUT(99)
tokens: $INPUT$ $($ $99$ $)$
INPUT(102)
tokens: $INPUT$ $($ $102$ $)$
INPUT(105)
tokens: $INPUT$ $($ $105$ $)$
INPUT(108)
tokens: $INPUT$ $($ $108$ $)$
INPUT(112)
tokens: $INPUT$ $($ $112$ $)$
INPUT(115)
tokens: $INPUT$ $($ $115$ $)$
OUTPUT(223)
tokens: $OUTPUT$ $($ $223$ $)$
OUTPUT(329)
tokens: $OUTPUT$ $($ $329$ $)$
OUTPUT(370)
tokens: $OUTPUT$ $($ $370$ $)$
OUTPUT(421)
tokens: $OUTPUT$ $($ $421$ $)$
OUTPUT(430)
tokens: $OUTPUT$ $($ $430$ $)$
OUTPUT(431)
tokens: $OUTPUT$ $($ $431$ $)$
OUTPUT(432)
tokens: $OUTPUT$ $($ $432$ $)$
118 = NOT(1)
tokens: $118$ $=$ $NOT$ $($ $1$ $)$
Error while reading line: 118 = NOT(1)