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YuhangQ 2023-03-09 13:17:53 +08:00
parent 622f0f11f9
commit 8e923f249d
28 changed files with 175351 additions and 1 deletions
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2
.gitignore vendored
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*.o
*.d
.vscode
*.txt
output.txt

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exp_result/ATPG-LS_b01.bench.txt Normal file
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make: 'atpg' is up to date.
========================
parsing file ./benchmark/b01.bench ... Done.
====== Circuit Statistics ======
PI: 7
PO: 7
Gate: 48
Stem: 28
Level: 3
================================
[SOL] flip: 0, stem: 0, fault:541. flip_cnt: 0, stem_cnt: 28, fault_cnt:42
coverage: 43.750% pattern: 1 before: 96 now: 54
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:145. flip_cnt: 0, stem_cnt: 28, fault_cnt:39
coverage: 63.542% pattern: 2 before: 54 now: 35
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:43. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 68.750% pattern: 3 before: 35 now: 30
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 28, fault_cnt:38
coverage: 76.042% pattern: 4 before: 30 now: 23
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:2. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 78.125% pattern: 5 before: 23 now: 21
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 78.125% pattern: 5 before: 21 now: 21
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 78.125% pattern: 5 before: 21 now: 21
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 78.125% pattern: 5 before: 21 now: 21
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 78.125% pattern: 5 before: 21 now: 21
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:75. flip_cnt: 0, stem_cnt: 28, fault_cnt:32
coverage: 82.292% pattern: 6 before: 21 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 82.292% pattern: 6 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 82.292% pattern: 6 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 82.292% pattern: 6 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 82.292% pattern: 6 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:49. flip_cnt: 0, stem_cnt: 28, fault_cnt:38
coverage: 86.458% pattern: 7 before: 17 now: 13
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 28, fault_cnt:34
coverage: 88.542% pattern: 8 before: 13 now: 11
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:12. flip_cnt: 0, stem_cnt: 28, fault_cnt:37
coverage: 91.667% pattern: 9 before: 11 now: 8
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 28, fault_cnt:37
coverage: 94.792% pattern: 10 before: 8 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:13. flip_cnt: 0, stem_cnt: 28, fault_cnt:31
coverage: 95.833% pattern: 11 before: 5 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 28, fault_cnt:31
coverage: 96.875% pattern: 12 before: 4 now: 3
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:31
coverage: 96.875% pattern: 12 before: 3 now: 3
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:5. flip_cnt: 0, stem_cnt: 28, fault_cnt:38
coverage: 97.917% pattern: 13 before: 3 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:38
coverage: 97.917% pattern: 13 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:11. flip_cnt: 0, stem_cnt: 28, fault_cnt:28
coverage: 98.958% pattern: 14 before: 2 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:7. flip_cnt: 0, stem_cnt: 28, fault_cnt:34
coverage: 100.000% pattern: 15 before: 1 now: 0
checking valid circuit ... result: 1.
real 0m0.364s
user 0m0.359s
sys 0m0.004s

7
exp_result/ATPG-LS_b02.bench.txt Normal file
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make: 'atpg' is up to date.
========================
parsing file ./benchmark/b02.bench ...Error while reading file: DFF is not a valid gate.
real 0m0.003s
user 0m0.001s
sys 0m0.000s

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exp_result/ATPG-LS_b03.bench.txt Normal file
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make: 'atpg' is up to date.
========================
parsing file ./benchmark/b03.bench ... Done.
====== Circuit Statistics ======
PI: 34
PO: 34
Gate: 152
Stem: 86
Level: 3
================================
[SOL] flip: 0, stem: 0, fault:1483. flip_cnt: 0, stem_cnt: 86, fault_cnt:117
coverage: 38.487% pattern: 1 before: 304 now: 187
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1222. flip_cnt: 0, stem_cnt: 86, fault_cnt:121
coverage: 60.526% pattern: 2 before: 187 now: 120
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:170. flip_cnt: 0, stem_cnt: 86, fault_cnt:107
coverage: 73.026% pattern: 3 before: 120 now: 82
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:399. flip_cnt: 0, stem_cnt: 86, fault_cnt:124
coverage: 79.934% pattern: 4 before: 82 now: 61
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:62. flip_cnt: 0, stem_cnt: 86, fault_cnt:117
coverage: 83.224% pattern: 5 before: 61 now: 51
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:72. flip_cnt: 0, stem_cnt: 86, fault_cnt:113
coverage: 84.539% pattern: 6 before: 51 now: 47
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 86, fault_cnt:121
coverage: 85.526% pattern: 7 before: 47 now: 44
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 86, fault_cnt:115
coverage: 89.803% pattern: 8 before: 44 now: 31
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:138. flip_cnt: 0, stem_cnt: 86, fault_cnt:117
coverage: 92.434% pattern: 9 before: 31 now: 23
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 86, fault_cnt:114
coverage: 93.092% pattern: 10 before: 23 now: 21
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:119
coverage: 93.092% pattern: 10 before: 21 now: 21
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:117
coverage: 93.421% pattern: 11 before: 21 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:127
coverage: 93.750% pattern: 12 before: 20 now: 19
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 86, fault_cnt:122
coverage: 94.408% pattern: 13 before: 19 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:120
coverage: 94.408% pattern: 13 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:86. flip_cnt: 0, stem_cnt: 86, fault_cnt:111
coverage: 98.355% pattern: 14 before: 17 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 86, fault_cnt:113
coverage: 99.013% pattern: 15 before: 5 now: 3
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:117
coverage: 99.342% pattern: 16 before: 3 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:116
coverage: 99.342% pattern: 16 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:116
coverage: 99.342% pattern: 16 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:118
coverage: 99.342% pattern: 16 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:119
coverage: 99.342% pattern: 16 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:115
coverage: 99.342% pattern: 16 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:122
coverage: 99.342% pattern: 16 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:113
coverage: 99.342% pattern: 16 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:114
coverage: 99.671% pattern: 17 before: 2 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:121
coverage: 99.671% pattern: 17 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:111
coverage: 99.671% pattern: 17 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:116
coverage: 99.671% pattern: 17 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:117
coverage: 99.671% pattern: 17 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:115
coverage: 99.671% pattern: 17 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:120
coverage: 99.671% pattern: 17 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:109
coverage: 99.671% pattern: 17 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:113
coverage: 99.671% pattern: 17 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:111
coverage: 99.671% pattern: 17 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:124
coverage: 99.671% pattern: 17 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:127
coverage: 100.000% pattern: 18 before: 1 now: 0
checking valid circuit ... result: 1.
real 0m5.785s
user 0m5.778s
sys 0m0.004s

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exp_result/ATPG-LS_b04.bench.txt Normal file
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make: 'atpg' is up to date.
========================
parsing file ./benchmark/b04.bench ... Done.
====== Circuit Statistics ======
PI: 77
PO: 74
Gate: 587
Stem: 262
Level: 7
================================
[SOL] flip: 0, stem: 0, fault:3259. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
coverage: 25.383% pattern: 1 before: 1174 now: 876
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:3249. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
coverage: 39.949% pattern: 2 before: 876 now: 705
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1254. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
coverage: 45.571% pattern: 3 before: 705 now: 639
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:969. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
coverage: 49.915% pattern: 4 before: 639 now: 588
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:608. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
coverage: 52.641% pattern: 5 before: 588 now: 556
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
coverage: 53.152% pattern: 6 before: 556 now: 550
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:874. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
coverage: 57.070% pattern: 7 before: 550 now: 504
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
coverage: 57.070% pattern: 7 before: 504 now: 504
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
coverage: 57.325% pattern: 8 before: 504 now: 501
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
coverage: 57.325% pattern: 8 before: 501 now: 501
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
coverage: 57.325% pattern: 8 before: 501 now: 501
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
coverage: 57.411% pattern: 9 before: 501 now: 500
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
coverage: 58.433% pattern: 10 before: 500 now: 488
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
coverage: 58.433% pattern: 10 before: 488 now: 488
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
coverage: 58.433% pattern: 10 before: 488 now: 488
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
coverage: 58.433% pattern: 10 before: 488 now: 488
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
coverage: 58.433% pattern: 10 before: 488 now: 488
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
coverage: 58.433% pattern: 10 before: 488 now: 488
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
coverage: 58.433% pattern: 10 before: 488 now: 488
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
coverage: 58.433% pattern: 10 before: 488 now: 488
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
coverage: 58.433% pattern: 10 before: 488 now: 488
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
coverage: 58.603% pattern: 11 before: 488 now: 486
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
coverage: 58.773% pattern: 12 before: 486 now: 484
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
coverage: 58.773% pattern: 12 before: 484 now: 484
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
coverage: 58.773% pattern: 12 before: 484 now: 484
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
coverage: 58.773% pattern: 12 before: 484 now: 484
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
coverage: 58.944% pattern: 13 before: 484 now: 482
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
coverage: 58.944% pattern: 13 before: 482 now: 482
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
coverage: 58.944% pattern: 13 before: 482 now: 482
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
coverage: 58.944% pattern: 13 before: 482 now: 482
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
coverage: 58.944% pattern: 13 before: 482 now: 482
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
coverage: 58.944% pattern: 13 before: 482 now: 482
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
coverage: 58.944% pattern: 13 before: 482 now: 482
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
coverage: 58.944% pattern: 13 before: 482 now: 482
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
coverage: 58.944% pattern: 13 before: 482 now: 482
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
coverage: 58.944% pattern: 13 before: 482 now: 482
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
coverage: 58.944% pattern: 13 before: 482 now: 482
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
coverage: 58.944% pattern: 13 before: 482 now: 482
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
coverage: 58.944% pattern: 13 before: 482 now: 482
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
coverage: 58.944% pattern: 13 before: 482 now: 482
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
coverage: 58.944% pattern: 13 before: 482 now: 482
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
coverage: 58.944% pattern: 13 before: 482 now: 482
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
coverage: 58.944% pattern: 13 before: 482 now: 482
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
coverage: 58.944% pattern: 13 before: 482 now: 482
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
coverage: 58.944% pattern: 13 before: 482 now: 482
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
coverage: 58.944% pattern: 13 before: 482 now: 482
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
coverage: 58.944% pattern: 13 before: 482 now: 482
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
coverage: 58.944% pattern: 13 before: 482 now: 482
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
coverage: 58.944% pattern: 13 before: 482 now: 482
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:2152. flip_cnt: 0, stem_cnt: 262, fault_cnt:376
coverage: 68.995% pattern: 14 before: 482 now: 364
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
coverage: 68.995% pattern: 14 before: 364 now: 364
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
coverage: 68.995% pattern: 14 before: 364 now: 364
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
coverage: 68.995% pattern: 14 before: 364 now: 364
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:928. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
coverage: 73.424% pattern: 15 before: 364 now: 312
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
coverage: 73.424% pattern: 15 before: 312 now: 312
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
coverage: 73.424% pattern: 15 before: 312 now: 312
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
coverage: 73.424% pattern: 15 before: 312 now: 312
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
coverage: 73.424% pattern: 15 before: 312 now: 312
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
coverage: 73.424% pattern: 15 before: 312 now: 312
checking valid circuit ... result: 1.

56
exp_result/ATPG-LS_b06.bench.txt Normal file
View File

@ -0,0 +1,56 @@
make: 'atpg' is up to date.
========================
parsing file ./benchmark/b06.bench ... Done.
====== Circuit Statistics ======
PI: 11
PO: 15
Gate: 56
Stem: 42
Level: 3
================================
[SOL] flip: 0, stem: 0, fault:513. flip_cnt: 0, stem_cnt: 42, fault_cnt:44
coverage: 39.286% pattern: 1 before: 112 now: 68
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:99. flip_cnt: 0, stem_cnt: 42, fault_cnt:44
coverage: 66.071% pattern: 2 before: 68 now: 38
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:10. flip_cnt: 0, stem_cnt: 42, fault_cnt:45
coverage: 75.000% pattern: 3 before: 38 now: 28
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:204. flip_cnt: 0, stem_cnt: 42, fault_cnt:45
coverage: 86.607% pattern: 4 before: 28 now: 15
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:56. flip_cnt: 0, stem_cnt: 42, fault_cnt:45
coverage: 90.179% pattern: 5 before: 15 now: 11
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:12. flip_cnt: 0, stem_cnt: 42, fault_cnt:47
coverage: 91.071% pattern: 6 before: 11 now: 10
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:6. flip_cnt: 0, stem_cnt: 42, fault_cnt:40
coverage: 92.857% pattern: 7 before: 10 now: 8
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:8. flip_cnt: 0, stem_cnt: 42, fault_cnt:41
coverage: 93.750% pattern: 8 before: 8 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 42, fault_cnt:36
coverage: 96.429% pattern: 9 before: 7 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:7. flip_cnt: 0, stem_cnt: 42, fault_cnt:40
coverage: 97.321% pattern: 10 before: 4 now: 3
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:3. flip_cnt: 0, stem_cnt: 42, fault_cnt:43
coverage: 98.214% pattern: 11 before: 3 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:13. flip_cnt: 0, stem_cnt: 42, fault_cnt:44
coverage: 99.107% pattern: 12 before: 2 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:46
coverage: 99.107% pattern: 12 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1. flip_cnt: 0, stem_cnt: 42, fault_cnt:40
coverage: 100.000% pattern: 13 before: 1 now: 0
checking valid circuit ... result: 1.
real 0m0.098s
user 0m0.093s
sys 0m0.004s

301
exp_result/ATPG-LS_b07.bench.txt Normal file
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@ -0,0 +1,301 @@
make: 'atpg' is up to date.
========================
parsing file ./benchmark/b07.bench ... Done.
====== Circuit Statistics ======
PI: 50
PO: 57
Gate: 419
Stem: 224
Level: 5
================================
[SOL] flip: 0, stem: 0, fault:2928. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
coverage: 29.236% pattern: 1 before: 838 now: 593
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:2071. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
coverage: 42.243% pattern: 2 before: 593 now: 484
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1368. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
coverage: 50.835% pattern: 3 before: 484 now: 412
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:893. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
coverage: 56.444% pattern: 4 before: 412 now: 365
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
coverage: 57.637% pattern: 5 before: 365 now: 355
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1767. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
coverage: 68.735% pattern: 6 before: 355 now: 262
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
coverage: 69.212% pattern: 7 before: 262 now: 258
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
coverage: 70.525% pattern: 8 before: 258 now: 247
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
coverage: 70.525% pattern: 8 before: 247 now: 247
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
coverage: 70.644% pattern: 9 before: 247 now: 246
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
coverage: 70.644% pattern: 9 before: 246 now: 246
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
coverage: 71.002% pattern: 10 before: 246 now: 243
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
coverage: 71.002% pattern: 10 before: 243 now: 243
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
coverage: 71.241% pattern: 11 before: 243 now: 241
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
coverage: 71.241% pattern: 11 before: 241 now: 241
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
coverage: 71.241% pattern: 11 before: 241 now: 241
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
coverage: 71.838% pattern: 12 before: 241 now: 236
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
coverage: 72.673% pattern: 13 before: 236 now: 229
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
coverage: 72.673% pattern: 13 before: 229 now: 229
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
coverage: 73.628% pattern: 14 before: 229 now: 221
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:969. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
coverage: 79.714% pattern: 15 before: 221 now: 170
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
coverage: 79.714% pattern: 15 before: 170 now: 170
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
coverage: 80.072% pattern: 16 before: 170 now: 167
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
coverage: 80.072% pattern: 16 before: 167 now: 167
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
coverage: 80.072% pattern: 16 before: 167 now: 167
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
coverage: 80.072% pattern: 16 before: 167 now: 167
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
coverage: 80.310% pattern: 17 before: 167 now: 165
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
coverage: 80.310% pattern: 17 before: 165 now: 165
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
coverage: 80.310% pattern: 17 before: 165 now: 165
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
coverage: 80.310% pattern: 17 before: 165 now: 165
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
coverage: 80.310% pattern: 17 before: 165 now: 165
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
coverage: 80.310% pattern: 17 before: 165 now: 165
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
coverage: 80.907% pattern: 18 before: 165 now: 160
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
coverage: 80.907% pattern: 18 before: 160 now: 160
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
coverage: 80.907% pattern: 18 before: 160 now: 160
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
coverage: 80.907% pattern: 18 before: 160 now: 160
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
coverage: 80.907% pattern: 18 before: 160 now: 160
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
coverage: 80.907% pattern: 18 before: 160 now: 160
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
coverage: 80.907% pattern: 18 before: 160 now: 160
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
coverage: 80.907% pattern: 18 before: 160 now: 160
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
coverage: 80.907% pattern: 18 before: 160 now: 160
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
coverage: 80.907% pattern: 18 before: 160 now: 160
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
coverage: 80.907% pattern: 18 before: 160 now: 160
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:760. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
coverage: 85.680% pattern: 19 before: 160 now: 120
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
coverage: 85.680% pattern: 19 before: 120 now: 120
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
coverage: 85.680% pattern: 19 before: 120 now: 120
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
coverage: 85.680% pattern: 19 before: 120 now: 120
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
coverage: 85.680% pattern: 19 before: 120 now: 120
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
coverage: 85.800% pattern: 20 before: 120 now: 119
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
coverage: 85.800% pattern: 20 before: 119 now: 119
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
coverage: 85.800% pattern: 20 before: 119 now: 119
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
coverage: 87.112% pattern: 21 before: 119 now: 108
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
coverage: 87.112% pattern: 21 before: 108 now: 108
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
coverage: 87.112% pattern: 21 before: 108 now: 108
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
coverage: 87.112% pattern: 21 before: 108 now: 108
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
coverage: 87.112% pattern: 21 before: 108 now: 108
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
coverage: 87.112% pattern: 21 before: 108 now: 108
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
coverage: 87.112% pattern: 21 before: 108 now: 108
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
coverage: 87.112% pattern: 21 before: 108 now: 108
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
coverage: 87.112% pattern: 21 before: 108 now: 108
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
coverage: 87.709% pattern: 22 before: 108 now: 103
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
coverage: 87.709% pattern: 22 before: 103 now: 103
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
coverage: 87.709% pattern: 22 before: 103 now: 103
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
coverage: 87.709% pattern: 22 before: 103 now: 103
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
coverage: 87.709% pattern: 22 before: 103 now: 103
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
coverage: 87.709% pattern: 22 before: 103 now: 103
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
coverage: 88.783% pattern: 23 before: 103 now: 94
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
coverage: 88.783% pattern: 23 before: 94 now: 94
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
coverage: 88.783% pattern: 23 before: 94 now: 94
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
coverage: 88.783% pattern: 23 before: 94 now: 94
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
coverage: 88.783% pattern: 23 before: 94 now: 94
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
coverage: 88.783% pattern: 23 before: 94 now: 94
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
coverage: 88.783% pattern: 23 before: 94 now: 94
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
coverage: 88.783% pattern: 23 before: 94 now: 94
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
coverage: 88.783% pattern: 23 before: 94 now: 94
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
coverage: 88.783% pattern: 23 before: 94 now: 94
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
coverage: 88.783% pattern: 23 before: 94 now: 94
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
coverage: 88.783% pattern: 23 before: 94 now: 94
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
coverage: 89.737% pattern: 24 before: 94 now: 86
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
coverage: 89.737% pattern: 24 before: 86 now: 86
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
coverage: 89.737% pattern: 24 before: 86 now: 86
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
coverage: 89.737% pattern: 24 before: 86 now: 86
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
coverage: 89.737% pattern: 24 before: 86 now: 86
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
coverage: 89.737% pattern: 24 before: 86 now: 86
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
coverage: 89.737% pattern: 24 before: 86 now: 86
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
coverage: 89.857% pattern: 25 before: 86 now: 85
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
coverage: 89.857% pattern: 25 before: 85 now: 85
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
coverage: 89.857% pattern: 25 before: 85 now: 85
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
coverage: 89.857% pattern: 25 before: 85 now: 85
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
coverage: 90.453% pattern: 26 before: 85 now: 80
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
coverage: 90.453% pattern: 26 before: 80 now: 80
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
coverage: 90.453% pattern: 26 before: 80 now: 80
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
coverage: 90.453% pattern: 26 before: 80 now: 80
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
coverage: 90.453% pattern: 26 before: 80 now: 80
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
coverage: 90.453% pattern: 26 before: 80 now: 80
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
coverage: 90.453% pattern: 26 before: 80 now: 80
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
coverage: 90.453% pattern: 26 before: 80 now: 80
checking valid circuit ... result: 1.

6134
exp_result/ATPG-LS_b08.bench.txt Normal file
View File

File diff suppressed because it is too large Load Diff

2240
exp_result/ATPG-LS_b09.bench.txt Normal file
View File

File diff suppressed because it is too large Load Diff

431
exp_result/ATPG-LS_b10.bench.txt Normal file
View File

@ -0,0 +1,431 @@
make: 'atpg' is up to date.
========================
parsing file ./benchmark/b10.bench ... Done.
====== Circuit Statistics ======
PI: 28
PO: 23
Gate: 182
Stem: 91
Level: 3
================================
[SOL] flip: 0, stem: 0, fault:1187. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
coverage: 30.495% pattern: 1 before: 364 now: 253
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:779. flip_cnt: 0, stem_cnt: 91, fault_cnt:96
coverage: 41.758% pattern: 2 before: 253 now: 212
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:792. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 53.297% pattern: 3 before: 212 now: 170
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:453. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 67.308% pattern: 4 before: 170 now: 119
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 68.407% pattern: 5 before: 119 now: 115
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 68.956% pattern: 6 before: 115 now: 113
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:361. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
coverage: 74.176% pattern: 7 before: 113 now: 94
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 76.923% pattern: 8 before: 94 now: 84
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 77.473% pattern: 9 before: 84 now: 82
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:135. flip_cnt: 0, stem_cnt: 91, fault_cnt:114
coverage: 79.945% pattern: 10 before: 82 now: 73
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 79.945% pattern: 10 before: 73 now: 73
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 81.044% pattern: 11 before: 73 now: 69
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 82.692% pattern: 12 before: 69 now: 63
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 83.242% pattern: 13 before: 63 now: 61
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 91, fault_cnt:113
coverage: 84.066% pattern: 14 before: 61 now: 58
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 84.066% pattern: 14 before: 58 now: 58
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 85.440% pattern: 15 before: 58 now: 53
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
coverage: 85.440% pattern: 15 before: 53 now: 53
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
coverage: 85.989% pattern: 16 before: 53 now: 51
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 85.989% pattern: 16 before: 51 now: 51
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 85.989% pattern: 16 before: 51 now: 51
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 91, fault_cnt:113
coverage: 89.011% pattern: 17 before: 51 now: 40
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 89.286% pattern: 18 before: 40 now: 39
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 91, fault_cnt:117
coverage: 89.560% pattern: 19 before: 39 now: 38
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
coverage: 89.560% pattern: 19 before: 38 now: 38
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:110
coverage: 89.560% pattern: 19 before: 38 now: 38
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:120
coverage: 89.560% pattern: 19 before: 38 now: 38
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 89.560% pattern: 19 before: 38 now: 38
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
coverage: 90.110% pattern: 20 before: 38 now: 36
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 90.110% pattern: 20 before: 36 now: 36
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
coverage: 90.110% pattern: 20 before: 36 now: 36
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 90.110% pattern: 20 before: 36 now: 36
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:118
coverage: 90.110% pattern: 20 before: 36 now: 36
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 91.209% pattern: 21 before: 36 now: 32
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
coverage: 91.209% pattern: 21 before: 32 now: 32
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 92.033% pattern: 22 before: 32 now: 29
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
coverage: 92.033% pattern: 22 before: 29 now: 29
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
coverage: 92.033% pattern: 22 before: 29 now: 29
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 92.033% pattern: 22 before: 29 now: 29
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 92.033% pattern: 22 before: 29 now: 29
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 93.407% pattern: 23 before: 29 now: 24
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
coverage: 93.407% pattern: 23 before: 24 now: 24
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:85
coverage: 93.407% pattern: 23 before: 24 now: 24
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:113
coverage: 93.407% pattern: 23 before: 24 now: 24
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 93.407% pattern: 23 before: 24 now: 24
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 93.956% pattern: 24 before: 24 now: 22
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:110
coverage: 93.956% pattern: 24 before: 22 now: 22
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 93.956% pattern: 24 before: 22 now: 22
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 93.956% pattern: 24 before: 22 now: 22
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:95
coverage: 93.956% pattern: 24 before: 22 now: 22
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 93.956% pattern: 24 before: 22 now: 22
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 93.956% pattern: 24 before: 22 now: 22
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 93.956% pattern: 24 before: 22 now: 22
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 94.505% pattern: 25 before: 22 now: 20
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:7. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 95.604% pattern: 26 before: 20 now: 16
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 95.604% pattern: 26 before: 16 now: 16
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 95.604% pattern: 26 before: 16 now: 16
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 95.604% pattern: 26 before: 16 now: 16
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 95.604% pattern: 26 before: 16 now: 16
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 95.604% pattern: 26 before: 16 now: 16
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 95.604% pattern: 26 before: 16 now: 16
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 95.604% pattern: 26 before: 16 now: 16
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:16. flip_cnt: 0, stem_cnt: 91, fault_cnt:115
coverage: 95.879% pattern: 27 before: 16 now: 15
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
coverage: 95.879% pattern: 27 before: 15 now: 15
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
coverage: 96.429% pattern: 28 before: 15 now: 13
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
coverage: 96.429% pattern: 28 before: 13 now: 13
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 96.429% pattern: 28 before: 13 now: 13
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 96.429% pattern: 28 before: 13 now: 13
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:89
coverage: 96.429% pattern: 28 before: 13 now: 13
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
coverage: 96.429% pattern: 28 before: 13 now: 13
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
coverage: 96.429% pattern: 28 before: 13 now: 13
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 96.429% pattern: 28 before: 13 now: 13
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 96.703% pattern: 29 before: 13 now: 12
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 96.703% pattern: 29 before: 12 now: 12
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:110
coverage: 96.703% pattern: 29 before: 12 now: 12
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:59. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
coverage: 98.077% pattern: 30 before: 12 now: 7
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:16. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
coverage: 98.626% pattern: 31 before: 7 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:115
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:94
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:114
coverage: 98.626% pattern: 31 before: 5 now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
coverage: 98.901% pattern: 32 before: 5 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:96
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:91
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:113
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:95
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:110
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:93
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:91
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
coverage: 98.901% pattern: 32 before: 4 now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:51. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
coverage: 100.000% pattern: 33 before: 4 now: 0
checking valid circuit ... result: 1.
real 0m36.403s
user 0m36.398s
sys 0m0.000s

1297
exp_result/ATPG-LS_b11.bench.txt Normal file
View File

File diff suppressed because it is too large Load Diff

10
exp_result/ATPG-LS_b12.bench.txt Normal file
View File

@ -0,0 +1,10 @@
make: 'atpg' is up to date.
========================
parsing file ./benchmark/b12.bench ... Done.
====== Circuit Statistics ======
PI: 126
PO: 127
Gate: 1039
Stem: 511
Level: 5
================================

364
exp_result/ATPG-LS_b13.bench.txt Normal file
View File

@ -0,0 +1,364 @@
make: 'atpg' is up to date.
========================
parsing file ./benchmark/b13.bench ... Done.
====== Circuit Statistics ======
PI: 63
PO: 63
Gate: 322
Stem: 187
Level: 3
================================
[SOL] flip: 0, stem: 0, fault:4104. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
coverage: 33.540% pattern: 1 before: 644 now: 428
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:2470. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
coverage: 53.727% pattern: 2 before: 428 now: 298
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1140. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
coverage: 63.043% pattern: 3 before: 298 now: 238
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:570. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
coverage: 67.702% pattern: 4 before: 238 now: 208
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:285. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
coverage: 70.031% pattern: 5 before: 208 now: 193
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
coverage: 71.739% pattern: 6 before: 193 now: 182
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
coverage: 72.360% pattern: 7 before: 182 now: 178
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
coverage: 74.068% pattern: 8 before: 178 now: 167
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
coverage: 75.932% pattern: 9 before: 167 now: 155
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:285. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
coverage: 78.261% pattern: 10 before: 155 now: 140
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
coverage: 78.571% pattern: 11 before: 140 now: 138
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
coverage: 78.571% pattern: 11 before: 138 now: 138
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
coverage: 79.814% pattern: 12 before: 138 now: 130
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
coverage: 80.590% pattern: 13 before: 130 now: 125
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
coverage: 81.832% pattern: 14 before: 125 now: 117
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
coverage: 81.832% pattern: 14 before: 117 now: 117
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
coverage: 81.832% pattern: 14 before: 117 now: 117
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
coverage: 83.385% pattern: 15 before: 117 now: 107
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
coverage: 83.385% pattern: 15 before: 107 now: 107
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
coverage: 84.317% pattern: 16 before: 107 now: 101
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
coverage: 85.093% pattern: 17 before: 101 now: 96
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
coverage: 85.248% pattern: 18 before: 96 now: 95
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
coverage: 85.248% pattern: 18 before: 95 now: 95
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
coverage: 85.248% pattern: 18 before: 95 now: 95
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
coverage: 85.714% pattern: 19 before: 95 now: 92
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
coverage: 85.714% pattern: 19 before: 92 now: 92
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
coverage: 85.714% pattern: 19 before: 92 now: 92
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
coverage: 85.714% pattern: 19 before: 92 now: 92
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
coverage: 85.714% pattern: 19 before: 92 now: 92
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
coverage: 86.646% pattern: 20 before: 92 now: 86
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
coverage: 86.646% pattern: 20 before: 86 now: 86
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
coverage: 86.646% pattern: 20 before: 86 now: 86
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
coverage: 86.646% pattern: 20 before: 86 now: 86
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
coverage: 86.646% pattern: 20 before: 86 now: 86
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
coverage: 86.646% pattern: 20 before: 86 now: 86
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
coverage: 86.646% pattern: 20 before: 86 now: 86
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:513. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
coverage: 90.839% pattern: 21 before: 86 now: 59
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
coverage: 90.839% pattern: 21 before: 59 now: 59
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
coverage: 90.839% pattern: 21 before: 59 now: 59
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
coverage: 90.839% pattern: 21 before: 59 now: 59
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
coverage: 91.770% pattern: 22 before: 59 now: 53
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
coverage: 91.925% pattern: 23 before: 53 now: 52
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
coverage: 91.925% pattern: 23 before: 52 now: 52
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
coverage: 91.925% pattern: 23 before: 52 now: 52
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
coverage: 91.925% pattern: 23 before: 52 now: 52
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
coverage: 91.925% pattern: 23 before: 52 now: 52
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
coverage: 91.925% pattern: 23 before: 52 now: 52
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
coverage: 91.925% pattern: 23 before: 52 now: 52
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
coverage: 91.925% pattern: 23 before: 52 now: 52
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
coverage: 91.925% pattern: 23 before: 52 now: 52
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
coverage: 91.925% pattern: 23 before: 52 now: 52
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
coverage: 91.925% pattern: 23 before: 52 now: 52
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
coverage: 91.925% pattern: 23 before: 52 now: 52
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
coverage: 91.925% pattern: 23 before: 52 now: 52
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
coverage: 91.925% pattern: 23 before: 52 now: 52
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
coverage: 91.925% pattern: 23 before: 52 now: 52
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
coverage: 91.925% pattern: 23 before: 52 now: 52
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:25. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
coverage: 92.702% pattern: 24 before: 52 now: 47
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
coverage: 92.702% pattern: 24 before: 47 now: 47
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
coverage: 92.702% pattern: 24 before: 47 now: 47
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
coverage: 92.702% pattern: 24 before: 47 now: 47
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
coverage: 92.702% pattern: 24 before: 47 now: 47
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
coverage: 92.857% pattern: 25 before: 47 now: 46
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
coverage: 92.857% pattern: 25 before: 46 now: 46
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
coverage: 92.857% pattern: 25 before: 46 now: 46
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
coverage: 93.012% pattern: 26 before: 46 now: 45
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
coverage: 93.012% pattern: 26 before: 45 now: 45
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
coverage: 93.012% pattern: 26 before: 45 now: 45
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
coverage: 93.012% pattern: 26 before: 45 now: 45
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
coverage: 93.012% pattern: 26 before: 45 now: 45
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
coverage: 93.012% pattern: 26 before: 45 now: 45
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
coverage: 93.012% pattern: 26 before: 45 now: 45
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
coverage: 93.012% pattern: 26 before: 45 now: 45
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
coverage: 93.012% pattern: 26 before: 45 now: 45
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
coverage: 93.168% pattern: 27 before: 45 now: 44
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
coverage: 93.323% pattern: 28 before: 44 now: 43
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
coverage: 93.789% pattern: 29 before: 43 now: 40
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
coverage: 93.789% pattern: 29 before: 40 now: 40
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:36. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
coverage: 94.099% pattern: 30 before: 40 now: 38
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
coverage: 94.255% pattern: 31 before: 38 now: 37
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
coverage: 94.255% pattern: 31 before: 37 now: 37
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
coverage: 94.410% pattern: 32 before: 37 now: 36
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
coverage: 94.410% pattern: 32 before: 36 now: 36
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
coverage: 94.410% pattern: 32 before: 36 now: 36
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
coverage: 94.410% pattern: 32 before: 36 now: 36
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
coverage: 94.410% pattern: 32 before: 36 now: 36
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
coverage: 94.410% pattern: 32 before: 36 now: 36
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
coverage: 94.410% pattern: 32 before: 36 now: 36
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
coverage: 94.410% pattern: 32 before: 36 now: 36
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
coverage: 94.410% pattern: 32 before: 36 now: 36
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
coverage: 95.186% pattern: 33 before: 36 now: 31
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
coverage: 95.186% pattern: 33 before: 31 now: 31
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
coverage: 95.186% pattern: 33 before: 31 now: 31
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
coverage: 95.186% pattern: 33 before: 31 now: 31
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
coverage: 95.186% pattern: 33 before: 31 now: 31
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
coverage: 95.186% pattern: 33 before: 31 now: 31
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
coverage: 95.186% pattern: 33 before: 31 now: 31
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
coverage: 95.186% pattern: 33 before: 31 now: 31
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
coverage: 95.186% pattern: 33 before: 31 now: 31
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
coverage: 95.186% pattern: 33 before: 31 now: 31
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
coverage: 95.186% pattern: 33 before: 31 now: 31
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
coverage: 95.186% pattern: 33 before: 31 now: 31
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
coverage: 95.186% pattern: 33 before: 31 now: 31
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
coverage: 95.186% pattern: 33 before: 31 now: 31
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
coverage: 95.186% pattern: 33 before: 31 now: 31
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
coverage: 95.342% pattern: 34 before: 31 now: 30
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
coverage: 95.342% pattern: 34 before: 30 now: 30
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
coverage: 95.342% pattern: 34 before: 30 now: 30
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
coverage: 95.342% pattern: 34 before: 30 now: 30
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
coverage: 95.342% pattern: 34 before: 30 now: 30
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
coverage: 95.342% pattern: 34 before: 30 now: 30
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
coverage: 95.342% pattern: 34 before: 30 now: 30
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
coverage: 95.342% pattern: 34 before: 30 now: 30
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
coverage: 95.342% pattern: 34 before: 30 now: 30
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
coverage: 95.342% pattern: 34 before: 30 now: 30
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
coverage: 95.342% pattern: 34 before: 30 now: 30
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
coverage: 95.342% pattern: 34 before: 30 now: 30
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
coverage: 95.652% pattern: 35 before: 30 now: 28
checking valid circuit ... result: 1.

10
exp_result/ATPG-LS_b17.bench.txt Normal file
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@ -0,0 +1,10 @@
make: 'atpg' is up to date.
========================
parsing file ./benchmark/b17.bench ... Done.
====== Circuit Statistics ======
PI: 1452
PO: 1512
Gate: 23710
Stem: 8257
Level: 7
================================

10
exp_result/ATPG-LS_b20.bench.txt Normal file
View File

@ -0,0 +1,10 @@
make: 'atpg' is up to date.
========================
parsing file ./benchmark/b20.bench ... Done.
====== Circuit Statistics ======
PI: 522
PO: 512
Gate: 8734
Stem: 3428
Level: 7
================================

10
exp_result/ATPG-LS_b21.bench.txt Normal file
View File

@ -0,0 +1,10 @@
make: 'atpg' is up to date.
========================
parsing file ./benchmark/b21.bench ... Done.
====== Circuit Statistics ======
PI: 522
PO: 512
Gate: 8995
Stem: 3647
Level: 8
================================

10
exp_result/ATPG-LS_b22.bench.txt Normal file
View File

@ -0,0 +1,10 @@
make: 'atpg' is up to date.
========================
parsing file ./benchmark/b22.bench ... Done.
====== Circuit Statistics ======
PI: 767
PO: 757
Gate: 13721
Stem: 5379
Level: 8
================================

44020
exp_result/ATPG-LS_c1355.bench.txt Normal file
View File

File diff suppressed because it is too large Load Diff

29
exp_result/ATPG-LS_c17.bench.txt Normal file
View File

@ -0,0 +1,29 @@
make: 'atpg' is up to date.
========================
parsing file ./benchmark/c17.bench ... Done.
====== Circuit Statistics ======
PI: 5
PO: 2
Gate: 11
Stem: 9
Level: 2
================================
[SOL] flip: 0, stem: 0, fault:8. flip_cnt: 0, stem_cnt: 9, fault_cnt:8
coverage: 36.364% pattern: 1 before: 22 now: 14
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 9, fault_cnt:9
coverage: 54.545% pattern: 2 before: 14 now: 10
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:18. flip_cnt: 0, stem_cnt: 9, fault_cnt:9
coverage: 90.909% pattern: 3 before: 10 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 9, fault_cnt:8
coverage: 90.909% pattern: 3 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:2. flip_cnt: 0, stem_cnt: 9, fault_cnt:6
coverage: 100.000% pattern: 4 before: 2 now: 0
checking valid circuit ... result: 1.
real 0m0.004s
user 0m0.002s
sys 0m0.000s

7669
exp_result/ATPG-LS_c1908.bench.txt Normal file
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File diff suppressed because it is too large Load Diff

346
exp_result/ATPG-LS_c2670.bench.txt Normal file
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@ -0,0 +1,346 @@
make: 'atpg' is up to date.
========================
parsing file ./benchmark/c2670.bench ... Done.
====== Circuit Statistics ======
PI: 233
PO: 140
Gate: 1426
Stem: 696
Level: 12
================================
[SOL] flip: 0, stem: 0, fault:13379. flip_cnt: 0, stem_cnt: 696, fault_cnt:707
coverage: 24.790% pattern: 1 before: 2852 now: 2145
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:5187. flip_cnt: 0, stem_cnt: 696, fault_cnt:536
coverage: 34.362% pattern: 2 before: 2145 now: 1872
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:6579. flip_cnt: 0, stem_cnt: 696, fault_cnt:707
coverage: 49.649% pattern: 3 before: 1872 now: 1436
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:2783. flip_cnt: 0, stem_cnt: 696, fault_cnt:723
coverage: 55.049% pattern: 4 before: 1436 now: 1282
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1520. flip_cnt: 0, stem_cnt: 696, fault_cnt:739
coverage: 57.854% pattern: 5 before: 1282 now: 1202
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:2871. flip_cnt: 0, stem_cnt: 696, fault_cnt:635
coverage: 63.359% pattern: 6 before: 1202 now: 1045
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:532. flip_cnt: 0, stem_cnt: 696, fault_cnt:487
coverage: 64.341% pattern: 7 before: 1045 now: 1017
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1444. flip_cnt: 0, stem_cnt: 696, fault_cnt:678
coverage: 67.006% pattern: 8 before: 1017 now: 941
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:475. flip_cnt: 0, stem_cnt: 696, fault_cnt:663
coverage: 67.882% pattern: 9 before: 941 now: 916
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1026. flip_cnt: 0, stem_cnt: 696, fault_cnt:639
coverage: 69.776% pattern: 10 before: 916 now: 862
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 696, fault_cnt:544
coverage: 70.161% pattern: 11 before: 862 now: 851
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 696, fault_cnt:545
coverage: 70.757% pattern: 12 before: 851 now: 834
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:523. flip_cnt: 0, stem_cnt: 696, fault_cnt:626
coverage: 71.844% pattern: 13 before: 834 now: 803
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:274. flip_cnt: 0, stem_cnt: 696, fault_cnt:513
coverage: 72.721% pattern: 14 before: 803 now: 778
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 696, fault_cnt:626
coverage: 73.107% pattern: 15 before: 778 now: 767
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:285. flip_cnt: 0, stem_cnt: 696, fault_cnt:615
coverage: 73.633% pattern: 16 before: 767 now: 752
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 696, fault_cnt:513
coverage: 74.053% pattern: 17 before: 752 now: 740
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 696, fault_cnt:733
coverage: 74.509% pattern: 18 before: 740 now: 727
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:244. flip_cnt: 0, stem_cnt: 696, fault_cnt:462
coverage: 75.070% pattern: 19 before: 727 now: 711
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 696, fault_cnt:563
coverage: 75.386% pattern: 20 before: 711 now: 702
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
coverage: 75.386% pattern: 20 before: 702 now: 702
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:619
coverage: 75.456% pattern: 21 before: 702 now: 700
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 696, fault_cnt:562
coverage: 75.596% pattern: 22 before: 700 now: 696
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 696, fault_cnt:534
coverage: 75.631% pattern: 23 before: 696 now: 695
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:439
coverage: 75.631% pattern: 23 before: 695 now: 695
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 696, fault_cnt:569
coverage: 75.842% pattern: 24 before: 695 now: 689
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 696, fault_cnt:694
coverage: 75.982% pattern: 25 before: 689 now: 685
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
coverage: 76.297% pattern: 26 before: 685 now: 676
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:342. flip_cnt: 0, stem_cnt: 696, fault_cnt:602
coverage: 76.928% pattern: 27 before: 676 now: 658
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:479
coverage: 76.928% pattern: 27 before: 658 now: 658
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:41. flip_cnt: 0, stem_cnt: 696, fault_cnt:604
coverage: 77.034% pattern: 28 before: 658 now: 655
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 696, fault_cnt:567
coverage: 77.174% pattern: 29 before: 655 now: 651
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:534
coverage: 77.174% pattern: 29 before: 651 now: 651
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:646
coverage: 77.174% pattern: 29 before: 651 now: 651
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:571
coverage: 77.244% pattern: 30 before: 651 now: 649
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:497
coverage: 77.244% pattern: 30 before: 649 now: 649
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 696, fault_cnt:540
coverage: 77.840% pattern: 31 before: 649 now: 632
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:594
coverage: 77.840% pattern: 31 before: 632 now: 632
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:479
coverage: 77.840% pattern: 31 before: 632 now: 632
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:557
coverage: 77.910% pattern: 32 before: 632 now: 630
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:490
coverage: 77.910% pattern: 32 before: 630 now: 630
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:442
coverage: 77.910% pattern: 32 before: 630 now: 630
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:494
coverage: 77.910% pattern: 32 before: 630 now: 630
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:568
coverage: 77.910% pattern: 32 before: 630 now: 630
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:630
coverage: 77.910% pattern: 32 before: 630 now: 630
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:501
coverage: 77.910% pattern: 32 before: 630 now: 630
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:476
coverage: 77.910% pattern: 32 before: 630 now: 630
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
coverage: 77.910% pattern: 32 before: 630 now: 630
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:399. flip_cnt: 0, stem_cnt: 696, fault_cnt:688
coverage: 78.647% pattern: 33 before: 630 now: 609
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:624
coverage: 78.647% pattern: 33 before: 609 now: 609
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:539
coverage: 78.647% pattern: 33 before: 609 now: 609
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:438
coverage: 78.647% pattern: 33 before: 609 now: 609
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 696, fault_cnt:588
coverage: 78.857% pattern: 34 before: 609 now: 603
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:521
coverage: 78.892% pattern: 35 before: 603 now: 602
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
coverage: 78.962% pattern: 36 before: 602 now: 600
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:475. flip_cnt: 0, stem_cnt: 696, fault_cnt:655
coverage: 79.839% pattern: 37 before: 600 now: 575
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:609
coverage: 79.839% pattern: 37 before: 575 now: 575
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:583
coverage: 79.874% pattern: 38 before: 575 now: 574
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 696, fault_cnt:756
coverage: 80.435% pattern: 39 before: 574 now: 558
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
coverage: 80.435% pattern: 39 before: 558 now: 558
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:771
coverage: 80.505% pattern: 40 before: 558 now: 556
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:609
coverage: 80.540% pattern: 41 before: 556 now: 555
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:523
coverage: 80.540% pattern: 41 before: 555 now: 555
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:655
coverage: 80.540% pattern: 41 before: 555 now: 555
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:629
coverage: 80.540% pattern: 41 before: 555 now: 555
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:671
coverage: 80.610% pattern: 42 before: 555 now: 553
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 696, fault_cnt:555
coverage: 80.891% pattern: 43 before: 553 now: 545
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:667
coverage: 80.891% pattern: 43 before: 545 now: 545
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:583
coverage: 80.891% pattern: 43 before: 545 now: 545
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:588
coverage: 80.891% pattern: 43 before: 545 now: 545
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:689
coverage: 80.891% pattern: 43 before: 545 now: 545
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:641
coverage: 80.891% pattern: 43 before: 545 now: 545
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:665
coverage: 80.891% pattern: 43 before: 545 now: 545
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:444
coverage: 80.891% pattern: 43 before: 545 now: 545
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:453
coverage: 80.891% pattern: 43 before: 545 now: 545
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:482
coverage: 80.891% pattern: 43 before: 545 now: 545
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:470
coverage: 80.891% pattern: 43 before: 545 now: 545
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:559
coverage: 80.891% pattern: 43 before: 545 now: 545
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 696, fault_cnt:609
coverage: 81.171% pattern: 44 before: 545 now: 537
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:611
coverage: 81.206% pattern: 45 before: 537 now: 536
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:581
coverage: 81.241% pattern: 46 before: 536 now: 535
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:681
coverage: 81.241% pattern: 46 before: 535 now: 535
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 696, fault_cnt:520
coverage: 81.452% pattern: 47 before: 535 now: 529
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:698
coverage: 81.452% pattern: 47 before: 529 now: 529
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:594
coverage: 81.452% pattern: 47 before: 529 now: 529
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:613
coverage: 81.487% pattern: 48 before: 529 now: 528
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:530
coverage: 81.487% pattern: 48 before: 528 now: 528
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:499
coverage: 81.487% pattern: 48 before: 528 now: 528
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 696, fault_cnt:541
coverage: 81.697% pattern: 49 before: 528 now: 522
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:641
coverage: 81.697% pattern: 49 before: 522 now: 522
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:436
coverage: 81.697% pattern: 49 before: 522 now: 522
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:678
coverage: 81.697% pattern: 49 before: 522 now: 522
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:596
coverage: 81.697% pattern: 49 before: 522 now: 522
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
coverage: 81.697% pattern: 49 before: 522 now: 522
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:568
coverage: 81.697% pattern: 49 before: 522 now: 522
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:715
coverage: 81.697% pattern: 49 before: 522 now: 522
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:531
coverage: 81.697% pattern: 49 before: 522 now: 522
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592
coverage: 81.697% pattern: 49 before: 522 now: 522
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:643
coverage: 81.697% pattern: 49 before: 522 now: 522
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:735
coverage: 81.697% pattern: 49 before: 522 now: 522
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 696, fault_cnt:643
coverage: 81.942% pattern: 50 before: 522 now: 515
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 696, fault_cnt:705
coverage: 82.153% pattern: 51 before: 515 now: 509
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:598
coverage: 82.153% pattern: 51 before: 509 now: 509
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:468
coverage: 82.153% pattern: 51 before: 509 now: 509
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:513
coverage: 82.188% pattern: 52 before: 509 now: 508
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:554
coverage: 82.188% pattern: 52 before: 508 now: 508
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:509
coverage: 82.188% pattern: 52 before: 508 now: 508
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:553
coverage: 82.188% pattern: 52 before: 508 now: 508
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:590
coverage: 82.188% pattern: 52 before: 508 now: 508
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:501
coverage: 82.188% pattern: 52 before: 508 now: 508
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 696, fault_cnt:560
coverage: 82.609% pattern: 53 before: 508 now: 496
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:693
coverage: 82.609% pattern: 53 before: 496 now: 496
checking valid circuit ... result: 1.

700
exp_result/ATPG-LS_c3540.bench.txt Normal file
View File

@ -0,0 +1,700 @@
make: 'atpg' is up to date.
========================
parsing file ./benchmark/c3540.bench ... Done.
====== Circuit Statistics ======
PI: 50
PO: 22
Gate: 1719
Stem: 605
Level: 14
================================
[SOL] flip: 0, stem: 0, fault:11041. flip_cnt: 0, stem_cnt: 605, fault_cnt:582
coverage: 16.928% pattern: 1 before: 3438 now: 2856
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:7292. flip_cnt: 0, stem_cnt: 605, fault_cnt:477
coverage: 28.272% pattern: 2 before: 2856 now: 2466
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:4577. flip_cnt: 0, stem_cnt: 605, fault_cnt:456
coverage: 35.340% pattern: 3 before: 2466 now: 2223
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:3730. flip_cnt: 0, stem_cnt: 605, fault_cnt:535
coverage: 41.245% pattern: 4 before: 2223 now: 2020
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:2679. flip_cnt: 0, stem_cnt: 605, fault_cnt:453
coverage: 45.346% pattern: 5 before: 2020 now: 1879
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:5093. flip_cnt: 0, stem_cnt: 605, fault_cnt:658
coverage: 53.170% pattern: 6 before: 1879 now: 1610
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1026. flip_cnt: 0, stem_cnt: 605, fault_cnt:305
coverage: 54.741% pattern: 7 before: 1610 now: 1556
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:418. flip_cnt: 0, stem_cnt: 605, fault_cnt:273
coverage: 55.381% pattern: 8 before: 1556 now: 1534
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1007. flip_cnt: 0, stem_cnt: 605, fault_cnt:396
coverage: 56.923% pattern: 9 before: 1534 now: 1481
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1672. flip_cnt: 0, stem_cnt: 605, fault_cnt:464
coverage: 59.482% pattern: 10 before: 1481 now: 1393
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 605, fault_cnt:328
coverage: 59.948% pattern: 11 before: 1393 now: 1377
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1045. flip_cnt: 0, stem_cnt: 605, fault_cnt:364
coverage: 61.547% pattern: 12 before: 1377 now: 1322
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:931. flip_cnt: 0, stem_cnt: 605, fault_cnt:435
coverage: 62.973% pattern: 13 before: 1322 now: 1273
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:437. flip_cnt: 0, stem_cnt: 605, fault_cnt:506
coverage: 63.642% pattern: 14 before: 1273 now: 1250
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 605, fault_cnt:304
coverage: 64.107% pattern: 15 before: 1250 now: 1234
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1843. flip_cnt: 0, stem_cnt: 605, fault_cnt:631
coverage: 66.928% pattern: 16 before: 1234 now: 1137
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 605, fault_cnt:479
coverage: 67.423% pattern: 17 before: 1137 now: 1120
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 605, fault_cnt:301
coverage: 67.685% pattern: 18 before: 1120 now: 1111
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:893. flip_cnt: 0, stem_cnt: 605, fault_cnt:475
coverage: 69.052% pattern: 19 before: 1111 now: 1064
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:316
coverage: 69.168% pattern: 20 before: 1064 now: 1060
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:570. flip_cnt: 0, stem_cnt: 605, fault_cnt:424
coverage: 70.041% pattern: 21 before: 1060 now: 1030
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:494. flip_cnt: 0, stem_cnt: 605, fault_cnt:507
coverage: 70.797% pattern: 22 before: 1030 now: 1004
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:684. flip_cnt: 0, stem_cnt: 605, fault_cnt:457
coverage: 71.844% pattern: 23 before: 1004 now: 968
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:342. flip_cnt: 0, stem_cnt: 605, fault_cnt:421
coverage: 72.368% pattern: 24 before: 968 now: 950
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1216. flip_cnt: 0, stem_cnt: 605, fault_cnt:488
coverage: 74.229% pattern: 25 before: 950 now: 886
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:684. flip_cnt: 0, stem_cnt: 605, fault_cnt:537
coverage: 75.276% pattern: 26 before: 886 now: 850
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:608. flip_cnt: 0, stem_cnt: 605, fault_cnt:571
coverage: 76.207% pattern: 27 before: 850 now: 818
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:513. flip_cnt: 0, stem_cnt: 605, fault_cnt:573
coverage: 76.992% pattern: 28 before: 818 now: 791
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 605, fault_cnt:642
coverage: 77.487% pattern: 29 before: 791 now: 774
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 605, fault_cnt:632
coverage: 77.778% pattern: 30 before: 774 now: 764
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:418. flip_cnt: 0, stem_cnt: 605, fault_cnt:401
coverage: 78.418% pattern: 31 before: 764 now: 742
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 605, fault_cnt:445
coverage: 78.505% pattern: 32 before: 742 now: 739
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 605, fault_cnt:567
coverage: 78.592% pattern: 33 before: 739 now: 736
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 605, fault_cnt:216
coverage: 78.738% pattern: 34 before: 736 now: 731
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:513
coverage: 78.738% pattern: 34 before: 731 now: 731
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:572
coverage: 78.738% pattern: 34 before: 731 now: 731
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:366
coverage: 78.738% pattern: 34 before: 731 now: 731
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:266. flip_cnt: 0, stem_cnt: 605, fault_cnt:480
coverage: 79.145% pattern: 35 before: 731 now: 717
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:380. flip_cnt: 0, stem_cnt: 605, fault_cnt:423
coverage: 79.727% pattern: 36 before: 717 now: 697
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 605, fault_cnt:458
coverage: 80.076% pattern: 37 before: 697 now: 685
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 605, fault_cnt:341
coverage: 80.163% pattern: 38 before: 685 now: 682
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 605, fault_cnt:506
coverage: 80.337% pattern: 39 before: 682 now: 676
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:361. flip_cnt: 0, stem_cnt: 605, fault_cnt:523
coverage: 80.890% pattern: 40 before: 676 now: 657
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:361. flip_cnt: 0, stem_cnt: 605, fault_cnt:479
coverage: 81.443% pattern: 41 before: 657 now: 638
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:469
coverage: 81.472% pattern: 42 before: 638 now: 637
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 605, fault_cnt:643
coverage: 81.617% pattern: 43 before: 637 now: 632
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:557
coverage: 81.617% pattern: 43 before: 632 now: 632
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 605, fault_cnt:455
coverage: 81.763% pattern: 44 before: 632 now: 627
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 605, fault_cnt:517
coverage: 81.850% pattern: 45 before: 627 now: 624
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 605, fault_cnt:520
coverage: 82.083% pattern: 46 before: 624 now: 616
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:396
coverage: 82.083% pattern: 46 before: 616 now: 616
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:539
coverage: 82.112% pattern: 47 before: 616 now: 615
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 605, fault_cnt:344
coverage: 82.315% pattern: 48 before: 615 now: 608
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 605, fault_cnt:478
coverage: 82.461% pattern: 49 before: 608 now: 603
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 605, fault_cnt:613
coverage: 82.752% pattern: 50 before: 603 now: 593
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:468
coverage: 82.752% pattern: 50 before: 593 now: 593
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 605, fault_cnt:454
coverage: 82.839% pattern: 51 before: 593 now: 590
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:328
coverage: 82.839% pattern: 51 before: 590 now: 590
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:451
coverage: 82.839% pattern: 51 before: 590 now: 590
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:402
coverage: 82.868% pattern: 52 before: 590 now: 589
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:369
coverage: 82.868% pattern: 52 before: 589 now: 589
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:434
coverage: 82.868% pattern: 52 before: 589 now: 589
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:539
coverage: 82.926% pattern: 53 before: 589 now: 587
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:489
coverage: 82.926% pattern: 53 before: 587 now: 587
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:465
coverage: 82.926% pattern: 53 before: 587 now: 587
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:367
coverage: 82.955% pattern: 54 before: 587 now: 586
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:371
coverage: 83.072% pattern: 55 before: 586 now: 582
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 605, fault_cnt:616
coverage: 83.537% pattern: 56 before: 582 now: 566
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:366
coverage: 83.566% pattern: 57 before: 566 now: 565
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:241
coverage: 83.566% pattern: 57 before: 565 now: 565
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:454
coverage: 83.595% pattern: 58 before: 565 now: 564
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:394
coverage: 83.595% pattern: 58 before: 564 now: 564
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:469
coverage: 83.595% pattern: 58 before: 564 now: 564
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:266. flip_cnt: 0, stem_cnt: 605, fault_cnt:442
coverage: 84.002% pattern: 59 before: 564 now: 550
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:510
coverage: 84.002% pattern: 59 before: 550 now: 550
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:447
coverage: 84.002% pattern: 59 before: 550 now: 550
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 605, fault_cnt:503
coverage: 84.264% pattern: 60 before: 550 now: 541
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:191
coverage: 84.264% pattern: 60 before: 541 now: 541
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:337
coverage: 84.264% pattern: 60 before: 541 now: 541
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:532. flip_cnt: 0, stem_cnt: 605, fault_cnt:413
coverage: 85.079% pattern: 61 before: 541 now: 513
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:569
coverage: 85.195% pattern: 62 before: 513 now: 509
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:529
coverage: 85.224% pattern: 63 before: 509 now: 508
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:293
coverage: 85.224% pattern: 63 before: 508 now: 508
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:306
coverage: 85.224% pattern: 63 before: 508 now: 508
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:516
coverage: 85.282% pattern: 64 before: 508 now: 506
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:290
coverage: 85.311% pattern: 65 before: 506 now: 505
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:451
coverage: 85.311% pattern: 65 before: 505 now: 505
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:532
coverage: 85.311% pattern: 65 before: 505 now: 505
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:309
coverage: 85.311% pattern: 65 before: 505 now: 505
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:480
coverage: 85.311% pattern: 65 before: 505 now: 505
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:333
coverage: 85.340% pattern: 66 before: 505 now: 504
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 605, fault_cnt:507
coverage: 85.573% pattern: 67 before: 504 now: 496
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:423
coverage: 85.573% pattern: 67 before: 496 now: 496
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:429
coverage: 85.573% pattern: 67 before: 496 now: 496
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:483
coverage: 85.573% pattern: 67 before: 496 now: 496
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 605, fault_cnt:551
coverage: 85.718% pattern: 68 before: 496 now: 491
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:425
coverage: 85.748% pattern: 69 before: 491 now: 490
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:285
coverage: 85.748% pattern: 69 before: 490 now: 490
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 605, fault_cnt:385
coverage: 86.009% pattern: 70 before: 490 now: 481
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:415
coverage: 86.009% pattern: 70 before: 481 now: 481
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:288
coverage: 86.009% pattern: 70 before: 481 now: 481
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 605, fault_cnt:490
coverage: 86.097% pattern: 71 before: 481 now: 478
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:380. flip_cnt: 0, stem_cnt: 605, fault_cnt:396
coverage: 86.678% pattern: 72 before: 478 now: 458
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:467
coverage: 86.678% pattern: 72 before: 458 now: 458
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 605, fault_cnt:451
coverage: 86.969% pattern: 73 before: 458 now: 448
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:387
coverage: 86.969% pattern: 73 before: 448 now: 448
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:127
coverage: 86.969% pattern: 73 before: 448 now: 448
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:453
coverage: 86.998% pattern: 74 before: 448 now: 447
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:591
coverage: 86.998% pattern: 74 before: 447 now: 447
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:481
coverage: 86.998% pattern: 74 before: 447 now: 447
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:544
coverage: 86.998% pattern: 74 before: 447 now: 447
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:450
coverage: 86.998% pattern: 74 before: 447 now: 447
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 605, fault_cnt:307
coverage: 87.260% pattern: 75 before: 447 now: 438
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:508
coverage: 87.289% pattern: 76 before: 438 now: 437
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:572
coverage: 87.289% pattern: 76 before: 437 now: 437
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:404
coverage: 87.289% pattern: 76 before: 437 now: 437
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:565
coverage: 87.289% pattern: 76 before: 437 now: 437
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:387
coverage: 87.405% pattern: 77 before: 437 now: 433
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:604
coverage: 87.405% pattern: 77 before: 433 now: 433
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:567
coverage: 87.405% pattern: 77 before: 433 now: 433
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:602
coverage: 87.522% pattern: 78 before: 433 now: 429
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:522
coverage: 87.522% pattern: 78 before: 429 now: 429
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:400
coverage: 87.522% pattern: 78 before: 429 now: 429
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:537
coverage: 87.522% pattern: 78 before: 429 now: 429
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:551
coverage: 87.522% pattern: 78 before: 429 now: 429
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:383
coverage: 87.580% pattern: 79 before: 429 now: 427
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:473
coverage: 87.580% pattern: 79 before: 427 now: 427
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:336
coverage: 87.580% pattern: 79 before: 427 now: 427
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:512
coverage: 87.580% pattern: 79 before: 427 now: 427
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:432
coverage: 87.580% pattern: 79 before: 427 now: 427
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:499
coverage: 87.580% pattern: 79 before: 427 now: 427
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:475
coverage: 87.580% pattern: 79 before: 427 now: 427
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:257
coverage: 87.580% pattern: 79 before: 427 now: 427
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:239
coverage: 87.580% pattern: 79 before: 427 now: 427
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:526
coverage: 87.580% pattern: 79 before: 427 now: 427
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:377
coverage: 87.580% pattern: 79 before: 427 now: 427
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:495
coverage: 87.580% pattern: 79 before: 427 now: 427
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:520
coverage: 87.638% pattern: 80 before: 427 now: 425
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 605, fault_cnt:529
coverage: 87.842% pattern: 81 before: 425 now: 418
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:318
coverage: 87.842% pattern: 81 before: 418 now: 418
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:370
coverage: 87.842% pattern: 81 before: 418 now: 418
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:334
coverage: 87.842% pattern: 81 before: 418 now: 418
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:484
coverage: 87.842% pattern: 81 before: 418 now: 418
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:228
coverage: 87.842% pattern: 81 before: 418 now: 418
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:510
coverage: 87.842% pattern: 81 before: 418 now: 418
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:292
coverage: 87.842% pattern: 81 before: 418 now: 418
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 605, fault_cnt:586
coverage: 88.191% pattern: 82 before: 418 now: 406
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:341
coverage: 88.191% pattern: 82 before: 406 now: 406
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:315
coverage: 88.191% pattern: 82 before: 406 now: 406
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:451
coverage: 88.191% pattern: 82 before: 406 now: 406
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 605, fault_cnt:393
coverage: 88.336% pattern: 83 before: 406 now: 401
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:483
coverage: 88.336% pattern: 83 before: 401 now: 401
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 605, fault_cnt:602
coverage: 88.598% pattern: 84 before: 401 now: 392
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:308
coverage: 88.598% pattern: 84 before: 392 now: 392
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:552
coverage: 88.598% pattern: 84 before: 392 now: 392
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:427
coverage: 88.598% pattern: 84 before: 392 now: 392
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:392
coverage: 88.627% pattern: 85 before: 392 now: 391
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:436
coverage: 88.627% pattern: 85 before: 391 now: 391
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:576
coverage: 88.627% pattern: 85 before: 391 now: 391
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:523
coverage: 88.627% pattern: 85 before: 391 now: 391
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:518
coverage: 88.627% pattern: 85 before: 391 now: 391
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:558
coverage: 88.627% pattern: 85 before: 391 now: 391
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:459
coverage: 88.656% pattern: 86 before: 391 now: 390
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:401
coverage: 88.656% pattern: 86 before: 390 now: 390
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:488
coverage: 88.656% pattern: 86 before: 390 now: 390
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:369
coverage: 88.656% pattern: 86 before: 390 now: 390
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:253
coverage: 88.656% pattern: 86 before: 390 now: 390
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:530
coverage: 88.656% pattern: 86 before: 390 now: 390
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:559
coverage: 88.656% pattern: 86 before: 390 now: 390
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:499
coverage: 88.656% pattern: 86 before: 390 now: 390
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:236
coverage: 88.656% pattern: 86 before: 390 now: 390
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:634
coverage: 88.714% pattern: 87 before: 390 now: 388
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:478
coverage: 88.714% pattern: 87 before: 388 now: 388
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:269
coverage: 88.714% pattern: 87 before: 388 now: 388
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 605, fault_cnt:519
coverage: 89.005% pattern: 88 before: 388 now: 378
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:484
coverage: 89.005% pattern: 88 before: 378 now: 378
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:461
coverage: 89.005% pattern: 88 before: 378 now: 378
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:447
coverage: 89.005% pattern: 88 before: 378 now: 378
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:461
coverage: 89.005% pattern: 88 before: 378 now: 378
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:504
coverage: 89.005% pattern: 88 before: 378 now: 378
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:488
coverage: 89.005% pattern: 88 before: 378 now: 378
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:314
coverage: 89.005% pattern: 88 before: 378 now: 378
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:460
coverage: 89.005% pattern: 88 before: 378 now: 378
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:285
coverage: 89.005% pattern: 88 before: 378 now: 378
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:473
coverage: 89.005% pattern: 88 before: 378 now: 378
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:626
coverage: 89.005% pattern: 88 before: 378 now: 378
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:495
coverage: 89.005% pattern: 88 before: 378 now: 378
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:600
coverage: 89.005% pattern: 88 before: 378 now: 378
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:520
coverage: 89.005% pattern: 88 before: 378 now: 378
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:595
coverage: 89.005% pattern: 88 before: 378 now: 378
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:464
coverage: 89.005% pattern: 88 before: 378 now: 378
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:460
coverage: 89.005% pattern: 88 before: 378 now: 378
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:272
coverage: 89.005% pattern: 88 before: 378 now: 378
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:459
coverage: 89.005% pattern: 88 before: 378 now: 378
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:342. flip_cnt: 0, stem_cnt: 605, fault_cnt:416
coverage: 89.529% pattern: 89 before: 378 now: 360
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:578
coverage: 89.587% pattern: 90 before: 360 now: 358
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:423
coverage: 89.616% pattern: 91 before: 358 now: 357
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:443
coverage: 89.616% pattern: 91 before: 357 now: 357
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:377
coverage: 89.616% pattern: 91 before: 357 now: 357
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:342
coverage: 89.732% pattern: 92 before: 357 now: 353
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:249
coverage: 89.732% pattern: 92 before: 353 now: 353
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:343
coverage: 89.732% pattern: 92 before: 353 now: 353
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:508
coverage: 89.732% pattern: 92 before: 353 now: 353
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:486
coverage: 89.791% pattern: 93 before: 353 now: 351
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:477
coverage: 89.791% pattern: 93 before: 351 now: 351
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:359
coverage: 89.791% pattern: 93 before: 351 now: 351
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:279
coverage: 89.791% pattern: 93 before: 351 now: 351
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:502
coverage: 89.791% pattern: 93 before: 351 now: 351
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:539
coverage: 89.791% pattern: 93 before: 351 now: 351
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:562
coverage: 89.791% pattern: 93 before: 351 now: 351
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:452
coverage: 89.791% pattern: 93 before: 351 now: 351
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:516
coverage: 89.791% pattern: 93 before: 351 now: 351
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:463
coverage: 89.791% pattern: 93 before: 351 now: 351
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:423
coverage: 89.791% pattern: 93 before: 351 now: 351
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:532
coverage: 89.791% pattern: 93 before: 351 now: 351
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:269
coverage: 89.791% pattern: 93 before: 351 now: 351
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:499
coverage: 89.791% pattern: 93 before: 351 now: 351
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:474
coverage: 89.791% pattern: 93 before: 351 now: 351
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:360
coverage: 89.791% pattern: 93 before: 351 now: 351
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:283
coverage: 89.791% pattern: 93 before: 351 now: 351
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:313
coverage: 89.820% pattern: 94 before: 351 now: 350
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:507
coverage: 89.820% pattern: 94 before: 350 now: 350
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 605, fault_cnt:430
coverage: 90.081% pattern: 95 before: 350 now: 341
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:374
coverage: 90.081% pattern: 95 before: 341 now: 341
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:487
coverage: 90.081% pattern: 95 before: 341 now: 341
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:522
coverage: 90.081% pattern: 95 before: 341 now: 341
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 605, fault_cnt:395
coverage: 90.169% pattern: 96 before: 341 now: 338
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:377
coverage: 90.169% pattern: 96 before: 338 now: 338
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:293
coverage: 90.169% pattern: 96 before: 338 now: 338
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:545
coverage: 90.169% pattern: 96 before: 338 now: 338
checking valid circuit ... result: 1.

88111
exp_result/ATPG-LS_c432.bench.txt Normal file
View File

File diff suppressed because it is too large Load Diff

19187
exp_result/ATPG-LS_c499.bench.txt Normal file
View File

File diff suppressed because it is too large Load Diff

10
exp_result/ATPG-LS_c5315.bench.txt Normal file
View File

@ -0,0 +1,10 @@
make: 'atpg' is up to date.
========================
parsing file ./benchmark/c5315.bench ... Done.
====== Circuit Statistics ======
PI: 178
PO: 123
Gate: 2485
Stem: 984
Level: 10
================================

619
exp_result/ATPG-LS_c6288.bench.txt Normal file
View File

@ -0,0 +1,619 @@
make: 'atpg' is up to date.
========================
parsing file ./benchmark/c6288.bench ... Done.
====== Circuit Statistics ======
PI: 32
PO: 32
Gate: 2448
Stem: 1488
Level: 7
================================
[SOL] flip: 0, stem: 0, fault:41910. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2217
coverage: 45.282% pattern: 1 before: 4896 now: 2679
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:21592. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2201
coverage: 68.566% pattern: 2 before: 2679 now: 1539
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:11922. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2206
coverage: 81.536% pattern: 3 before: 1539 now: 904
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:5196. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2188
coverage: 87.132% pattern: 4 before: 904 now: 630
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:4078. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2182
coverage: 91.585% pattern: 5 before: 630 now: 412
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1786. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2182
coverage: 93.505% pattern: 6 before: 412 now: 318
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1178. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2177
coverage: 94.771% pattern: 7 before: 318 now: 256
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:798. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197
coverage: 95.629% pattern: 8 before: 256 now: 214
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:646. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193
coverage: 96.324% pattern: 9 before: 214 now: 180
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1026. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2145
coverage: 97.426% pattern: 10 before: 180 now: 126
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:437. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193
coverage: 97.896% pattern: 11 before: 126 now: 103
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2206
coverage: 98.019% pattern: 12 before: 103 now: 97
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
coverage: 98.223% pattern: 13 before: 97 now: 87
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196
coverage: 98.448% pattern: 14 before: 87 now: 76
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:285. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194
coverage: 98.754% pattern: 15 before: 76 now: 61
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2180
coverage: 99.020% pattern: 16 before: 61 now: 48
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2174
coverage: 99.183% pattern: 17 before: 48 now: 40
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194
coverage: 99.244% pattern: 18 before: 40 now: 37
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2188
coverage: 99.306% pattern: 19 before: 37 now: 34
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2185
coverage: 99.367% pattern: 20 before: 34 now: 31
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2168
coverage: 99.449% pattern: 21 before: 31 now: 27
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
coverage: 99.469% pattern: 22 before: 27 now: 26
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197
coverage: 99.489% pattern: 23 before: 26 now: 25
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2160
coverage: 99.510% pattern: 24 before: 25 now: 24
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
coverage: 99.510% pattern: 24 before: 24 now: 24
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2186
coverage: 99.571% pattern: 25 before: 24 now: 21
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
coverage: 99.571% pattern: 25 before: 21 now: 21
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
coverage: 99.571% pattern: 25 before: 21 now: 21
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2185
coverage: 99.571% pattern: 25 before: 21 now: 21
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
coverage: 99.632% pattern: 26 before: 21 now: 18
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2201
coverage: 99.632% pattern: 26 before: 18 now: 18
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2202
coverage: 99.632% pattern: 26 before: 18 now: 18
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2199
coverage: 99.653% pattern: 27 before: 18 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2165
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2175
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2175
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2167
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2188
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2178
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2181
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2177
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2158
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2166
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2201
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2185
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2169
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2186
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2182
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2180
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2211
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2205
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2182
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2165
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2202
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2182
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2187
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2201
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2206
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2190
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2175
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2184
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2221
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2178
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2201
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2165
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2176
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2190
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2173
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2182
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2188
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2157
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2185
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2170
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2209
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2204
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2229
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2215
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2186
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2200
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2204
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2179
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2177
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2173
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2203
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2198
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2198
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2180
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2161
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2173
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2179
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2162
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2181
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2188
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2199
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2185
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2200
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2178
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2164
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2199
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2187
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2190
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2186
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2185
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2171
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2167
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2163
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2202
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2199
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2198
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2184
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2163
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2178
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2202
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2164
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2190
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2174
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2182
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2216
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2198
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2205
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2176
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2204
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2201
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2205
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2210
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2187
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2178
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2212
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2200
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2188
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2200
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2184
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2210
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2182
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2210
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2177
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2187
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2165
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2199
coverage: 99.653% pattern: 27 before: 17 now: 17
checking valid circuit ... result: 1.

670
exp_result/ATPG-LS_c7552.bench.txt Normal file
View File

@ -0,0 +1,670 @@
make: 'atpg' is up to date.
========================
parsing file ./benchmark/c7552.bench ... Done.
====== Circuit Statistics ======
PI: 207
PO: 108
Gate: 3719
Stem: 1537
Level: 10
================================
[SOL] flip: 0, stem: 0, fault:31574. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1667
coverage: 22.412% pattern: 1 before: 7438 now: 5771
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:23913. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1701
coverage: 40.656% pattern: 2 before: 5771 now: 4414
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:13051. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1593
coverage: 50.094% pattern: 3 before: 4414 now: 3712
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:5949. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1503
coverage: 54.329% pattern: 4 before: 3712 now: 3397
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:6654. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1561
coverage: 59.196% pattern: 5 before: 3397 now: 3035
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:4089. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1580
coverage: 62.140% pattern: 6 before: 3035 now: 2816
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:3109. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1443
coverage: 64.372% pattern: 7 before: 2816 now: 2650
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:6042. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1750
coverage: 68.647% pattern: 8 before: 2650 now: 2332
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:4459. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1716
coverage: 71.847% pattern: 9 before: 2332 now: 2094
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1653. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1483
coverage: 73.017% pattern: 10 before: 2094 now: 2007
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1121. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1430
coverage: 73.810% pattern: 11 before: 2007 now: 1948
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:7467. flip_cnt: 0, stem_cnt: 1537, fault_cnt:2099
coverage: 79.094% pattern: 12 before: 1948 now: 1555
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:950. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1522
coverage: 79.766% pattern: 13 before: 1555 now: 1505
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:950. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1594
coverage: 80.438% pattern: 14 before: 1505 now: 1455
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1676. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1648
coverage: 81.675% pattern: 15 before: 1455 now: 1363
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:951. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1561
coverage: 82.361% pattern: 16 before: 1363 now: 1312
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1634. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1681
coverage: 83.517% pattern: 17 before: 1312 now: 1226
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:741. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1450
coverage: 84.041% pattern: 18 before: 1226 now: 1187
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1442
coverage: 84.136% pattern: 19 before: 1187 now: 1180
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1453
coverage: 84.364% pattern: 20 before: 1180 now: 1163
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:855. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1559
coverage: 84.969% pattern: 21 before: 1163 now: 1118
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1178. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1681
coverage: 85.803% pattern: 22 before: 1118 now: 1056
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1426
coverage: 85.803% pattern: 22 before: 1056 now: 1056
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1007. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1759
coverage: 86.515% pattern: 23 before: 1056 now: 1003
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1412
coverage: 86.636% pattern: 24 before: 1003 now: 994
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1487
coverage: 86.650% pattern: 25 before: 994 now: 993
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:437. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1565
coverage: 86.959% pattern: 26 before: 993 now: 970
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1483
coverage: 86.986% pattern: 27 before: 970 now: 968
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1410
coverage: 87.161% pattern: 28 before: 968 now: 955
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:589. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1582
coverage: 87.577% pattern: 29 before: 955 now: 924
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1482
coverage: 87.591% pattern: 30 before: 924 now: 923
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:475. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1508
coverage: 87.927% pattern: 31 before: 923 now: 898
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1509
coverage: 87.981% pattern: 32 before: 898 now: 894
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1609
coverage: 88.196% pattern: 33 before: 894 now: 878
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:456. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1494
coverage: 88.518% pattern: 34 before: 878 now: 854
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:1064. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1930
coverage: 89.271% pattern: 35 before: 854 now: 798
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:418. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1542
coverage: 89.567% pattern: 36 before: 798 now: 776
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:380. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1546
coverage: 89.836% pattern: 37 before: 776 now: 756
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:285. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1877
coverage: 90.038% pattern: 38 before: 756 now: 741
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1523
coverage: 90.266% pattern: 39 before: 741 now: 724
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1468
coverage: 90.266% pattern: 39 before: 724 now: 724
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:456. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1836
coverage: 90.589% pattern: 40 before: 724 now: 700
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1527
coverage: 90.643% pattern: 41 before: 700 now: 696
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:399. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1632
coverage: 90.925% pattern: 42 before: 696 now: 675
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:741. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1829
coverage: 91.449% pattern: 43 before: 675 now: 636
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1530
coverage: 91.517% pattern: 44 before: 636 now: 631
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1653
coverage: 91.543% pattern: 45 before: 631 now: 629
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1950
coverage: 91.772% pattern: 46 before: 629 now: 612
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1503
coverage: 91.812% pattern: 47 before: 612 now: 609
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1534
coverage: 91.853% pattern: 48 before: 609 now: 606
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1537
coverage: 91.960% pattern: 49 before: 606 now: 598
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1579
coverage: 91.974% pattern: 50 before: 598 now: 597
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1551
coverage: 91.974% pattern: 50 before: 597 now: 597
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1645
coverage: 92.001% pattern: 51 before: 597 now: 595
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1465
coverage: 92.001% pattern: 51 before: 595 now: 595
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1585
coverage: 92.108% pattern: 52 before: 595 now: 587
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1862
coverage: 92.135% pattern: 53 before: 587 now: 585
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1505
coverage: 92.202% pattern: 54 before: 585 now: 580
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1486
coverage: 92.283% pattern: 55 before: 580 now: 574
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1435
coverage: 92.283% pattern: 55 before: 574 now: 574
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1423
coverage: 92.350% pattern: 56 before: 574 now: 569
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1763
coverage: 92.404% pattern: 57 before: 569 now: 565
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1868
coverage: 92.511% pattern: 58 before: 565 now: 557
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1436
coverage: 92.511% pattern: 58 before: 557 now: 557
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1419
coverage: 92.511% pattern: 58 before: 557 now: 557
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1666
coverage: 92.525% pattern: 59 before: 557 now: 556
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1564
coverage: 92.552% pattern: 60 before: 556 now: 554
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1516
coverage: 92.606% pattern: 61 before: 554 now: 550
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1655
coverage: 92.673% pattern: 62 before: 550 now: 545
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1607
coverage: 92.673% pattern: 62 before: 545 now: 545
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:475. flip_cnt: 0, stem_cnt: 1537, fault_cnt:2158
coverage: 93.009% pattern: 63 before: 545 now: 520
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1497
coverage: 93.036% pattern: 64 before: 520 now: 518
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1658
coverage: 93.076% pattern: 65 before: 518 now: 515
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1833
coverage: 93.076% pattern: 65 before: 515 now: 515
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1470
coverage: 93.076% pattern: 65 before: 515 now: 515
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1603
coverage: 93.170% pattern: 66 before: 515 now: 508
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1562
coverage: 93.197% pattern: 67 before: 508 now: 506
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1866
coverage: 93.197% pattern: 67 before: 506 now: 506
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1837
coverage: 93.211% pattern: 68 before: 506 now: 505
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1634
coverage: 93.278% pattern: 69 before: 505 now: 500
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1725
coverage: 93.318% pattern: 70 before: 500 now: 497
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1582
coverage: 93.332% pattern: 71 before: 497 now: 496
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1477
coverage: 93.332% pattern: 71 before: 496 now: 496
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1427
coverage: 93.332% pattern: 71 before: 496 now: 496
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1645
coverage: 93.332% pattern: 71 before: 496 now: 496
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1462
coverage: 93.332% pattern: 71 before: 496 now: 496
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1796
coverage: 93.332% pattern: 71 before: 496 now: 496
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1657
coverage: 93.439% pattern: 72 before: 496 now: 488
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1473
coverage: 93.439% pattern: 72 before: 488 now: 488
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1526
coverage: 93.439% pattern: 72 before: 488 now: 488
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1571
coverage: 93.439% pattern: 72 before: 488 now: 488
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1449
coverage: 93.439% pattern: 72 before: 488 now: 488
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1583
coverage: 93.439% pattern: 72 before: 488 now: 488
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1499
coverage: 93.439% pattern: 72 before: 488 now: 488
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1690
coverage: 93.560% pattern: 73 before: 488 now: 479
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1587
coverage: 93.614% pattern: 74 before: 479 now: 475
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1543
coverage: 93.614% pattern: 74 before: 475 now: 475
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1457
coverage: 93.614% pattern: 74 before: 475 now: 475
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1513
coverage: 93.654% pattern: 75 before: 475 now: 472
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1425
coverage: 93.654% pattern: 75 before: 472 now: 472
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1876
coverage: 93.708% pattern: 76 before: 472 now: 468
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1778
coverage: 93.708% pattern: 76 before: 468 now: 468
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1431
coverage: 93.721% pattern: 77 before: 468 now: 467
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1483
coverage: 93.775% pattern: 78 before: 467 now: 463
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1481
coverage: 93.802% pattern: 79 before: 463 now: 461
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1592
coverage: 93.802% pattern: 79 before: 461 now: 461
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1804
coverage: 93.802% pattern: 79 before: 461 now: 461
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1605
coverage: 93.816% pattern: 80 before: 461 now: 460
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1668
coverage: 93.842% pattern: 81 before: 460 now: 458
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1840
coverage: 93.842% pattern: 81 before: 458 now: 458
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1441
coverage: 93.842% pattern: 81 before: 458 now: 458
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1662
coverage: 93.869% pattern: 82 before: 458 now: 456
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1452
coverage: 93.869% pattern: 82 before: 456 now: 456
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1448
coverage: 93.869% pattern: 82 before: 456 now: 456
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1592
coverage: 93.869% pattern: 82 before: 456 now: 456
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1529
coverage: 93.869% pattern: 82 before: 456 now: 456
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1575
coverage: 93.896% pattern: 83 before: 456 now: 454
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1555
coverage: 93.896% pattern: 83 before: 454 now: 454
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1503
coverage: 93.896% pattern: 83 before: 454 now: 454
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1606
coverage: 93.896% pattern: 83 before: 454 now: 454
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1529
coverage: 93.923% pattern: 84 before: 454 now: 452
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1572
coverage: 93.923% pattern: 84 before: 452 now: 452
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1506
coverage: 93.923% pattern: 84 before: 452 now: 452
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1544
coverage: 94.152% pattern: 85 before: 452 now: 435
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1441
coverage: 94.152% pattern: 85 before: 435 now: 435
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1487
coverage: 94.152% pattern: 85 before: 435 now: 435
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1572
coverage: 94.152% pattern: 85 before: 435 now: 435
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1944
coverage: 94.367% pattern: 86 before: 435 now: 419
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1555
coverage: 94.367% pattern: 86 before: 419 now: 419
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1453
coverage: 94.367% pattern: 86 before: 419 now: 419
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1828
coverage: 94.367% pattern: 86 before: 419 now: 419
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1570
coverage: 94.407% pattern: 87 before: 419 now: 416
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1760
coverage: 94.434% pattern: 88 before: 416 now: 414
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1478
coverage: 94.434% pattern: 88 before: 414 now: 414
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1486
coverage: 94.434% pattern: 88 before: 414 now: 414
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1478
coverage: 94.474% pattern: 89 before: 414 now: 411
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1512
coverage: 94.474% pattern: 89 before: 411 now: 411
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1463
coverage: 94.474% pattern: 89 before: 411 now: 411
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1469
coverage: 94.474% pattern: 89 before: 411 now: 411
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1621
coverage: 94.474% pattern: 89 before: 411 now: 411
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1658
coverage: 94.474% pattern: 89 before: 411 now: 411
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1428
coverage: 94.474% pattern: 89 before: 411 now: 411
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1568
coverage: 94.474% pattern: 89 before: 411 now: 411
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1868
coverage: 94.474% pattern: 89 before: 411 now: 411
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1593
coverage: 94.568% pattern: 90 before: 411 now: 404
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1520
coverage: 94.568% pattern: 90 before: 404 now: 404
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1638
coverage: 94.568% pattern: 90 before: 404 now: 404
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1527
coverage: 94.568% pattern: 90 before: 404 now: 404
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1458
coverage: 94.568% pattern: 90 before: 404 now: 404
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1534
coverage: 94.568% pattern: 90 before: 404 now: 404
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1876
coverage: 94.568% pattern: 90 before: 404 now: 404
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1561
coverage: 94.568% pattern: 90 before: 404 now: 404
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1502
coverage: 94.595% pattern: 91 before: 404 now: 402
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1616
coverage: 94.595% pattern: 91 before: 402 now: 402
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1494
coverage: 94.622% pattern: 92 before: 402 now: 400
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1868
coverage: 94.622% pattern: 92 before: 400 now: 400
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1746
coverage: 94.622% pattern: 92 before: 400 now: 400
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1537
coverage: 94.622% pattern: 92 before: 400 now: 400
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1514
coverage: 94.622% pattern: 92 before: 400 now: 400
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1484
coverage: 94.622% pattern: 92 before: 400 now: 400
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1627
coverage: 94.622% pattern: 92 before: 400 now: 400
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1566
coverage: 94.649% pattern: 93 before: 400 now: 398
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1472
coverage: 94.649% pattern: 93 before: 398 now: 398
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1931
coverage: 94.824% pattern: 94 before: 398 now: 385
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1464
coverage: 94.824% pattern: 94 before: 385 now: 385
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1535
coverage: 94.824% pattern: 94 before: 385 now: 385
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1591
coverage: 94.824% pattern: 94 before: 385 now: 385
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1606
coverage: 94.824% pattern: 94 before: 385 now: 385
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1452
coverage: 94.824% pattern: 94 before: 385 now: 385
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1820
coverage: 94.851% pattern: 95 before: 385 now: 383
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1717
coverage: 94.864% pattern: 96 before: 383 now: 382
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1742
coverage: 94.878% pattern: 97 before: 382 now: 381
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1474
coverage: 94.878% pattern: 97 before: 381 now: 381
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1878
coverage: 94.878% pattern: 97 before: 381 now: 381
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1513
coverage: 94.878% pattern: 97 before: 381 now: 381
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1577
coverage: 94.878% pattern: 97 before: 381 now: 381
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1897
coverage: 94.878% pattern: 97 before: 381 now: 381
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1576
coverage: 94.878% pattern: 97 before: 381 now: 381
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1483
coverage: 94.878% pattern: 97 before: 381 now: 381
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1607
coverage: 94.878% pattern: 97 before: 381 now: 381
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1473
coverage: 94.878% pattern: 97 before: 381 now: 381
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1543
coverage: 94.905% pattern: 98 before: 381 now: 379
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1482
coverage: 94.905% pattern: 98 before: 379 now: 379
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1465
coverage: 94.905% pattern: 98 before: 379 now: 379
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1910
coverage: 95.066% pattern: 99 before: 379 now: 367
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1437
coverage: 95.066% pattern: 99 before: 367 now: 367
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1698
coverage: 95.066% pattern: 99 before: 367 now: 367
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1495
coverage: 95.079% pattern: 100 before: 367 now: 366
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1419
coverage: 95.079% pattern: 100 before: 366 now: 366
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1550
coverage: 95.079% pattern: 100 before: 366 now: 366
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1826
coverage: 95.079% pattern: 100 before: 366 now: 366
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1712
coverage: 95.079% pattern: 100 before: 366 now: 366
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1573
coverage: 95.079% pattern: 100 before: 366 now: 366
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1492
coverage: 95.106% pattern: 101 before: 366 now: 364
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1869
coverage: 95.106% pattern: 101 before: 364 now: 364
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1499
coverage: 95.106% pattern: 101 before: 364 now: 364
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1529
coverage: 95.106% pattern: 101 before: 364 now: 364
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1510
coverage: 95.106% pattern: 101 before: 364 now: 364
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1578
coverage: 95.106% pattern: 101 before: 364 now: 364
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1878
coverage: 95.106% pattern: 101 before: 364 now: 364
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1470
coverage: 95.106% pattern: 101 before: 364 now: 364
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1563
coverage: 95.106% pattern: 101 before: 364 now: 364
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1637
coverage: 95.120% pattern: 102 before: 364 now: 363
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1444
coverage: 95.120% pattern: 102 before: 363 now: 363
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1494
coverage: 95.120% pattern: 102 before: 363 now: 363
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1551
coverage: 95.120% pattern: 102 before: 363 now: 363
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1945
coverage: 95.120% pattern: 102 before: 363 now: 363
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1623
coverage: 95.120% pattern: 102 before: 363 now: 363
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1684
coverage: 95.120% pattern: 102 before: 363 now: 363
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1539
coverage: 95.120% pattern: 102 before: 363 now: 363
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1519
coverage: 95.120% pattern: 102 before: 363 now: 363
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1463
coverage: 95.120% pattern: 102 before: 363 now: 363
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1579
coverage: 95.120% pattern: 102 before: 363 now: 363
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1573
coverage: 95.120% pattern: 102 before: 363 now: 363
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1409
coverage: 95.120% pattern: 102 before: 363 now: 363
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1512
coverage: 95.120% pattern: 102 before: 363 now: 363
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1836
coverage: 95.120% pattern: 102 before: 363 now: 363
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1556
coverage: 95.120% pattern: 102 before: 363 now: 363
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1646
coverage: 95.133% pattern: 103 before: 363 now: 362
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1527
coverage: 95.133% pattern: 103 before: 362 now: 362
checking valid circuit ... result: 1.

2708
exp_result/ATPG-LS_c880.bench.txt Normal file
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